Abstract: A reload timer circuit comprises an n-bit up/down counter circuit for receiving input data of n bits and providing up/down count data of n bits; an n-bit timer circuit for receiving the n-bit up/down count data and providing timer data of n bits; and a timer period setting means for generating a timer period signal in response to an overflow signal of the n-bit timer data and providing the n-bit up/down counter circuit with the timer period signal. This reload timer circuit automatically sets a reload value by hardware without relying on software, thereby reducing the load on a central processing unit.

Abstract: A frequency divider includes at least three master-slave flip-flops which are connected to each other in stages, each stage including a master flip-flop and a slave flip-flop, to construct a 1/N frequency divider. At least two outputs whose periods are the same but phases are different are taken out from a master flip-flop and a slave flip-flop and combined to obtain a 1/(N/2) divided output signal. As a result, a divided output signal whose period does not vary with time is obtained and, when the N is an even number, an output signal with a duty ratio of 1/2 is obtained. A pulse signal former includes a differential amplifier to which two signals whose periods and pulse widths are the same but phases are shifted by a pulse width and an output obtained by comparing those two signals is output from the pulse signal former. As a result, an output signal whose duty ratio is 1/2 is obtained.

Abstract: Two cascaded eight-bit maskable counters (62) and (64) provide a sixteen-bit output, for instance, to a digital-to-analog converter (10). Each of the counters (62) and (64) is a maskable counter that is operable to mask off a programmable number of the least significant bits therein. The next adjacent bit thereto comprises a virtual least significant bit. During the counting operation, the count is initiated at the virtual least significant bit such that the virtual least significant bit is clocked for each counting cycle. An initial value is first loaded into the counter (62) and (64) on a data bus (74). Thereafter, masked data is loaded into the counters (62) and (64) on the same data bus (74) to define the ones of the least significant bits that are masked off. In such a manner, the overall resolution of the counter can be varied without varying the clock rate to the counter.

Abstract: Frequency division circuits in n stages sequentially 1/2-frequency-divide an input clock signal. Pattern generating circuit generates and issues a plurality of pattern data parallel to each other in synchronism with a frequency-divided clock from the final frequency division stage thereof. Multiplexing circuits in n stages are given a plurality of pattern data and multiplex input pattern data in each stage for each two data. Output clock signals of the n-th through first stage frequency division circuits are supplied to the first through n-th multiplexing circuits via respective delay circuits as multiplexing control clock signals. A retiming circuit is inserted in series to the input of at least one of the multiplexing circuits, and a multiplexing control clock signal applied to said one multiplexing circuit from the corresponding frequency division circuit is given to the retiming circuit as a retiming clock signal.

Abstract: A frequency dividing circuit divides an input signal of an input frequency into an output signal of an output frequency. The frequency dividing circuit comprises first through fourth latch circuits which operate the input signal, respectively. The first latch circuit delays an original signal into a first delay signal. The second latch circuit delays the first delay signal to produce a second delay signal and a first inverted delay signal which has an antiphase relative to the second delay signal. The third latch circuit delays the second delay signal into a third delay signal as the output signal. The fourth latch circuit receives a first OR signal which is produced by logically adding the third delay signal and mode signal which has first and second levels. The fourth latch signal delays the first OR signal into a fourth delay signal and produces a second inverted delay signal which has an antiphase relative to the fourth delay signal.

Abstract: An asynchronous ripple counter counts from a predetermined binary value to zero in response to an input clock signal. Zero detection logic is coupled to the ripple counter for detecting, from a most significant bit to a least significant bit of the ripple counter, when the counter has counted to zero. Both the counter and the zero detection logic receive and store the predetermined binary value. The monitoring of the ripple counter's digits from MSB to LSB prevents false detections of zero states in the ripple counter and allows the ripple counter to be extended to an arbitrarily large number of bits without sacrificing the maximum input clock frequency.

Abstract: An incrementer circuit includes a plurality of input terminals for receiving an address data, having a plurality of bits, to be incremented, a carry signal generating unit for generating a carry signal for each bit of the address data and a plurality of output terminals where an incremented address data appears. The carry signal generating unit includes a detector for detecting whether or not all of a predetermined number of less significant bits of the address data are at high level and outputs a detection signal if so. In response to this detection signal, a carry signal is generated and supplied to a bit which is more significant than the most significant bit of the predetermined number of less significant bits by one bit.

Abstract: A network for detection and correction of errors in a digital signal data stream, using an encoded code remainder that augments the data stream. The network utilizes a linear shift feedback register and a data register that works as a shifter or as a counter in assisting the error detection/correction process. Although the digital signal is in the form of serial data, the data register works with bytes, rather than bits, in a parallel arrangement so that the processing time is substantially reduced.

Abstract: An inventive presettable synchronous predecoded counter which provides predecoding and counting in a single circuit, with an inventive dual-input flip-flop included in the design. This predecoded counter is used advantageously to sequentially access elements in a semiconductor memory array. This invention offers small size and simple design.

Abstract: A programmable counter or frequency divider includes the combination of a fixed modulus prescaler (110) and a programmable divider (120, 130, 140, 150, 160) in which the prescaler provides more than a single clock phase to the programmable divider and the programmable divider utilizes the multiple clock phases to allow operation in a true fractional-integer mode. The overall combination of the prescaler and programmable divider functions as a programmable divider for which the minimum increment in the overall divider modulus is less than the prescaler modulus, but the maximum clock frequency usable is the maximum clock frequency of the prescaler.

Abstract: The synchronization circuit of the preferred embodiment is a T flip flop which has a first output which changes state on the leading edge of the clock signal, and a second output which changes state on the trailing edge of the clock signal. The T flip flop has an exclusive OR gate input in which the T input is combined with the first output. The output of the exclusive OR is coupled to an internal node when the clock signal is at a first logic state, and isolated from the internal node when the clock signal is at a second logic state. The internal node is coupled to the first output when the clock signal is at the second logic sate and isolated from the internal node when the clock signal is at the first logic state. The first output signal is coupled to the second output signal when the clock signal is at the first logic state, and isolated from the second output terminal when the clock signal is at the second logic state.

Abstract: Error rates above a given threshold are detected by initiating a counter to count a group of n bits on each occurrence of an error bit. The counters are inspected on each occurrence of an error to see whether the counter initiated x error bits earlier is still counting. If the counter is still counting the error rate is above a threshold of x error bits in a group of n bits in a serial stream.

Abstract: A high speed counter circuit for counting electrical pulses includes a master/slave flip-flop at the input stage of the counter. An AND gate logically ANDs the pulses being counted with the master output to produce a first gating signal. A plurality of cascade coupled flip-flops each having a slave and an inverse slave output are provided. The clock input to each cascade coupled flip-flop is produced by the logical OR of the electrical pulses being counted, the first gating signal and the slave output of all preceding flip-flops of the counter. The counter output is provided by the inverse slave output of each flip-flop.

Abstract: A loadable N-bit ripple counter having N bit subcircuits that each inlude a flip-flop and a bit loading element. The flip-flop output is controllable to a known state when a flip-flop control signal is asserted. The bit loading element is connected to receive the flip-flop output and a bit input of a multibit number being loaded and to provide a bit output of the counter, the bit output being controlled by the states of the flip-flop output and the bit input, and, except for the most significant bit, serving as a clock for the next more significant bit subcircuit.

Abstract: A high speed CMOS binary up/down counter having a 200 MHZ clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. The counter performs in an up-count mode or a down-count mode in accordance with the state of a mode select signal. Each stage of the 4-bit counting section comprises a propagate/kill/generate gate for determining the status of a carry signal to a next stage, except the last stage of a 4-bit section, which does not require such a gate because it is coupled to a carry-forward generator along with the outputs from the other preceeding stages in the section. Each 4-bit section performs the counting function through a successive process of modulo-two sums of a lower order carry and the current state of a counter stage without the need for cumbersome gating structures.

Abstract: A pipeline binary updown counter is comprised of simple stages that may be readily replicated. Each stage is defined by the Boolean logic equationA.sub.n (t)=A.sub.n (t-1).sym.[(U.multidot.P.sub.n)+(D.multidot.Q.sub.n)]where A.sub.n (t) denotes the value of the nth bit at time t. The input to the counter has three values represented by two binary signals U and D such that if both are zero, the input is zero, if U=0 and D=1, the input is -1 and if U=1 and D=0, the input is +1. P.sub.n represents a product of A.sub.k 's for 1.ltoreq.k.ltoreq.-1, while Q.sub.n represents the product of A's for 1.ltoreq.k.ltoreq.n-1, where A.sub.k is the complement of A.sub.k and P.sub.n and Q.sub.n are expressed as the following two equationsP.sub.n =A.sub.n-1 A.sub.n-2 . . . A.sub.1Q.sub.n =A.sub.n-1 A.sub.n-2 . . . A.sub.1which can be written in recursion form asP.sub.n =P.sub.n-1 .multidot.A.sub.n-1Q.sub.n =Q.sub.n-1 .multidot.A.sub.n-1with the initial values P.sub.1 =1 and Q.sub.1 =1.

Abstract: A stable binary counter as applicable to synchronous counters, to frequency dividers and more particularly to microwave integrated circuits is constituted by a plurality of elementary counters mounted in cascade. Each elementary counter is formed by a half-adder having two inputs, one "sum" output and one "carry" output. The "sum" output is connected to the input of a master-slave flip-flop, the output of which is connected in a feedback loop to one input of the half-adder. The master and slave flip-flops are controlled by the two complementary waveforms of a single clock signal. The "carry" output of one half-adder is connected to the input of the following half-adder.

Abstract: A data conversion circuit is constructed in such a manner that a plurality of flip-flop series, each including tandem connected master/slave flip-flops, are provided and driven by plural phase numbers of clock signals which have no overlap therebetween, so that a parallel data is obtained with a serial data supplied to the flip-flop series, or a serial data is obtained with a parallel data supplied to the flip-flop series. The clock signals employed here have no overlap between each of the corresponding phases of the signals.

Abstract: In a flip-flop circuit, input and output terminals of two inverters connected between corresponding data input terminals and corresponding data output terminals are cross-connected. Latch switches are inserted between the inverters and the corresponding data input terminals. Hold switches are inserted in the cross-connected portion of the two inverters. The latch switches are turned on/off in synchronism with a latch input while the hold switches are turned on/off in synchronism with a hold input.

Abstract: A 1.2 .mu.m CMOS binary counter having a 200 MHz clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. Each bit stage within a 4-bit counter section uses the current state of such stage to determine what happens in the next stage. Each 4-bit section performs the counting function through a successive process of additions of a lowest order carry-bit input. A count enable signal serves to enable the count process as well as serving as a carry-bit input to a first stage. Count enable effects a counter reset when in a logic "zero" state. Once the count enable is raised to the logic "one" state, the process of counting begins with the rising edge of the first clock pulse. As long as the count enable is maintained, counting continues. When the count enable is reduced to a "zero" state, counting is terminated, with a counter reset occurring on the next sequential rising edge of the clock.

Abstract: An up/down counter device includes a D-type flip-flop circuit for producing a count signal of the 0th bit in synchronism with a clock signal, and 1st to n-th flip-flop circuits for producing count signals of the 1st to the n-th bits in synchronism with a clock signal. The first logic circuit is connected between the output of the D-type flip-flop circuit and the JK terminals of the first flip-flop circuit. The first stage logic circuit includes a first logic circuit section supplied with an up/down mode signal and the output signal of the D-type flip-flop circuit, and a second logic circuit connected in series with with the first logic circuit. Each of the 2nd to the n-th stage logic circuits includes a first logic circuit which is connected between the output terminal of the prestage flip-flop circuit and the JK terminals of the post stage flip-flop circuit, and a second logic circuit section connected to the first logic circuit.

Abstract: A bipolar clock-controlled bistable multivibrator circuit arrangement having a static memory cell formed of a D-master-slave flip-flop with a first inverted output signal fed back to a data input and with feedback loops, respectively, for intermediately storing output signals of the master and the slave. A dynamic memory cell is formed of the D-master-slave flip-flop with a second inverted output signal fed back to the data input. The second inverted output signal has gate propagation times performing intermediate memory functions in place of the feedback loops and includes a synchronizing device connected between the static and the dynamic memory cells. Means are provided for setting the circuit of the static memory cell in operation at relatively high clock frequencies. Thereby the useful frequency range of the multivibrator is at least doubled.

Abstract: A weighted event counting circuit comprises a cascade connection circuit composed of a plurality of frequency dividing circuit means and a plurality of coincidence detecting circuit means inserted between the frequency dividing circuit means, and input circuit means to supply digital data representing the occurrence of plural events to the coincidence detecting circuit means. The number of occurrence times of the plural events is counted and totalized with weighting.

Abstract: A multi-digit counter circuit performs both successive data production function and non-successive data production. Successive data is produced by an increment or decrement operation according to a first carry (borrow) signal. Non-successive data is produced by a control circuit which applies a second carry (borrow) signal independently of the first carry (borrow) signal to an arbitrary selected digit or digits. The arbitrary digit is designated according to the distance between the preceding data and the following data to be produced.

Abstract: An improved, high-speed frequency divider circuit (32) is presented. The frequency divider circuit (32) is comprised of three D-type flip-flops (34, 36 38). The three flip-flops (34, 36, 38) are clocked synchronously for higher speed of operation. The design of the frequency divider circuit (32) embodies a sagacious state assignment to minimize the number of bits that change state on any given state transition, thus reducing the possibility of faulty circuit operation.

Abstract: A synchronous binary circuit comprising a counter including J-K flip-flops constituting lower l bit stages and higher m bit stages, first logic means for feeding, to J and K input terminals on each of flip-flops among the lower l bit stage flip-flops higher than the second bit stage, an AND of non-inverted outputs of all the lower stage flip-flops than the pertinent stage, second logic means for feeding, to the J and K input terminals of the first stage flip-flops among the higher m bit stage flip-flops, a first logical product of the non-inverted output of a one bit lower stage flip-flop and non-inverted outputs of the first to (l-1)-th bit stage flip-flops among the lower bit stage flip-flops, and third logic means for feeding, to the J and K input terminals of flip-flops among the higher m bit stage flip-flops higher than the second stage, a second logical product of non-inverted outputs of the lower first to (l-1)-th bit stage flip-flops and a third logical product, the third logical product being a logic

Abstract: A counter for counting clock pulses and having a plurality of output bits successively numbered from a first output bit to a highest output bit. The counter includes a plurality of bistable devices, one bistable device being associated with each output bit, and each bistable device including a clock input for receiving clock pulses to be counted, and an output for providing one of the output bits and its complement. The bistable device which is associated with the first output bit toggles with the receipt of each clock pulse to be counted. The counter also includes a decode section responsive to the outputs of the plurality of bistable devices for providing decoded signals, and a select section for receiving the clock pulses to be counted and responsive to the decoded signals and the complement of the first output bit. The select section selects which of the plurality of bistable devices associated with the second and higher output bits will toggle on the receipt of the next clock pulse.

Abstract: A binary up/down counter stage particularly suitable for CMOS implementation. The counter stage includes an exclusive OR gate having a first input for receiving a toggle signal, a flip-flop having a data input coupled to the output of the exclusive OR gate and Q and Q outputs, the Q output of which provides the stage output and a feedback to the second input of the exclusive OR gate, and a multiplexer having first and second inputs coupled to the Q and Q of the flip-flop respectively, the output of the multiplexer being logically ANDED with a toggle-in signal to provide a toggle-out signal for a further counter stage in cascade.

Abstract: A master-slave flip-flop device wherein the master segment employs function and load isolated outputs driven in parallel with cross-coupled latch transistors is described. Signal feed forward may also be provided from a similarly isolated output of the master segment to a device output gate which also receives the otherwise final output of the slave segment. The device is found to exhibit a minimized duration of the undesired metastable state of the master segment and to, thereby, enhance propagation speed in which a stable state is established.

Abstract: A binary counter consists of a plurality of unit stages each having a bistable circuit, a buffer circuit for generating an output corresponding to an output state of the bistable circuit, a switching circuit for supplying an output of the buffer circuit to the bistable circuit, and a coincidence gate for supplying a clock signal to the next unit stage in accordance with the predetermined output state of the bistable circuit.

Abstract: An 8.5 divider comprises a first and second 1/2 dividers to produce output pulses having phases different from each other by 90.degree., a first logic gate producing output pulses having a repetition frequency of a half of the input pulses, a third and fourth 1/2 dividers connected in series and dividing twice the output pulses of the first logic gate by two, a fifth 1/2 divider receiving the output of the fourth 1/2 divider, a second logic gate detecting the simultaneous presence of the outputs of the second, third and fifth 1/2 dividers to invert the phase of the output pulses of the first 1/2 divider and a third logic gate detecting the simultaneous presence of the outputs of the first and third 1/2 dividers and the inverted output of the fifth 1/2 divider.

Abstract: A serial fast propagation transmission switch responsive to a propagate input control signal to transmit a signal from the input to the output terminal in combination with a double inverting logic parallel to the transmission switch to limit the line impedance to a single stage impedance subsequent to the serial transmission.

Abstract: A ripple counter circuit is provided that reduces propagation delay inherent in flip-flops, and therefore, reduces the current required. A first flip-flop has a clock input responsive to a clock signal and a D input connected to a Q output. A second flip-flop has a clock input ANDed to a Q output of the first flip-flop and the clock signal. A propagation delay normally associated with the first flip-flop is eliminated from the Q output of the second flip-flop.

Abstract: A binary counter consists of some unit stages having a first pair of coincident gates composed of a first and a second coincident gates, a first input terminal of each being cross-coupled with the other's output terminal, and a second pair of coincident gates composed of a third and a fourth coincident gates, a first input terminal of each being cross-coupled with the other's output terminal.

Abstract: There is shown and described a new and unique counter mechanism or circuit which includes feedback latches, in cascade, and which monitors a "carry-in" signal which selectively causes the latch to toggle. When the contents of the latch is a binary 1, the carry-in signal propagates through the counter as a "carry-out" signal. Counting by the circuit occurs when the count input and carry-in signals are active.

Abstract: A first variant using conventional ratio-type two-phase design with nonoverlapping clock signals consists of a first inverter (I1), a complex gate (KG), a first transfer transistor (T1), a second inverter (I2), and a third inverter (I3) connected in series with respect to the signal flow. The complex gate (KG) consists of two NORed AND elements (U1, U2). The output of the second inverter (I2) is the count-up output (VA), and that of the third inverter (I3) is the count-down output (RA). The count-up output (VA) is coupled through a second transfer transistor (T3), controlled by the second clock signal (F2), to the first input of the first AND element (U1), whose second input is connected to the output of the first inverter (I1).

Abstract: A multi-stage logic circuit employing integrated MOS-circuit techniques having gates to produce carry signals between stages where the gates which transfer the carry signals are designed as transfer-gates. Specific circuits are shown for full adders, comparators, synchronous binary counters, forwards-backwards synchronous binary counters and forwards-synchronous counting decades.

Abstract: A plurality of two stage Gray code counters are connected in series to generate a multiple bit pseudo Gray code count C.sub.0, C.sub.1, . . . , C.sub.7. A binary count B.sub.0, B.sub.1, . . . , B.sub.7 is then generated by using the odd subscripted bits C.sub.1, C.sub.3, C.sub.5, C.sub.7 of the pseudo Gray code as the binary count bits B.sub.1, B.sub.3, B.sub.5, B.sub.7 and generating the even subscripted bits of the binary count B.sub.0, B.sub.2, B.sub.4, B.sub.6 by Exclusive ORing the odd and even position counts of each two stage Gray code counter together in Exclusive OR circuits.

Abstract: A switched frequency divider is disclosed comprising an array of bistable devices which are linked together so as to propagate through the array a low or high signal applied to an input to the array, first gating means for inserting at least one more bistable device into the array, and second gating means for making such an insertion only when the output of the array completes a cycle. To provide for an output wave form that has approximately a 50 percent duty cycle, the bistable devices are coupled togther in the form of a Johnson counter. To permit a change in the divisor only upon the completion of an output cycle, the second gating means is a bistable device which reads an incoming control signal only when the output of the Johnson counter makes a specified change in state. Advantageously, the switched frequency divider may be used as an FSK modulator to generate different AC frequencies from a single AC input signal in response to a digital data signal applied to the divider as said control signal.

Abstract: A method and apparatus is described for dividing a clock frequency by any odd number to obtain a symmetrical output. Generally, some dividers in a chain of divide-by-two dividers are designated as controlled dividers and others are designated as uncontrolled dividers. The clock input of each controlled divider receives the output of an exclusive NOR gate, the inputs to which include the output of the last divider in the chain and either the clock signal or the output of a preceding divider, depending on certain criteria. The clock input of each uncontrolled divider receives the output of an immediately preceding divider. With this arrangement, the last divider in the chain develops a divided output which is symmetrical.

Abstract: The ring counter of this invention is self-initializing and is operable at a clock frequency corresponding to four gate delays and comprises a plurality of master of slave flip-flops, in which this high speed capability is attained by using non-inverting feedback between the first and last flip-flops and by operating the master and slave of each in complementary fashion without requiring the use of a complementary clock signal. The non-inverting feedback takes advantage of the inherent delay between the response of the complementary outputs of each flip-flop.

Abstract: An EFL D-type latch employing an EFL storage cell (17) controlled by a two-level tree of differential transistor pairs (12, 14 and 32, 34). Also described are counter cells, up counters, down counters and up/down counters, including binary, hexadecimal and BCD types, which can be formed from master/slave combinations of D-type and D-type latches. Examples of specific three-level and four-level EFL realizations of the counter cells are also described.