Abstract: An electrical cable reel module for a drone includes a bracket adapted to be firmly fixed to the drone. A reel body is movably and rotatably mounted on the bracket. A first driving device is mounted on one side of the bracket to drive the reel body to rotate and a second driving device is mounted on the other side of the bracket to drive the reel body to move linearly in a first direction. A third driving device is mounted on the bracket to drive the reel body to move linearly in a second direction opposite to that of the first direction. At least one positioning device is mounted among the reel body, the first driving device and the second driving device to selectively drive the reel body to rotate and prevent the reel body from movement and rotation.

Abstract: In a ramp signal producing apparatus, a ramp signal is produced under low clock signal frequency in a compact circuit arrangement. Luminance control and a white balance control are carried out by the ramp signal in a liquid crystal display. The ramp signal producing apparatus is comprised of: an up/down counter for either counting up, or counting down a clock signal supplied thereto; amplitude amount converting means for converting the amplitude of the supplied clock signal into such an amplitude value corresponding to the count value of the up/down counter and for converting the amplitude value in such a manner that a change amount per one count value is increased during the count down operation by the up/down counter; and ramp signal producing means for producing such a ramp signal with an amplitude corresponding to the converted amplitude value.

Abstract: An N stage Gray code generator includes an N stage binary counter having an input for receiving clock pulses to be counted and providing N outputs forming an N bit binary code. N minus 1 storage stages capable of being toggled between a logic "1" and a logic "0" state, each having a toggle input to cause them to toggle, have their toggle inputs coupled to the outputs of the first N minus 1 stages of the binary counter. The outputs of the N minus 1 storage stages form the first N minus 1 Gray code outputs and the most significant output of the binary counter provides the most significant output of the Gray code generator.

Abstract: In a binary counter made using the I.sup.2 L technique, the realization of different gate types is complicated, because only NAND gates can be obtained directly. According to the invention, a particular circuit construction is indicated, which is constructed according to the I.sup.2 L technique, is very simple and requires only a few gate transit times so that a comparatively high switching speed can be attained. In the circuit construction of the invention, both the flipflops and their associated combinatorial networks are fabricated in the I.sup.2 L technique, using only NAND gates. Nevertheless, because of the particular circuit configuration of the invention, all of the necessary internal signals can be generated in an efficient manner.

Abstract: An analog-to-digital converter quantizer and bidirectional counter using superconducting quantum interference devices (SQUID's) as the principal elements. A double-junction non-latching SQUID is used as a quantizer to produce unipolar output pulses on two different output lines, indicative of positive and negative increments of change in an analog signal current. The unipolar pulses are then counted in a bidirectional counter that employs double-junction non-latching SQUID's as counter stages and as logic gates for the propagation of carry and borrow signals from stage to stage.

Abstract: A linear array of bistable data latches and logic gates arranged to count the binary transitions, both low to high and high to low, of a clock signal and provide a threshold style output code, characterized along the array by high logic states on one side of the threshold point and low logic states on the opposite side. Each latch in the array is permitted to set when a clock transition occurs after the preceding latch has set or to reset when a clock transition occurs after the succeeding latch has reset. Clock phasing and count enable/disable logic may be included along with direct set/reset inputs in order to accomplish parallel and/or ripple preset/clear functions or other output code modifications.

Abstract: A proportional digital control system for radio frequency synthesizers using binary coded decimal control to a frequency synthesizer tunable in contiguous small interval increasing or decreasing steps throughout the frequency bandwidth range of operation. A fine tune dial switch circuit generates a two signal output with one a step count signal and the other an up-down control signal generated only upon rotation of the fine tuning dial and with the signal pulse rates thereof a direct function of the rate of fine tune dial turning. The up-down control signal is an up or down signal input to up-down pulse counting to BCD output circuits as determined by phase relation thereof to the step count signal and with the phase determined by direction of fine tune dial turning clockwise for up count and counterclockwise for down count.