Abstract: A system and method for providing improved resolution in the measuring the pulse width of digital signals comprising counting the integral number of measuring clock pulses covered by said digital pulse and triggering a chain of cascaded high resolution delay elements from the trailing edge of said measuring clock pulses. Further, the invention measures the delay count obtained from said chain of cascaded delay elements from the trailing edge of the last measuring clock pulse up to the end of said digital pulse, and adds said measured delay count to said integral measuring clock pulse count to obtain the total width of said digital pulse.

Abstract: This invention relates to a measurement system for determining the running time that a person need to run over one of a plurality of selectable different out-and-back courses, departing from a common starting point that is the finish point at the same time, wherein different turning points are provided by which the particular out-and-back course to be run is established. The times consumed are detected and evaluated individually.

Abstract: Random number generators are used for entertainment in gambling, lotteries and video gaming devices. True Random Number Generators, as are now currently defined, must be actuated by a physical noise source, typically based on the uncertainty of the phase differences of a stable and an unstable autonomous oscillator. In this invention an autonomous random frequency modulated oscillator driven by a self contained pseudo-random number generator outputs three loosely correlated random binary streams. Included in the invention is a hardware method for proving wandering phase differences and also the existence of a colored random distribution of concatenated nibbles.

Abstract: A method for determining the rotation speed of a rotating shaft that has associated with it a means that has markings which produce an electrical signal upon being carried past a sensor element of a sensor, the sensor encompassing an evaluation device that counts the markings carried past the sensor element within a gate time and transfers them to a control unit as a numerical value. The gate time is derived from a time increment, and a pulse having an actual time duration derived from the time increment is transferred to the control unit and is compared by the control unit with a target time duration, the numerical value being corrected using a correction value that is ascertained from a comparison of the actual time duration with the target time duration.

Abstract: A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device associated with each respective counter device is additionally set in response to an overflow condition. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits. An operatively coupled control device monitors each associated overflow bit device and initiates incrementing a second count value stored at a corresponding memory location in response to a respective overflow bit being set.

Abstract: A time interval measurement apparatus and method counts the total number of full clock time periods between two measurement signals. Clock fractional time periods are generated between each of the two measurement signals and the next leading edge of a full clock time period. The total number of full clock time periods and the clock fractional time periods are converted to a time equivalent measurement and combined to generate the total time interval between the two measurement signals.

Abstract: A circuit and related method for distributing events in an event stream (i.e., an electronic signal having a plurality of rising edge transitions and falling edge transitions). The circuit distributes the events in a primary event stream across multiple secondary event streams in such a way that the event rate in each of the secondary event streams is lower than the event rate in the primary event stream, but the relative timing of the events in the primary event stream is maintained in each of the secondary event streams. The secondary event streams can then be provided to respective timestamp circuits, which record the times at which events occur in the secondary event streams. Since the relative timing of the events in the primary event stream is maintained in each of the secondary event streams, the multiple timestamp circuits collectively record the times at which events occur in the primary event stream. The circuit and related method can be used when debugging/testing semiconductor devices.

Abstract: A local timer includes a dividing counter which counts a first clock and outputs a reference counting signal divided from the first clock; a timing synchronizing timer which counts a timing synchronizing timer value in synchronization with a reference timer responsive to the reference counting signal; a first buffer which stores a counted value of the dividing counter in synchronization with a second clock, when operation is by the first clock; a second buffer which stores the timing synchronizing timer value in synchronization with the second clock, when operation is by the first clock; a first adder which adds a first or second offset value to the stored value in the first buffer in synchronization with the second clock, when the first clock is suspended; and a second adder which adds a set value to the timing synchronizing timer value responsive to a carry from the first adder.

Abstract: A technique for implementing an extended bit timer with a time processing unit (TPU), without using the channel hardware of the TPU includes a number of steps. A timer of the TPU is periodically read to determine the value of the timer. A counter is incremented when rollover of the timer has occurred and a coherency flag is de-asserted after the timer transitions through a first count. The coherency flag is asserted after the value of the timer transitions through a third count and the value of the timer is combined with the value of the counter to provide a current count. When the coherency flag is asserted and the value of the timer is equal to or between the first and second counts, the current count is adjusted.

Abstract: A self test for a counter system in an integrated circuit includes a clock coupled to counters in a plurality of counters. A first counter in the plurality of counters has a first counter output and a first counter rollover. A second counter in the plurality of counters has a second counter output, a second counter rollover less than the first counter rollover, and a second counter rollover signal that is active when the second counter has rolled over. A comparison circuit having inputs coupled to the first and second counter outputs, compares the first and second counter outputs to produce a counter error output signal. A latch latches the counter error output signal in response to the second counter rollover signal being inactive and the counter error output signal indicating a difference in the first and second counter outputs. Counters may be segmented to reduce a number of digits.

Abstract: Multi-phase clock time stamping for improving time stamp resolution is provided. One of many possible embodiments is a method for generating a time stamp having an improved time resolution for an event signal. Briefly described, one such method comprises the steps of: receiving an event signal for which a time stamp is to be generated; generating a first pulse signal having a pulse width defined by the event signal and a first clock signal; generating a second pulse signal having a pulse width defined by the event signal and a second clock signal; and determining which of the first pulse signal and the second pulse signal is to be used for generating the time stamp for the event signal.

Abstract: The present invention provides a clocking system such that the magnetic sensor can detect the external magnetic field from the magnetic member that is rather far apart therefrom without increasing the sensitivity of the magnetic sensor excessively and without making the magnet constructing the magnetic member strong excessively.

Abstract: A digital counter with a dial position having a hardware part which determines the n lowest-value bits of the dial position and a software part which determines the remaining higher-value bits of the dial position includes first and a second software parts as the software part with the dial position being a combination of the first software part and the hardware part when the hardware part is in a first counting range, and being a combination of the second software part and the hardware part when the hardware part is in a second counting range.

Abstract: The invention provides an electrooptic device and an electronic apparatus, in which the electrical characteristics of many thin-film switching elements formed in a substrate to support an electrooptic material can be accurately inspected. The invention also provides a method for making the electrooptic device. In a TFT array substrate of a liquid crystal device, an inspection TFT is formed in one of dummy pixels disposed at the periphery of a pixel region. A pixel electrode connected to a drain region of the TFT functions as a first inspection pad. In an adjacent dummy pixel, the pixel electrode electrically connected to an extended portion of a data line functions as a second inspection pad. In another adjacent dummy pixel, the pixel electrode electrically connected to an extended portion of a scan line via a junction electrode functions as a third inspection pad.

Abstract: An apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. Each time value from the set of time values is uniquely associated with a detected edge transition from the input signal. The memory is coupled to the edge detector. The memory is configured to receive from the edge detector the set of time values. The memory is configured to store the set of time values. The pulse-input engine is coupled to the memory. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of the time values stored in the memory.

Abstract: The invention relates to a method for overload-free driving of an actuator, in which an activation counter is incremented or decremented each time an activation request signal occurs, in which, depending on each occurrence of an activation request signal, a drive signal for the actuator is generated if the counter reading of the activation counter is less than or greater than a predetermined maximum or minimum counter reading, in which the counter reading is in each case decremented or incremented if the time since the last generation of a drive signal or since the deactivation of the drive signal is greater than or equal to a predetermined or predeterminable interval time or if the time since the last decrementing of the activation counter is greater than or equal to the interval time.

Abstract: A data word is used to represent the total amount of time duration or predefined events a device has experienced during its lifetime. The data word is incremented count by count while the device is powered on and each updated data word is backed up to a non-volatile memory. A two-version redundancy scheme is employed to ensure failsafe backup and restoration of the data word. At any time at least one valid version of the data word exists in the non-volatile memory. In another aspect, a partitioned memory configuration is implemented to backup the data word and its associated error correction code to the non-volatile memory. In this way the non-volatile memory is able to store a range of counts whose maximum number far exceeds the memory's endurance limit.

Abstract: A technique for estimating current consumption of an electronic device such that current consumed during reception of bursts is utilized in calculating the remaining battery power. By determining the time duration of each reception burst and the charge consumed during each burst, the total charge consumed by the reception bursts is calculated. The total charge calculated is used to determine the remaining battery power.

Abstract: In a thermal developing method for continuously and thermally developing thermal developing sheets which have a latent image formed thereon by exposure and various sizes, a minimum temperature recovery time required for thermally developing a next thermal developing sheet is determined from physical information about a thermally developed sheet, and the next thermal developing sheet is started to be developed after the minimum temperature recovery time passes.

Abstract: A measurement system and method for determining a revolution rate of a rotating gear is described. Such a rotating gear can be, for example, a turbine or compressor. The described measurement system and method, for example, can perform highly accurate measurements and can be a fault tolerant system providing high reliability. In one embodiment, an apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of time values stored in the memory.

Abstract: An operating property of the integrated circuit, such as its speed class, value is determined during testing. In order to identify the integrated circuit with a value for its operating property, there are provided at least two registers whose outputs are logically combined bit by bit via OR gates. The registers are preferably programmable with fuses. In a first test run, the first register is programmed with the ascertained value of the operating property, and the second register is correspondingly programmed in a second test run. The logic combination enables the less significant value of the operating property to predominate. The storage of this value on the integrated circuit itself simplifies the later identification on the housing of the integrated circuit.

Abstract: Systems and methods for efficiently and accurately determining a speed of a faster clock having unknown frequency using a slower clock having a known frequency. A series of measurement pairs are taken from the clocks; each measurement pair including one measurement from the slower clock and one measurement—at the same time—from the faster clock. A lower bound and an upper bound for the measurement pairs are determined. The lower bound and the upper bound are averaged to derive a calibration variable that indicates a number of clock cycles that occur on the faster clock during one cycle of the slower clock. The calibration variable is used to time various processes in a computer system.

Abstract: An integrated circuit according to the present invention includes application-specific circuitry and an embedded counter assembly capable of measuring the frequency of one or more clock signals, which may be generated internally by the integrated circuit or externally by one or more sources external to the integrated circuit. The embedded counter assembly utilizes a reference clock signal having known characteristics, and measures the frequency of an unknown clock signal based upon the reference clock signal. The embedded counter assembly is capable of measuring the frequency of internal clock signals that are otherwise inaccessible via external output pins.

Abstract: A timer circuit for providing output pulses of an adjustable duration based upon stored decode parameters. The circuit has a timer element which generates a periodic timing signal. Preferably the frequency of the periodic timing signal is also adjustable. A frequency divider is clocked by the timing signal and provides a plurality of frequency divided outputs. A decode circuit combines selected ones of the frequency divided outputs based upon decode parameters and generates a timer circuit output pulse having a duration determined by the frequency divided outputs selected by the decode parameters. The decode parameters are stored in a non-volatile data storage unit so that the timer output pulse will remain the same after power interruption.

Abstract: A timer control circuit includes timers that perform count operations. A signal selection circuit selectively passes underflow signals supplied from the timers, based on control signals. A flip-flop is supplied with an output of the signal selection circuit section as a toggle signal.

Abstract: The timer control circuit includes plurality of timers that perform predetermined count operations. The signal selection circuit section allows to selectively pass underflow signals supplied from the timers based on the control signals. The flip-flop is supplied with an output of the signal selection circuit section a toggle signal.

Abstract: A method and apparatus for detection of missing pulses from a repetitive pulse train including signal detection circuits for capturing the rising and/or falling edges of an input signal, time-stamping the captured edges, calculating the maximum and minimum instantaneous frequency over a specified time period, and displaying such frequency values. Instantaneous frequency values between any two adjacent edges are calculated based upon the time-stamps of the edges. The instantaneous frequency values in a specified time period are then sorted to find the minimum and maximum frequency values for that time period. These instantaneous frequency values are displayed in the form of a histogram evidencing the occurrence or lack of occurrence of missing pulses from the input signal.

Abstract: A phase detector with a linear gain characteristic includes two exclusive-OR gates with inputs connected to an input signal and an inverted input signal and a reference signal in a phase locked loop. The outputs of the exclusive-OR gates are connected to a plurality of switches. The switches are connected to a plurality of resistors and the resistors are connected together to form an output signal. Switches and resistors are selected in complementary pairs by a gain select function to provide a linear gain characteristic for the output signal.

Abstract: A timing circuit records the duration of intervals between a plurality of events in a data stream. The circuit includes at least two timing channels, each arranged to generate a signal representing time elapsed between events. The rate of change of the signal generated by each timing channel varies with increasing interval duration, and the timing channels are arranged such that each event terminates the operation of one timing channel and initiates operation of another timing channel.

Abstract: A system and a method are characterized in that the method of detection can be configured by varying a size and/or a position of a time slot to be taken into consideration for the detection and/or by varying relevant bits of the counts to be compared. This makes it possible to individually adapt the detection method to various or varying requirements at any time and with a minimum of expenditure required.

Abstract: A semiconductor circuit is provided including circuitry for producing a pulse. A plurality, n, of delay elements are provided each enabled and disabled in parallel by the pulse. Each delay element is adapted to transmit the pulse from an input to an output, with the pulse reaching the respective outputs at different times. A plurality, n−1, of detectors is provided each having an input coupled to an input of a corresponding delay element. Each detector is adapted to set a state of its output to a predetermined state, from a plurality of states, in response to receiving a portion of the pulse. The outputs of the detectors are coupled to output pins of the semiconductor circuit. A tester is provided that is adapted to couple to the semiconductor output pins and detect the state of the detector outputs.

Abstract: An event counter circuit including an input signal coupled to a frequency divider circuit that can be cleared by an external signal, a multiplexer coupled to the divider circuit driven by an output edge and its inverse, and a counter circuit coupled to the multiplexer driven by outputs of the multiplexer.

Abstract: A watchdog timer includes an instruction decoder, a delay circuit and a counter. The instruction decoder decodes a watchdog timer initialization instruction regularly executed to generate an instruction pulse for initializing the count of the counter. The delay circuit delays the rising edge of the instruction pulse, and supplies the delayed instruction pulse to the counter as a signal for initializing the count. The delay circuit prevents the pulse signal from being supplied to the counter when the operation frequency of the microcomputer is high or when the supply voltage to the microcomputer is low, so that the count of the counter overflows, and the overflow signal causes the microcomputer to be reset. This makes it possible to reset the microcomputer before it runs away, thereby solving a problem of a conventional watchdog timer in that the microcomputer can produce, if it runs away, an unexpected signal from its port before it is reset, and hence can impair the security of the system.

Abstract: A counting apparatus having excellent fail-safe characteristics can be used in a rotation-stopped detection apparatus. As a first feature, timing of a high-frequency signal P2 is carried out by a counter 1 after completion of a counting of pulse signals P1. When the frequency of the timing output for the high-frequency signal is a predetermined value, a judgment signal, indicating that the counting is normal, is generated by a frequency discriminating circuit 30. As a second feature, a counter 100 is preset using a preset signal. Then, after verifying by an output from a self hold circuit 102 that the counter 100 has been reset, a counting output is generated from a self hold circuit 104. As a third feature, the counting apparatus is used as timer circuits 203, 300, 400, and the generation frequency of a rotation detection pulse signal IP based on a sensor signal, is obtained to thereby detect a rotation-stopped condition of a rotating body.

Abstract: An improved speed indication method for a sensor that develops one or more electrical pulses per unit movement of a movable part, wherein the indicated speed is based on the number of speed pulses generated per unit time, but is constrained by a limit function based on the time elapsed without the generation of a speed pulse. When the pulse generation rate falls below the update rate of the speed indication, a maximum possible speed based on the duration of the “no pulse interval” is computed, and the indicated speed is reduced based on the computed maximum. When the next pulse occurs, the speed indication is updated based on the lower of a new speed calculation and the computed maximum speed. If speed pulses continue to be received, the computed maximum is no longer used as a limit, and the speed indication is updated in accordance with the pulse based speed calculation.

Abstract: An athletic training device including a housing. Also included is light or speaker mounted on the housing for providing an indication upon the actuation thereof. At least one impact sensor is mounted on the housing for actuating the indication means upon being struck by a user.

Abstract: A time period (Td) is generated with a high accuracy and a high resolution. At a starting instant (ti) of the time period (Td), an analog integration operation (3) is started to generate an integration value (ios). At a certain instant (t1), the analog integration operation is interrupted to start counting (2) clock pulses (Clk). A selected number (N;N2) of clock pulses (Clk) is counted to obtain a sub-period (T2). The analog integration operation is resumed at the end of the sub-period (T2) at the integration value (ios) reached at the start of the sub-period (T2). The analog integration operation finishes at an end instant (td) of the time period (Td) at which the integration value (ios) crosses a reference value (Ref).

Abstract: A postage metering system includes a device to monitor the passage of a unit of time, a calendar profile, a system date and a control system. The calendar profile has parameterized data including day, month, year and leap year information so that dates may be reconciled. The control system is for advancing the system date depending upon the information contained with the calendar profile and the passage of a given amount of time.

Abstract: A data processing apparatus functions as a timer or counter by counting clock pulses of a system clock signal to generate a timing signal. The system clock signal is generated as one of either a first or a second basic clock signal generated by two respective oscillators. Even if the second basic clock signal which has a lower frequency fluctuates, the data processing apparatus can accurately generate a pulse signal having a desired period. When the first basic clock signal is selected as the system clock signal, the second basic clock signal is measured with the system clock signal. When the second basic clock signal is selected as the system clock signal, a numerical value up to which the clock pulses of the system clock signal are counted is corrected on the basis of the measured second basic clock signal.

Abstract: A timer circuit for providing output pulses of an adjustable duration based upon stored decode parameters. The circuit has a timer element which generates a periodic timing signal. Preferably the frequency of the periodic timing signal is also adjustable. A frequency divider is clocked by the timing signal and provides a plurality of frequency divided outputs. A decode circuit combines selected ones of the frequency divided outputs based upon decode parameters and generates a timer circuit output pulse having a duration determined by the frequency divided outputs selected by the decode parameters. The decode parameters are stored in a non-volatile data storage unit so that the timer output pulse will remain the same after power interruption.

Abstract: A pulse width determining device includes a down counter for counting down from a first initial count value reloaded thereinto. If the down counter underflows, it can start counting down from a second initial count value reloaded thereinto as needed. Every time the device receives an input pulse, a count clock control circuit can set a period of time during which it can generate and furnish count clock pulses to the down counter, according to the pulse width of the input pulse. The device can determine whether or not the pulse width of the input pulse is in a predetermined range of pulse widths according to a relation between timing with which the down counter underflows and the time period during which the count clock pulses are generated.

Abstract: An apparatus for monitoring a reference clock signal having a clock pulse train comprises a detecting block for counting pluses of a count clock signal to produce a count value and generate a count failure signal when the count value reaches a predetermined value, wherein the frequency of the count clock signal is larger than that of the reference clock signal; and a controlling block for generating a clear signal at every clock pulse of the reference clock signal to cleat the detecting block when the clear signal is inputted thereto.

Abstract: A circuit such as a host adapter includes a timer capable of detecting time-outs for multiple pending commands. The timer includes a single free-running counter, a first storage for start counts, a second storage for time-out values, a subtractor, and a comparator. The start counts are counts from the counter that are saved when issuing an associated command. The time-out values indicate the lengths of different types of time-out periods. To check whether a command timed out, a start count associated with the command is selected from the first storage, and the subtractor determines a difference between a current count in the counter and the selected start count. The difference is then compared to a time-out value that is selected from the second storage according to the type of time-out. The command timed out if the difference is greater than the selected time-out value.

Abstract: There is provided a small-size time counting circuit which measures time with high accuracy and low power consumption. Around a differential inverter ring composed of an odd number of differential inverters of identical structure connected in a ring configuration, signal transition is caused to circulate by oscillation. A first signal group is composed of normal output signals from the odd-numbered differential inverters and inverted output signals from the even-numbered differential inverters, which rise and fall sequentially at equal time intervals corresponding to delay times in the individual differential inverters. A second signal group is composed of inverted output signals from the odd-numbered differential inverters and normal output signals from the even-numbered differential inverters, which similarly rise and fall sequentially at equal time intervals.

Abstract: Provided is a time counting circuit which can measure the time taken from the rising edge to the falling edge of a pulse signal and the time from the falling edge to the rising edge thereof. The time counting circuit according to the present invention comprises a measuring circuit for measuring the time between either of the rising and falling edges of the pulse signal, and a pulse converting circuit for converting a pulse signal to be measured to a pulse signal having either of the edges in accordance with the rising edge of the pulse signal to be measured and having either of the edges in accordance with the falling edge of the pulse signal to be measured. The time between either of the edges of the pulse signal converted by the pulse converting circuit is measured by the measuring circuit. The time obtained by measurement is the time taken from the rising edge to the falling edge of the pulse signal to be measured or the time taken from the falling edge to the rising edge thereof.

Abstract: An output timer includes a capture register for capturing a count value held by a free running up-counter in coorporation with a transmission gate in response to an event signal applied to the output timer. An adder adds a first value stored in another register to the count value captured by the capture register and produces a sum. A comparator compares a count value held by the free running up-counter with the sum and outputs a coincidence signal when the count value and sum are equal to each other. A set-reset flip-flop includes a set terminal for receiving the event signal and a reset terminal connected to the output terminal of the comparator.

Abstract: A timer circuit for providing output pulses of an adjustable duration based upon stored decode parameters. The circuit has a timer element which generates a periodic timing signal. Preferably the frequency of the periodic timing signal is also adjustable. A frequency divider is clocked by the timing signal and provides a plurality of frequency divided outputs. A decode circuit combines selected ones of the frequency divided outputs based upon decode parameters and generates a timer circuit output pulse having a duration determined by the frequency divided outputs selected by the decode parameters. The decode parameters are stored in a non-volatile data storage unit so that the timer output pulse will remain the same after power interruption.

Abstract: A safety-related control system (SRCS) designed to safeguard personnel operating hazardous production equipment. The SRCS integrates the safety-related part of a machine into one homogenous system for the purpose of increasing safety. In so doing, the SRCS monitors the machine, the operator, and itself for safe operation. The SRCS utilizes a non-material barrier to sense the intrusion of a person's body into a hazardous area of a machine. The SRCS uses machine feedback and/or operator interface to determine whether a hazardous condition is present. If such condition is present, the hazard is rendered harmless by the time the intruding body member can reach the potential danger area. The system includes separable means for stopping motion of the moving parts of the equipment, starting movement of the movable parts, and detecting faults in sections of the system.

Abstract: A method for producing a result prepared from asynchronous external events, wherein two mutually independent counting processes are activated, the temporal coincidence of the ends of counting of these two processes are verified and, on the basis of the information elements pertaining to the verification of each of these two counting processes and according to a specific sequencing of the application considered, a non-consolidated intermediate action is activated for each of the two sequencing processes and, after the verification of the temporal coincidence of the intermediate actions, and taking account of possible external priority actions, a resultant action is produced if all the necessary conditions are fulfilled.

Abstract: A timer circuit for providing output pulses of an adjustable duration based upon stored decode parameters. The circuit has a timer element which generates a periodic timing signal. Preferably the frequency of the periodic timing signal is also adjustable. A frequency divider is clocked by the timing signal and provides a plurality of frequency divided outputs. A decode circuit combines selected ones of the frequency divided outputs based upon decode parameters and generates a timer circuit output pulse having a duration determined by the frequency divided outputs selected by the decode parameters. The decode parameters are stored in a non-volatile data storage unit so that the timer output pulse will remain the same after power interruption.