Abstract: A Vernier delay line interpolator provides a precision level smaller than a clock period by delaying a periodic pulse signal in a delay line which has equally time-spaced taps and a total delay that is a harmonic H greater than 1 of the pulse period. The taps of the delay line are latched and decoded to derive the fraction of the pulse period that has passed. When the interpolator is combined with a coarse counter, misalignment between their outputs is prevented by having the coarse counter count both edges of the periodic pulse signal so as to provide redundant bits between the counter and the interpolator. If the redundant bits are not equal, the counter output is corrected before it is combined with the output of the interpolator.

Abstract: There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption. An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition.

Abstract: The invention provides a high speed variable rate output pulse generating circuit for a semiconductor testing device. The circuit includes a shift register formed of 2n number of flip-flops which counts the lower bits of lower counter data selected by a selector, a ripple down counter formed of m number of flip-flops counts the upper bits of upper counter data selected by a NOR gate. A counting end judgment circuit for judging an end of counting the ripple down counter and the shift register produces a counting end signal. A first flip-flop latches the counting end signal to supply a counter load signal to the selector and the NOR gate to load subsequent data, and a second flip-flop generates a first output clock pulse.

Abstract: There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption.An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition.

Abstract: A deviation of a clock rate of the timepiece clock signal is determined relative to a reference clock rate of a reference clock signal (CR) which is either issued while the mobile unit is switched on or is contained in a received signal. The reference clock rate is higher than the clock rate of the timepiece clock signal. A count number (N) is calculated based on the deviation of the clock rate of the timepiece clock signal. The clock signal is generated such that the clock pulses the clock signal are successively issued each time the clock pulses of the timepiece clock signal counted up to the count number.

Abstract: A power meter (10) is provided which can plug into an electric wall socket and it is provided with its own socket (16) for receiving the plug of an electrical appliance. The power meter has means for measuring electric current flow to an electrical appliance and indicates the amount of electrical power consumed by an appliance. In alternative embodiments, the meter is provided as an integral part of an electric wall switch (30) or wall socket (40) or it is built into an electrical appliance (50). In another embodiment, the power meter has a plurality of sockets for receiving the plugs of a number of electrical appliances for separately indicating the power consumption of each appliance.

Abstract: A clock generates clock pulses defining a plurality of clock cycles. A circuit is connected to receive the clock pulses and measure a primary time of occurrence of an event with respect to a clock cycle. Logic circuits are provided to generate a timing pulse representing a time interval between the event and a clock pulse of the subsequent clock cycle. The timing pulse begins at the time of the event and ends on the occurrence of a subsequent clock pulse. A filter circuit receives the timing pulse and generates in response thereto a signal having an amplitude representing the duration of the timing pulse. The amplitude is measured to determine the width of the timing pulse thereby identifying the occurrence of the event with respect to a subsequently occurring clock pulse.

Abstract: An arrival order judgment device is easy in operation to judge the arrival order for positively recording slit images before and after the finish line for the arrival order judgment only in a necessary minimum range. Slit signals picked up by a line image sensor camera are inputted into a video signal delay circuit. The video signal delay circuit outputs the slit video signals at a predetermined delay time period A. When competitors approaches the finish line and the moment the competitors interrupt a photoelectric device, ON signals are inputted into a memory device to start the record of the images delayed for a predetermined time period. When the competitors are not on the finish line, the photoelectric device outputs OFF signals to a record instruction delay circuit. The record on the memory device is interrupted after the delay period set at the record instruction delay circuit has lapsed. Thus, it is possible to record the images after the competitors have passed through the finish line.

Abstract: A time interval measurement system, by which measurement of individual time interval with remarkably improved measurement accuracy is made possible with smaller circuit scale, comprises a high speed counter section, an adder section, and a control section. The high speed counter section includes a m-bit counter unit having a plurality of m-bit counters for obtaining an integer part of the time interval between a START signal and a STOP signal, a first 1-bit counter unit having a plurality of first 1-bit counters for obtaining an decimal part of the time interval, and a high frequency pulse generator circuit.

Abstract: A system for determining the time between the receipt of two different sils, includes a voltage ramp generator which generates a time dependent voltage signal upon receipt of a timing pulse at a time T.sub.1, and provides the instantaneous value of the voltage signal when the voltage ramp generator receives an input signal having a predetermined threshold value at time T.sub.2. A data processor coupled to receive the voltage signal, generates the timing pulse, and determines a time difference .DELTA.T from the voltage signal, where .DELTA.T=T.sub.2 -T.sub.1.

Abstract: A device and method for quantitative determination of an analyte in a biological sample utilizes a non-transparent support medium for retaining a chromatogenic reaction product with the medium being exposed to a source of light for transmitting therethrough a scattered, uniform response light signal which is collected at a photosensitive device whereby the amount of the analyte is correlated to the intensity of the response light signal. The response light signal may be converted to a time-duration signal proportional to light intensity to facilitate the quantitative determination.

Abstract: A fractional time frequency measuring apparatus includes a divider for dividing a frequency of a signal to be measured with a predetermined division factor; a counter unit for counting the divided signal with a standard clock for every period of the divided signal and outputting count results; a fractional time measuring unit for measuring fractional times produced by the counting with the standard clock; a sequence control unit to form a sequence circuit for sequentially counting the divided signal with the standard clock; a memory unit for holding the count results from the counter unit; a microprocessor for determining a value of the divisional factor, generating a reset signal, and calculating the frequency of the signal to be measured from the count results stored in the memory unit.

Abstract: A method and apparatus for detection of missing pulses from a repetitive pulse train including signal detection circuits for capturing the rising and/or falling edges of an input signal, time-stamping the captured edges, calculating the maximum and minimum instantaneous frequency over a specified time period, and displaying such frequency values. Instantaneous frequency values between any two adjacent edges are calculated based upon the time-stamps of the edges. The instantaneous frequency values in a specified time period are then sorted to find the minimum and maximum frequency values for that time period. These instantaneous frequency values are displayed in the form of a histogram evidencing the occurrence or lack of occurrence of missing pulses from the input signal.

Abstract: An electronic circuit having control data registers (24-28) for receiving the output of a digital counter (20) that records clock pulses within a measured time that is determined by a rotary speed sensor (14) which produces a square wave pulse train signal and separate registers (30,32) for recording the time of each signal developed by the speed sensor and the time to produce a pulse train signal of predetermined length whereby the data in the data registers may be used to determine velocity and derivatives of that velocity for use in solving dynamic equations stored in memory thus effecting control system output functions.

Abstract: A clocking system for measuring running speeds such as split time or lap time for a plural number of track runners like racehorses at each one of a plural number of clocking positions provided at predetermined intervals along a running course or track toward a goal position. The clocking system fundamentally includes: a trigger signal transmission means provided at each one of the clocking positions and adapted to release a trigger signal toward a narrow signal receiving zone; a passing signal generating means carried by each runner and adapted to produce a passing signal specific to a particular runner at each clocking position upon reception of the trigger signal; and a measuring means provided either at each clocking position or on each runner and adapted to register a time reading for each runner upon reception of the trigger signal or passing signal.

Abstract: In a timer device, the counter thereof counts the number of the pulses of a pulse signal input from an external apparatus up to a count initial value to output a count ending signal at the time of the end of the counting, and the control signal generator thereof generates a signal for controlling the external apparatus on the count ending signal output from the counter, and further the count operation controller thereof controls the count operation of the counter on a state change signal indicating the change of the state of the external apparatus. Thereby, the timer device can execute extensive processing by means of few counters.

Abstract: A very high speed counter system of operating at frequencies of up to around 800 MHz provides timing measurements with accuracies on the order of (1/f) seconds where f is the frequency of operation. The least significant bit of the counter operates at the given frequency of a first clock signal while the other higher order bits operate at a second clock signal where the second clock signal is one-half the frequency of the first clock signal and is inverted. Carry lookahead circuits connected between stages of the second counter operate in conjunction with the clocking scheme to produce a high speed and accurate counter.

Abstract: A Vernier delay line interpolator provides a precision level smaller than a clock period by delaying a periodic pulse signal in a delay line which has equally time-spaced taps and a total delay that is a harmonic H greater than 1 of the pulse period. The taps of the delay line are latched and decoded to derive the fraction of the pulse period that has passed. When the interpolator is combined with a coarse counter, misalignment between their outputs is prevented by having the coarse counter count both edges of the periodic pulse signal so as to provide redundant bits between the counter and the interpolator. If the redundant bits are not equal, the counter output is corrected before it is combined with the output of the interpolator.

Abstract: An integrated circuit counter is capable of implementing a relatively high count while being testable using a relatively low number of clock cycles. A linear-feedback shift register (LFSR) having n bit positions is used as the counter. The feedback path of the shift register includes an exclusive OR (XOR) gate that couples selected bits back to the input of the register, in order to implement a 2.sup.n -1 counter. Combinatorial logic circuitry is included to test the counter in significantly less than 2.sup.n -1 clock cycles. This allows for implementing a testable "watchdog timer" that may be used to detect software runaway conditions in microprocessor systems, among other uses.

Abstract: In order to measure an individual time interval with accuracy beyond frequency limit of semiconductors, a time measurement system of the invention generates a series of delayed pulses, each of which has the same pulse width with the time interval to be measured and delayed by a unit delay time shorter than a cycle time of a system clock from its preceding delayed pulse. A series of discriminate number measurement pulses are also generated from the series of delayed pulses, each of which rises at a common time and falls at each corresponding delay pulse. From number of a longest sequence of the same pulse number of the system clock counted in the discriminate number measurement pulses, the unit delay time is measured. From average value of pulse numbers of the system clock counted in each of the delayed pulses, the time interval to be measured is calculated with accuracy of the unit delay time.

Abstract: The present invention relates to an electronic meter circuit for a time comparison measurement between two successive periodic events with which the signal time ratios between two times two successive events can be recognized by a simple method.The electronic meter circuits comprises a reference meter to be loaded with a reset value when a first event occurs and for reference meter to start to count at a clock frequency and when a second event occurs, reference meter starts to count in the opposite direction at a clock frequency until a third event occurs, and when the third event occurs, meter reading forms a reference value for the ratio of the signal times between the occurrence of the first and second events and between the second and third events.

Abstract: The invention discloses a method and an apparatus for implementing an L phase clock in conjuction with L counters, where L is an integer, to count at a frequency scalable by L.

Abstract: A test circuit determines state of an electrical element supplied with alternating current and measures the duration of that state. The test circuit is connected to the element so that current flows to the test circuit when the element is in the state being measured. The test circuit rectifies the alternating current to periodic pulses, which are counted to determine the duration of the current and, thus, the state. The circuit is particularly useful for testing operation of a dishwasher pump motor that is interrupted periodically. The test circuit is connected to auxiliary contacts that open and close in correspondence with the operation of the pump motor.

Abstract: A power meter (10) is provided which can plug into an electric wall socket and it is provided with its own socket (16) for receiving the plug of an electrical appliance. The power meter has means for measuring electric current flow to an electrical appliance and indicates the amount of electrical power consumed by an appliance. In alternative embodiments, the meter is provided as an integral part of an electric wall switch (30) or wall socket (40) or it is built into an electrical appliance (50). In another embodiment, the power meter has a plurality of sockets for receiving the plugs of a number of electrical appliances for separately indicating the power consumption of each appliance.

Abstract: A system and method for detecting fault conditions within a vehicle recording device are disclosed herein. The fault detection technique may be implemented in a vehicle in which are incorporated one or more vehicle sensors for monitoring one or more operational parameters of the vehicle. A recording device disposed within the vehicle is used to collect vehicle operation data produced by the one or more vehicle sensors.The fault detection technique of the invention contemplates storing a current time value at regular intervals during periods in which the recording device is provided with a source of main power. Time differences are determined between consecutive ones of the stored time values, and the time differences compared to a predetermined maximum value. A power loss fault condition is registered when at least one of the time differences exceeds the predetermined maximum value.

Abstract: A timer circuit for providing output pulses of an adjustable duration based upon stored decode parameters. The circuit has a timer element which generates a periodic timing signal. Preferably the frequency of the periodic timing signal is also adjustable. A frequency divider is clocked by the timing signal and provides a plurality of frequency divided outputs. A decode circuit combines selected ones of the frequency divided outputs based upon decode parameters and generates a timer circuit output pulse having a duration determined by the frequency divided outputs selected by the decode parameters. The decode parameters are stored in a non-volatile data storage unit so that the timer output pulse will remain the same after power interruption.

Abstract: A free running relaxation oscillator is disposed on a semiconductor integrated circuit die for generating a frequency representative of the natural frequency of the die. The natural frequency of the die changes for different operating temperatures and voltages. An optimal speed may be determined at which the die will reliably operate by measuring the natural frequency. The die may be effectively graded and matched with a similar die by correlating the natural frequency of the die with the temperature and voltage values at which the natural frequency was measured for each die. A plurality of integrated circuit dice may be connected into a digital system, and the natural frequencies of each die may be monitored so as to optimize the system operating speed, reduce system power consumption without degrading performance, and/or increase the operating speed of a slower die by changing the temperature and/or operating voltage thereof.

Abstract: A control device for power saving for personal computers, printers, etc. which generates a suspension signal or a power-off signal to perform power saving by detecting input horizontal and vertical sync signals. The suspension signal provides a suspension mode for a minimum basic operation of the computer or printer, while the power-off signal provides a system power-off mode. The control device is designed as a digital circuit comprising latches, counters, monostable multivibrators, and other logical elements. Integration of the circuit is possible as well as its transient response characteristic is improved.

Abstract: A timer apparatus which is provided with a control circuit 80, annexed to each of timers 1-1, 1-2 and 1-3 generating a control signal making the register 3 write data outputted from a CPU 50 when both a write signal 5 generated by the CPU 50 for writing data into the registers 3, and a timer single write signal 11 for specifying any of the timers, are generated, and furthermore is provided with a selection circuit 70 making each control circuit 80 generate a control signal when both the write signal 5 and a timer grouping signal 14 generated for specifying each of the plurality of timers 1-1, 1-2 and 1-3, are generated. When it is necessary that identical data be held in the respective registers 3 of the plurality of timers 1-1, 1-2 and 1-3, the identical data can be written into each of the registers 3 at the same time.

Abstract: For correction of an error caused in a period of a clock signal for digitizing a plurality of time signals, e.g., from an image sensor, a clock signal generating device generates a reference signal Sr indicative of a reference time of time signals TS from an OR-date (20). The device counts a reference clock signal .phi. in a frequency divider (30) until the reference signal Sr is generated, and outputs a divided clock signal .phi..sub.n with frequency dividing ratio 1/N from the frequency divider (30). It then counts the signal .phi..sub.n and stores the count value as a reference value S in a reference value counter (40). The device outputs an output clock signal .phi..sub.o from an output counter (50) each time the signal .phi. received after generation of the signal Sr reaches a predetermined value. It accumulates in an accumulator (60) the count value of the frequency divider (30) at the time of generation of the signal Sr in response to the signal .phi..sub.

Abstract: It is an object to accurately obtain the period of the horizontal synchronizing signal in the video signal. The number of internal pulses are measured in a predetermined measurement period defined by the horizontal synchronizing signal. It is assumed that the periods of the horizontal synchronizing signal and the internal pulse are denoted as T.sub.H and T.sub.S, and the measurement period is defined by one period of a divided signal NS which is obtained by N-dividing the horizontal synchronizing signal. In this case, the length of the measurement period is N.multidot.T.sub.H. The period of the horizontal synchronizing signal is obtained when the internal pulse is activated K times in the measurement period. After the measurement period is started, the divided signal NS transits between the Kth activation of the internal pulse and the (K+1)th activation, and the measurement period is ended. Accordingly, there is the relation of T.sub.S .multidot.K<N.multidot.T.sub.H <T.sub.S .multidot.(K+1). The error .

Abstract: An integrated circuit which includes not only a real time clock, but also an elapsed time counter, and a third counter. The elapsed time counter measures the total number of seconds during which a system has been powered up. The third counter is a "cycle counter," which measures the number of times a power cycle (power-up and power-down) has occurred. Thus, by reading the cycle counter and the elapsed time indicator, the general power history of a system can readily be determined, even if the system itself has totally failed. This integrated circuit is battery backed, and is advantageously combined with a system for which power history must be maintained.

Abstract: A timer has a function of compensation calculation and includes a compensation value register 1 for holding a compensation value and an arithmetic unit 2 which adds or subtracts a compensation value ".alpha." held in the compensation value register 1 and a value "CC" of a count value C of a counter 3 at that time point, and by loading the operation result of the arithmetic unit 2 to the counter 3. Such a timer reduces a burden on a CPU and is capable of compensating the count value correctly regardless of a remaining time.

Abstract: A memory device for recording a time factor of data includes a threshold element, coupling capacitance, an RC-circuit, and a digital counter. A reference voltage is input to the RC-circuit. The output of the RC-circuit and an input voltage are each input to the coupling capacitance. The output of the coupling capacitance is input to the threshold element. When the voltage received by the threshold element reaches a threshold voltage level, the threshold element generates an output voltage. The digital counter receives the threshold element output voltage and the reference voltage. The digital counter is triggered by the reference voltage to begin counting clock pulses generated by a reference clock. The digital counter is then triggered by the threshold element output voltage to stop counting the clock pulses.

Abstract: A printer controller employs a microprocessor together with an application-specific-integrated-circuit (ASIC) to manage the operation of the printer. Among its functions, the ASIC manages memory access for the microprocessor. Either fast- or slow-clock microprocessors may be installed in the controller, but the ASIC requires a slow clock. When a fast-clock microprocessor is installed, the ASIC must divide the clock frequency to provide its own (slow) clock. Likewise, the use of a fast-clock microprocessor requires the ASIC to insert memory-cycle WAIT times, whereas a slow-clock microprocessor needs no WAITs. In a preferred embodiment of the invention, provision is made, during initial power-on RESET, to inform the ASIC which clock speed is being used. This information is conveyed by the configuration of the WAIT interconnection between ASIC and microprocessor, thus eliminating the need for a dedicated ASIC pin for this purpose.

Abstract: A perishable good integrity indicator includes a first oscillator for outputting a first clock signal which does not substantially vary in response to temperature. A second oscillator outputs a second clock temperature which varies as a function of temperature. A counter counts the pulses of the second clock signal during a time period determined by the first clock and outputs a count value. A data table receives the count value, translates the count value into a time temperature value representing the relationship of time and temperature during the time period and outputs the time temperature value to an adder. The adder adds the time temperature values output by the data table over time and outputs a cumulative time temperature value corresponding to shelf life for a product.

Abstract: An actuator movement detector (10) indicates proper engagement of a solenoid (12). The current flowing through a field coil (16) is converted to a sense voltage that exponentially increases and then follows a dip before increases again to a steady state value greater than the first peak value. The exponentially increasing sense voltage is stored across a capacitor (24). Any AC variation about the stored sense voltage sets the output state of comparators (30, 32) and determines a first peak value of the sense voltage. After the first peak, a counter (44) must count to a predetermined value during the low peak before the sense voltage returns to its first peak value. If the counter reaches at least the predetermined count value before returning to its first peak value and count back down to zero before reaching steady state, then the solenoid is considered engaged.

Abstract: Method and device for counting clock pulses for the purpose of determining period length works in accordance with an absolute time measuring principle, provides at least a single main counter which runs uninterruptedly from the start of measurement to the end of measurement and a channel counter for each of a number n of measuring channels. By stopping a channel counter at the associated measurement period end and reading out the counter reading thereof as well as that of a supplementary upper main counter part which contains the higher-order count positions, a determination is made of the total time elapsed from the start of measurement up to the respective detected period end, and thereafter the target period lengths are determined by forming the difference of successive count values. The invention can be used, for example, for the high-precision measurement of the speed of a system rotating about an axis.

Abstract: A watch-dog timer circuit including a counter which counts clock pulses of a microcomputer and a timer circuit which is refreshed in every period of the clock pulse, thereby to generate a request signal to reset a CPU by means of the counter when the counter overflows or underflows, and generate a request signal to reset the CPU by means of the timer circuit when the clock pulse stops, in order to monitor both uncontrollable operation of the CPU and the stop of oscillation of the clock pulses, and the micro computer equipped with the watch-dog timer circuit.

Abstract: A method and apparatus for a "self-calibration timing circuit" is utilized to dynamically compensate for inherent performance differences between individual semiconductor dice, and for a wide range of different operating temperature and voltage parameters. The present invention accomplishes this by utilizing circuits which are deposed on the semiconductor die. These circuits consist of a relaxation oscillator running at the natural frequency of the silicon die, a gated counter counting the number of cycles of the relaxation oscillator frequency during a reference clock period to produce a ratio thereof, and a decision circuit that utilizes this ratio to optimize a system clock frequency for best system operation.

Abstract: A programmable time-intervals generator comprising first and second digital counters, a memory, a digital divider and a digital adder. On the occurrence of a first event, the first counter starts counting, and on the occurrence of a second event, only the most significant bits of the number counted up to then are stored, thereby providing a division by truncation. From the stored number, at least two discrete fractions are obtained by the divider, whereafter said fractions are summed at the adder which operates on strings of bits. The second counter counts down the sum number and, on becoming cleared, generates a signal.

Abstract: An elapsed time recording device includes a counter (130) for incrementally advancing a count value from an initial value towards and beyond a threshold in response to successive clock pulses of a clock signal. Control logic (140) enables the counter (130) to incrementally advance the count value in response to a first input (pin 3) and a second input (pin 1) being at or near a first voltage level, and holds the count value in response to the first input (pin 3) being at or near a second voltage level and the second input (pin 1) being at or near the first voltage level. Setting logic (210) sets the count value to a value beyond the threshold in response to the first input (pin 3) and the second input (pin 1) being at or near the second voltage level when the count value is between the initial value and the threshold.

Abstract: A parking lot traffic control and fee collection system is disclosed for use in stadium type parking lots. A vehicle counter installed in a portable traffic pylon is provided at the entry point for each entrance lane of the parking lot for marking the station of the parking attendant. The vehicle counter is installed in a tamper-proof arrangement and the cumulative count of vehicles is presented on a display device which is viewable without opening the enclosure provided by the pylon. A parking supervisor may read the cumulative count at any time and pick-up the receipts from the parking attendant during or at the completion of the parking process. The amount of the receipts collected is compared with the reading on the display device and discrepancies are noted by the supervisor. The vehicle counter is provided with a tamper-proof reset switch.

Abstract: A dual time base, zero dead zone time domain reflectometer repetitively launches a predetermined number of stimulus pulses into a transmission system in synchronism with clock signals from a first time base, providing a measurement cycle. The duration of the launched stimulus pulses, determined by a predetermined number clock cycles from the first time base, exceeds the total propagation time of the system to be measured so that a time interval between a launch and a reflection may be measured within the launched pulse. A second time base, which has a predetermined period that differs from the period of the first time base and defines a measurement period divided into equal sub-periods, continuously produces clock signals, one or more of which may be counted during the time interval.

Abstract: A signal generating circuit includes a counter for counting up input clock pulses to output a trigger signal when counting up to a predetermined number of pulses, a CPU for outputting a mask request of a first trigger signal, a first flip-flop for storing the mask request of the CPU, a second flip-flop for latching a normal output signal of the first flip-flop by the trigger signal of the counter, and an AND circuit for calculating a logical sum of a mask request signal output from the second flip-flop and the trigger signal output from the counter. Thus, the trigger signal generating circuit masks the first trigger signal output from the counter and prevents the output of a superfluous trigger signal when a timing of a trigger signal generation is delayed.

Abstract: Utilization circuits, such as logic chip circuits, are prevented from receiving the initial one or more pulses of a train of clock pulses produced after the master system clock is started, while the pulses of that train occurring thereafter are coupled to the utilization circuit. This prevents the skew usually present between the initial pulses of the train relative to the subsequent train pulses from adversely effecting operation of the utilization circuits. This clock swallowing preferably blocks a certain predetermined number of initial clock pulses from reaching the rest of the circuitry, although the system is adaptable to allow preselection of the number of such swallowed pulses.

Abstract: An apparatus is disclosed that provides control of access to a module. In particular, the module should not be accessed while in a busy or unstable state. The module disclosed herein, by way of example, is a timer module. Access to the timer is controlled by the disclosed apparatus while the timer is changing state.

Abstract: A power-on reset system comprises one-shot pulse generator for generating a one-shot pulse signal in response to a change in the power supply potential, a flip-flop to be set to operate by a one shot pulse signal and a timer to be activated by an output signal of said flip-flop operating as an enable signal for timing a given period of time. An output signal of said timer operates to reset the flip-flop so that the output of said flip-flop is utilized as a system reset signal. The timer includes an oscillator and a counter for counting oscillation signals. A voltage step-up means has an input responsive to the oscillation signals. With such an arrangement, the overall surface area of an LSI incorporating the system is minimized and a sufficiently long reset period is ensured for it.

Abstract: A high resolution counter circuit measures the time interval between the occurrence of an initial and a subsequent electrical pulse to two nanoseconds resolution using an eight megahertz clock. The circuit includes a main counter for receiving electrical pulses and generating a binary word--a measure of the number of eight megahertz clock pulses occurring between the signals. A pair of first and second pulse stretchers receive the signal and generate a pair of output signals whose widths are approximately sixty-four times the time between the receipt of the signals by the respective pulse stretchers and the receipt by the respective pulse stretchers of a second subsequent clock pulse. Output signals are thereafter supplied to a pair of start and stop counters operable to generate a pair of binary output words representative of the measure of the width of the pulses to a resolution of two nanoseconds.

Abstract: Apparatus for determining the number of cycles occurring in a frequency modulated signal during a sample period, including not only the number of full cycles but any portion of a cycle, by determining the number of whole cycles and adding to this a value obtained by counting the number of high frequency clock cycles occurring between the time of the last rising edge of a full cycle and the end of the sample period, and the number of high frequency clock cycles occurring from the last rising edge prior to the start of the sample period and the start of the sample period and the number of high frequency clock cycles in a whole cycle.