Abstract: A timing circuit 10 that can be used to control the flow of fluid according to a specific time period that is allotted for each user includes a initialization circuit 30, a reset counter circuit 32, a flow time counter circuit 38, and a clock circuit 40. The timing circuit 10 accepts a DETECT* input signal, that indicates the presence of a user, and provides a DRIVE output signal that indicates when fluid shall be permitted to flow. The flow time counter circuit 38 is user configurable to provide a maximum flow time period while the DETECT* signal is active. The reset counter circuit 32 ensures that each user is provided with his or her maximum flow time period by introducing a system reset time between consecutive users and by allowing a user to remove him or her self from being detected, thus placing the DETECT* signal in an inactive state and subsequently inactivating the DRIVE signal, for certain periods of time without forfeiting any of his or her allotted maximum flow time period.

Abstract: A revolution counting circuit for performing such an operation includes a pulse multiplying unit for multiplying signal pulses generated by an encoder and a pulse dividing unit for dividing the multiplied signal pulses by a divided value set up by a microprocessor. Further, a revolution counting circuit may include a pulse selection unit for selecting one of the signal pulses generated by the pulse multiplying unit and the pulse dividing unit. Also included are a waveform shaping unit for generating a pair of divided signal pulses having the same phase difference as the signal pulses generated by the encoder and a control signal generator for sending control signals to the waveform shaping unit.

Abstract: A pseudo-random repetitive sampling circuit which is capable of sampling fast signals, sampling negative and positive time around a trigger event, and rapidly building the waveform for display. The circuit accomplishes this by acquiring negative and positive time in two different ways. Positive time information is acquired using a modified form of sequential sampling, since sequential sampling can rapidly build the signal for samples that occur after the trigger event. The system also may take multiple samples for each trigger event. For samples occurring prior to the trigger event, the system uses a modified form of random repetitive sampling. The modification comprises sampling of the waveform prior to allowing any trigger events to occur, and qualifying each trigger event so that a trigger event is only recognized when it occurs in a programmable time window after a sample.

Abstract: A power meter (10) is provided which can plug into an electric wall socket and it is provided with its own socket (16) for receiving the plug of an electrical appliance. The power meter has means for measuring electric current flow to an electrical appliance and indicates the amount of electrical power consumed by an appliance. In alternative embodiments, the meter is provided as an integral part of an electric wall switch (30) or wall socket (40) or it is built into an electrical appliance (50). In another embodiment, the power meter has a plurality of sockets for receiving the plugs of a number of electrical appliances for separately indicating the power consumption of each appliance.

Abstract: A pulse accumulator (24) operates in a pulse measurement mode. In the pulse measurement mode, accumulator (24) measured pulse lengths of consecutive high and low input signal pulses in reference to a clock signal. A leading-edge capture circuit (50) asserts a leading-edge pulse to indicate a rising edge of the input signal and a trailing-edge capture circuit (52) asserts a trailing-edge pulse to indicate a falling edge of the input signal. The leading-edge and trailing-edge pulses are logically combined (70) to provide a load signal to enable counter (76) to provide an accumulate value to a buffer register (78). After a predetermined delay (62, 64), each of the leading-edge and trailing-edge pulses are logically combined (66) to provide a clear signal which indicates the input signal has transitioned and counter (76) should be cleared to begin measuring a length of a next pulse.

Abstract: In a capstan servo circuit, a waveform shaping error which might occur while shaping the waveform of an FG signal is suppressed to control the speed of a capstan motor stably. An FG signal from a frequency generator mounted on the shaft of the capstan motor is shaped in waveform by an amplifier and a comparator and is multiplied to double its frequency by a multiplier. The multiplied FG signal is inputted to an FV counter where the time from a rise to a subsequent fall of the waveform-shaped FG signal and the time from a fall to a subsequent rise of the same FG signal are counted. The count values are latched in order by two levels of latch circuits. The N-bit count values latched are inputted to an adder where a mean of the two count values is calculated by outputting the upper N bits and is supplied to the capstan motor as a servo signal.

Abstract: A digital capacitive sensing device comprises: a reference capacitor having a reference capacitance unaffected by a force to be measured; a reference pulse signal generating circuit which generates a reference pulse signal of a frequency corresponding to the reference capacitance; a sensing capacitor having capacitance variable according to the magnitude of the force; a measuring pulse signal generating circuit having a construction similar to that of the reference pulse signal generating circuit and capable of generating a measuring pulse signal of a frequency corresponding to the capacitance of the sensing capacitor; and a differential arithmetic circuit which adds the number of pulses of the reference pulse signal in a predetermined time interval to a set value and subtracts the number of pulses of the measuring pulse signal in a predetermined time interval from the set value.

Abstract: An apparatus is described for increasing a fare to a rounded-off amount, in which the fare is determined by an electronic taximeter and prior to the preparation of a voucher in an assigned voucher printout mechanism the amount payable is rounded-off by an increase of the fare amount manually preselectable in predetermined steps, based on an actuation of operating keys. A stepwise or discretely adjustable rounding-off is selectable for printout in the voucher printer in such a way that the voucher shows the sum, formed from the fare+surcharge+additional amount selected by the passenger.

Abstract: A sensor generates a pulse signal at a predetermined angle of a rotating body. First and second registers respectively memorize both of a leading edge and a trailing edge of a divided signal of the pulse signal. The first resistor maintains the timing of the detected preceding leading edge until the next leading edge is detected so that the timing of the next leading edge is renewed when the next leading edge is detected. The second register maintains and renews the timing of the trailing edge in the same manner as the first register. The rotational speed is obtained by computing the time difference of each memorized timing at the start of such computing operation. Accordingly, an accurate rotational speed can be always obtained, even when the rotational speed computing operation is delayed by a high priority interrupt operation.

Abstract: A sorting machine is disclosed based on a procedure utilizing standard length pulses initiated by the sensing of the leading edge of a sensed product and rejecting a defective product based on sensing where its trailing edge is or should be if covered up by a successive overlapping product. Such detection allows for rejecting products that are either too long or too short. The detection of the trailing edge location also is employed for the activation of a reject mechanism operated on a fixed delay from the occurrence of a defect signal for whatever reason produced from the sensing of a product in the product stream.

Abstract: A digitalization assembly of the over-sampling type includes an analog to digital converter (2) producing at a frequency F=kf small-format p samples and a digital filter (3) which, through the summation of a certain number n of over-samples, produces validated larger P-format samples at the frequency f, at instants fixed by a clock. In order to readjust the sampling instants in relation to an outside event which can occur at any time, a temporary memory store (5) is inserted between the converter (2) and the filter (3) and, according to the instant of arrival of this event, the appropriate samples to be sent towards the filter for their summation are selected.

Abstract: A pulse generating apparatus equipped with a first comparator (20) for comparing the count value of a timer register (9) with the reference value of a comparing register (10) in terms of each bit and a coincidence detection circuit (21) responsive to the output values of the first comparator (20) to output a coincidence signal when all the bits of the output values thereof are the same. Between the first comparator (20) and the coincidence detection circuit (21) there are provided a plural-bit mask register (17) whose comparison value is set by a CPU (2) and a second comparator (22) for comparing the comparison value of the mask register (17) with the output value of the first comparator (20) in terms of each bit. With this arrangement, the generation timing of the output pulse can variously be changed by setting one time the mask register (17).

Abstract: A circuit that may be implemented in a computer system that will measure the maximum and minimum time intervals for system elements to respond to a request for data or information. The circuit includes control logic that controls operation of the circuit, an up-counter and a down-counter that are used together for measuring the maximum or minimum response time interval, and a display for displaying the maximum or minimum response time interval that is measured during a test period.

Abstract: The present invention is a time vernier providing fine timing control of an input signal having coarse timing edges. The time vernier comprises a receiving means for receiving a value representing a desired time delay to be added to the coarse timing edge input. The desired time delay may have both fine and coarse delay aspects. The time vernier also comprises a first decoding means for decoding the fine delay aspect and generating fine delay control signals, as well as a second decoding means for decoding a coarse delay aspect and generating coarse delay control signals. A delay line is also included in the time vernier which has inputs to receive the input signal having coarse timing edges, the fine and coarse delay control signals, and a control voltage which automatically adjusts with temperature and power supply variations, so as to provide for temperature and power supply compensation. The delay line combines the fine and coarse delay signals to provide an output signal with fine timing edges.

Abstract: The remote control units of a electronic centralized locker system are programmed with incremental rate parameters, such that the rental fee for each locker increases as the time period during which the locker is used increases. In order to implement the incremental rate structure, the total rental time is broken into a number of subperiods and a separate incremental fee is charged for each subperiod. In accordance with the invention, it is also possible to set the number of subperiods over which a fee will be charged, before a maximum fee is reached. Once the maximum fee is reached, the locker rental charge does not increase.

Abstract: A circuit for determining the duty cycle of a control signal includes an oscillator that operates at a frequency that is a predetermined multiple of ten higher than the frequency of the control signal. The oscillator output is connected to the count input of a digital counter, and the control signal is connected to a count inhibit input of the counter. Thus, the counter only counts the oscillator output pulses during the active interval of each cycle of the control signal. Timer means are provided to generate a store trigger signal at the end of a predetermined number of control signal cycles. The store command causes the counter to store and visually display the total count of oscillator pulses detected during the active interval of each cycle. Thus, the count total corresponds to the duty cycle of the control signal. A reset timer is provided to initialize the counter after a predetermined delay from the time that the count total was stored.

Abstract: A timing interpolator providing high resolution timing measurement of when an event occurs. The interpolator of the present invention includes three embodiments. The interpolator of the first embodiment includes a Voltage Controlled Oscillator (VCO) phase-locked loop, an N-bit counter, and an N-bit latch. The interpolator of the second embodiment includes a delay line phase-lock loop and an X-bit latch. The delay line phase-lock loop includes an X-bit delay cell chain and a phase detector. The interpolator of the third embodiment of the present invention represents a combination of the interpolators of the first and second embodiments. The interpolator of the third embodiment includes a VCO phase-locked loop, a delay line phase-lock loop and X-bit latches.

Abstract: A start-stop synchronous communication speed detecting apparatus includes a counter, a speed determining unit, a clock switching unit, a shift register, a character determining unit, a code generator, and a controller. The counter counts a time period, in which received data is a space polarity, in start-stop synchronous communication. The speed determining unit compares the count value with a time per bit of a specified communication speed. The clock switching unit selects a clock synchronized with the start bit of the received data and having the same frequency as that of the specified communication speed. The shift register stores the received data. The character determining unit compares a received character from the register with a predetermined character. The code generator supplies codes of the first to Nth characters to the character determining unit.

Abstract: A reload timer circuit comprises an n-bit up/down counter circuit for receiving input data of n bits and providing up/down count data of n bits; an n-bit timer circuit for receiving the n-bit up/down count data and providing timer data of n bits; and a timer period setting means for generating a timer period signal in response to an overflow signal of the n-bit timer data and providing the n-bit up/down counter circuit with the timer period signal. This reload timer circuit automatically sets a reload value by hardware without relying on software, thereby reducing the load on a central processing unit.

Abstract: An input to the control unit of a microprocessor places the microprocessor in a WAIT condition whenever the input clock frequency is determined to be less than a predetermined minimum value. A timing circuit which includes a relatively high capacitance device generates a "kill" signal whenever the time interval between successive clock pulses is greater than a value corresponding to a cut-off frequency. The kill signal is applied to the control unit of the microprocessor and cannot be reset except with a system reset.

Abstract: A circuit for time stamping event signals, e.g. zero-crossings, using coarse and fine timers. The fine timer is a circuit section which subdivides a period from a phase-locked ring-oscillator into 2N subparts. An event signal is timed by latching a digital representation of a particular subpart. The digital representation of the subpart is an N-bit dual thermometer code which uniquely identifies each subpart with each adjacent subpart differing by only one bit. The subparts are made finer in time quantization than the propagation delay of one active element in the ring oscillator by the use of linear combiner elements. The dual thermometer code, encoded post-latching into a binary code, forms the "fine" timing part of a binary word representation of the event time. The event also latches the count states of a pair of lead-lag counters in a master-slave configuration counting ring oscillator periods. These counters change states respectively before and after the dual thermometer code turn-overs.

Abstract: A device for measuring ultrasound transit times in workpieces disposed over an HF pulse generator which generates high-frequency wave trains with few oscillations periods and which is connected with an ultrasound transmitter/ultrasound receiver, whose output signal acts upon a comparator. The comparator generates pulses on zero crossings of the ultrasound echo. Between a gate circuit and a counter there is provided an AND-gate, whose second input is acted upon with the output signal of the comparator. The time gate of the gate circuit can be positioned, computer controlled, a quarter-wavelength of the ultrasound before the maximum of the envelope curve signal of the amplified ultrasound echo, so that it always equal-lying steepest zero crossing triggers the start or stop impulse of the counter.

Abstract: A digital frequency detection circuit, or frequency discriminator, is implemented for use as a synchronization field detector for the synchronization field frequency in the data stream read from a computer floppy disk. No analog components are utilized; and the detector produces an output indicative of the presence of a valid synchronization field frequency whenever the incoming data pulses fall within a predetermined range of frequencies having a lowest frequency limit and an upper frequency limit. This is accomplished by employing a multi-stage binary counter for counting the reference clock pulses from a computer. The counter is reset each time an incoming data pulse is received; and the outputs of the counter are coupled to coincidence gates, which establish the lowest and highest frequency limits of the predetermined range of frequencies to be detected.

Abstract: An anti-fraud device for digital measuring instrument includes a sensing encoder integrated circuit combinably packed with a sensor, and a measuring decoder integrated circuit combinably packed with a measuring meter for receiving signal as sensed from the sensor through a transmission line. When an external-signal generator is fraudulently installed on the transmission line for increasing output signals into the meter for cheating a meter fare, an external signal from the external-signal generator will be first checked by the measuring decoder integrated circuit provided before the measuring meter to be different from a prestored data in the measuring. Then the measuring decoder will not output a valid pulse to be counted in the measuring meter, without increasing an unwanted meter fare or fees for preventing a fraud matter.

Abstract: A data transmission system with double lines comprises a plurality of sensor terminals connected to the current line in cascade, and a controller connected to a current input side of the first sensor terminal. A switch device in each sensor terminal connects the current line to a sensor circuit for a specified time after a current begins to flow to the current input side of the sensor terminal, and connects the current line to the current output side of the sensor terminal after an elapse of the specified time. After that switching, the current begins to flow to the next sensor terminal. If the sensor turns on while the current is flowing to the sensor circuit, the value of the current of the current line may be greater. The controller detects value of the current and decides state of the sensor circuit in the sensor terminal according to the value of the current.

Abstract: A PWM signal demodulation method measuring the leading edge period of a modulated signal and a time between adjoining leading and trailing edges of the signal and finding the modulation factor in terms of the ratio of the period to the time. Reliable demodulation is ensured even if the carrier frequency of the modulated signal varies significantly. This novel method eliminates one disadvantage of the prior art demodulation method encountered when a varying carrier frequency exceeds the linearity domain of an integrator in its integrating characteristic, causing unreliable demodulation.

Abstract: A pulse control circuit generates latch signals in response to edges of externally-input pulses and generates a resetting signal after each of the latch signals is generated. A pulse position measurement counter counts reference clock signals, thereby measuring the time interval between the generation of one latch signal and the generation of the succeeding latch signal. In response to the latch signal, a latch circuit latches the time interval measured by the pulse position measurement counter as output data. A pulse detector detects that the time interval between successive latch signals is shorter than a predetermined time. It also detects that the number of latch signals which have been input is larger than a predetermined number. A data control circuit is employed in association with the pulse detector.

Abstract: A swim/sporting event timer/counter times a athlete moveing along a predetermined path based on signals received from the athlete. A time counter begins when movement of the athlete is detected. Based upon the amount of time it takes for the athlete to pass by the timing system, the time counter is automatically adjusted, if necessary, to account for the time counter having been started at an incorrect time.

Abstract: A method and apparatus makes rapid frequency measurements by measuring time intervals for a series of blocks of event counts with the number of events in each block held constant. This makes the numerator of the events/time relationship constant so it does not have to be measured, processed or stored. The frequency of the signal is determined by measuring the time interval, then taking the inverse of the measured value and multiplying by the appropriate constant. A fast inverse circuit uses a Taylor series expansion technique implemented in digital circuit, with the slope resolution adjusted for regions of small slope to improve accuracy.

Abstract: A circuit system for preventing a measuring device such as an engine speed measuring device or the like from being erroneously operated includes as essential components a filter circuit, a Schmitt trigger circuit, an oscillating circuit, a counting circuit, a pulse monitoring circuit and an adding circuit. A combination of the filter circuit and the Schmitt trigger circuit serve to properly shape a wave form of each of a series of pulse-shaped sensor detection signals. The oscillating circuit generates a series of pulses each having a reference frequency. The pulse monitoring circuit monitors a wave-form shaping output pulse by counting the number of a series of output pulses each having a reference frequency for a predetermined period of time with the edge of the wave-form shaping output pulse as a trigger.

Abstract: A processing circuit is provided for signals (S.sub.1, S.sub.2) supplied by two transducers measuring a physical quantity parameter in a differential mode and delivering a signal representative of this parameter. This processing circuit essentially comprises a first counter for counting within a measurement period an integer N.sub.1 of periods T.sub.1 of the signal S.sub.1, a second counter for counting within this period of measurement an integer N.sub.2 of periods T.sub.2 of the signal S.sub.2, and a logic circuit to deliver a signal S.sub.m representative of the difference between the interval N.sub.1 .multidot.T.sub.1 and the interval N.sub.2 .multidot.T.sub.2, this signal being representative of the value of the physical parameter. The circuit is useful for measuring acceleration, force, pressure or temperature.

Abstract: A timing signal delay circuit comprises a counter placed with first delay setting data (21-24) for counting a first clock signal (12) in response to an input timing pulse (11), and a first flip-flop circuit which has a D-input supplied with the output of the counter (1) and a clock input supplied with a second clock signal of the same timing frequency as the first clock signal. For doubling resolution of the delay which the input timing pulse undergoes, there are provided an exclusive-OR gate (4) supplied with a second dealy data signal (31) and a third clock signal (14) of the same timing as the second clock signal (13), an AND gate (5) supplied with the output of the exclusive-OR gate (4) and that of the first flip-flop (3), and a second flip-flop supplied with the output of the AND gate (5) and a fourth clock signal (15) having twice as high frequency as that of the first clock (12). The input timing pulse can be delayed with high resolution or accuracy.

Abstract: A measurement mechanism which can be implemented in any complex system for measuring the service times required for carrying out specified operations is described for a system having a plurality of components working in pre-emptive mode so that an operation once started by a component can be suspended to perform other operations which are requested by the same or other components if these operations have higher priority levels. The measurement mechanism includes a current status register 16 in which the system causes a status value to be stored representative of the current operation being performed by the system. It also includes a reference status register 18 in which a reference value representative of the operation to be measured is stored. These values are compared through a compare logic circuit under control of a filtering value stored in another register. When a match is detected by the compare circuit, the content of a counter is incremented.

Abstract: The timer circuit according to this invention has a first circuit block to which a source voltage is applied at all times and which includes a memory circuit which is set when an input signal is applied thereto. The timer circuit also has a reference voltage circuit which outputs a reference voltage when the memory circuit is set and which ceases to output the reference voltage when the memory circuit is reset, an oscillation circuit which outputs a train of pulse signals in a predetermined cycle, and a counter which begins to count the train of pulse signals after the reference voltage is outputted. The timer circuit further includes a second circuit block which includes a signal processing circuit which outputs a timer signal while the counter is counting. A reference voltage is supplied from the reference voltage circuit to the components of the second circuit block while the memory circuit remains set and the memory circuit is reset in response to a time-out signal from the counter.

Abstract: A semiconductor integrated circuit constructed on a single chip. Either one of a signal inputted to a clock signal input terminal and a signal obtained by dividing the frequency of the clock signal inputted to the clock signal input terminal is selected by a selecting circuit responsive to a selection signal supplied from the exterior of the chip to be supplied to a control circuit. Consequently, the frequency dividing circuit can be bypassed in response to the selecting circuit. Accordingly, it is possible to easily provide operation at a high frequency exceeding the maximum operating frequency of component devices forming the semiconductor integrated circuit. This can be done by connecting an external circuit having the same function as that of the circuit bypassed and capable of higher-speed operation.

Abstract: An apparatus for automatically reads a mode of a capstan reproducing speed by counting pulse signals generated from a capstan motor. This apparatus uses a pulse generator for generating pulse signals and, a frequency multiplier for doubling the capstan frequency generator signals. A counter circuit is used for counting output pulse signals of the frequency multiplier, and a gate processing circuit outputs three different reproducing speed discrimination control pulse signals in response to the signals counted by the counter circuit. A detection error compensating circuit outputs an Extended playing mode discrimination signal and a Long Playing mode discrimination signal from a reproducing speed discrimination control signal of the gate processing circuit by being driven by the pulse signals of the pulse generator. A Standard Playing mode discrimination signal is outputted by a logic combination from output signals of the detection error compensating circuit.

Abstract: In a delay measuring circuit (10), an input clock signal (13) is applied to a multitapped delay line (14), the output taps of which are connected to a switch (26) which selects one of the switch inputs for connection to a phase comparator (34) which compares the input clock signal (13), delayed in a delay device (38) to compensate for the delay inherent in the switch (26), with the output of the switch (26). The input clock signal is also applied to a counter (22), and when the phase comparator (34) detects a phase match, the counter value is stored in a latch (32), the counter (22) is reset to a predetermined value, and the counting procedure resumed. The latch (32) thus always stores a value dependent on the delay of an individual delay cell (16-l to 16-N). This stored value can be applied to various uses, such as in a timing watchdog circuit or for generating accurate delays.

Abstract: A multimode electronic timepiece has an electroptic display, an alarm, several pushbuttons and an integrated circuit programmed to keep time. Several timepiece operating modes include a pace mode, wherein audible periodic beeping sounds are produced by the alarm which correspond to the value of a preselected pace of an operator. A first manual actuation of a pushbutton commences a timing event, and second manual actuation of the pushbutton terminates the timing event. An internal program alters the preselected pace and stores an altered pace in response to the time elapsed between first and second actuation of the pushbutton. The program displays the altered pace and causes the alarm to beep at a rate equivalent to the altered pace.

Abstract: A vital microcompressor-based rate decoder for use in a vital processing system in on-board main line railroad and rapid transit automatic train protection systems; the design is such that a method is incorporated for tolerating specific kinds of signal disruption and in such a way that the probability of a wrongside failure has a calculable upper bound. A pickup coil transmits external or wayside signals to an arrangement which involves two channels and which provides period and duty cycle measurement of the pulses resulting from demodulation of the external signals. A counter is employed in each of the channels and a tolerance accumulation rate decoding device is included, the maximum amount of tolerance accumulated, and the minimum time required to accumulate it, being functions of the rate code selected.

Abstract: An actuation counter is disclosed for counting the number of operation cycles of a valve or other electrically actuated device. The counter provides a real-time output display of the count for analysis by an operator. A battery operated counting circuit is configured in a housing and is responsive to the detection of load or actuation current on a conductor to increment a stored count. The actuation current which corresponds to the operation cycles of the monitored device is detected by a current probe. A preferred embodiment the counting circuit includes a delay circuit which operates to prevent an increment in the count due to spurious signals such as those induced by contact bounce. Access ports associated with the counting circuit are provided so that an operator can determined the presence or absence of magnetic fields by the use of a voltmeter. The counting circuit also preferably includes a threshold setting circuit and reset switch.

Abstract: A time-interval meter (10) employs a counter (16) to count the number of cycles of the output of an oscillator (18) that occur between a pulse on a start input line (12) and a subsequent pulse on a stop input line (14). The result is a coarse measurement. A filter (28) filters the output of the oscillator (18) to produce a sinusoidal signal, and the meter (10) refines the coarse measurement by employing analog-to-digital converters (20 and 22) to measure the values assumed by the sinusoidal signal at the occurrences of the start and stop pulses. A calculation circuit (24) employs an inverse trigonometric function of the converter outputs to determine the difference between the phases of the sinusoidal signal at the occurrences of the start and stop pulses, and it adds the time difference associated with this phase difference to the coarse measurement indicated by the cycle count to yield a total interval duration.

Abstract: In data logging applications an apparatus for real-time stamping data includes a reference time base, a short stopwatch circuit operative for generating a short-time stamp, and a long stopwatch circuit operative for generating at intervals a long-time stamp. Data to be logged with the short-time stamp is combined therewith and stored. A controller circuit controls the storage of the data and of the long-time and the short-time stamps. The controller circuit stores the long-time stamp at predetermined intervals.

Abstract: A method of digitally controlling the gate for a timing counter, to open and close the gate based on the occurrence of signal events, rather than on the envelope of the pulse. In a particular embodiment, a digital divider controls the gate, so that, when a pulse burst of RF is encountered, the gate opens on the second signal event. The divider can be programmed to close the gate any number of signal events later. Measurements are taken for an integral number of signal events, while counting time events from a precision clock. A series of measurements can be taken with various integral numbers of signal events for frequency profiling. By incrementing the digital divider from n to n+1 signal events for successive measurements, and subtracting the results, very narrow gates are effectively generated which move through the pulse cycle by cycle for frequency profiling.

Abstract: A method for identifying a measured value of a velocity or speed of an object where a measured value call-in can occur at any time. A chronological spacing of measuring pulses of a speed sensor is measured and a measured value is formed therefrom. The measurement is carried out until either a measured value call-in occurs, a maximum number of measuring pulses is registered, or a maximum measuring duration is exceeded. When no measuring pulse or only one measuring pulse is registered, a distinction is made in the formation of the measured value as to whether a measuring duration corresponding to a minimum velocity or minimum speed is upwardly or downwardly crossed. An initial counter reading is stored at every measuring start and at every first registered measured pulse. A final counter reading is stored at every further registered measuring pulse until either a measured value call-in occurs or the maximum measuring duration is exceeded.

Abstract: A terminal response time analysis system is disclosed for measuring the response time of a terminal system connected to a host processor. The terminal system has a keyboard for inputing information to the host processor and a monitor with a screen for displaying information received from the host.

Abstract: A device embodying the invention for a packet time-division switcher comprises essentially a circuit for detecting beginnings and ends of load interruption periods in the switcher, and a period counter. The detecting circuit is connected to a plurality of input buffer quenes of the switcher and detects a load interruption when all queues signal a state of packet emptiness. A time base of the switcher is inhibited at the end of a period of predetermined duration established by the counter and following the detection of a load interruption. Said duration is predetermined so as to complete the switching of a packet that has been begun. Once the time base is inhibited, the operating of the switcher is interrupted and its power consumption becomes very low. The time base is freed as soon as a packet is received by the queues, and the switcher resumes operating.

Abstract: A first input section inputs a first signal serving as a trigger. A second input section inputs second and third signals having phases opposite to each other to set a time period width. A first data hold section obtains a first hold output in response to the first and second signals respectively output from the first and second input sections. A second data hold section obtains a second hold output in response to the first and third signals respectively output from the first and second input sections. A determination section determines whether the first hold output from the first data hold section or the second hold output from the second data hold section is output first. A selection section selects the second or third signal from the second input section in accordance with a determination result from the determination section.

Abstract: A logic analyzer has a counter/timer that can reconstruct the higher resolution with which data was acquired using multiple phases of the logic analyzer system clock signal. For a two-phase data sampling system, separate pairs of event recognizers monitor the data collected using the two phases of the system clock. Counter/timer control logic uses the information from these separate pairs of event recognizers to control the behavior of the counter/timer so that it can either single count or double count, depending on whether an event was true during both phases or only one phase of the data acquisition, thus allowing the counter/timer resolution to be as high as the information inherent in the data acquired using both clock phases. The counter/timer employed is capable of single or double counting and has two stages, a prescaler and an extension counter/timer, for increased power and cost effectiveness.

Abstract: Equipment using consumables that require replacement after a predetermined number of uses includes counter arrangements for keeping track of the number of uses of each consumable. Even though some of the consumables may replace the same item, the usage count is maintained for each individual consumable. For the consumables, automatic identification of replaced items is provided whereby the counter arrangement is enabled to accumulate usage counts on the correct consumables.

Abstract: An improved digital delay generator (10) for producing an output pulse/signal a preselected time interval after an input pulse/signal. The digital delay generator (10) of the present invention includes a single auxiliary timer (24) which starts responsive to feeding an input pulse thereto. This auxiliary timer (24) is stopped in response to the first generated clock pulse occurring after the input pulse. The timer (24) is then restarted after a preselected number of cycles of the clock pulse such that the total delay between the input pulse (12) and the output pulse (36) is substantially equal to the insertion delay of the single auxiliary timer (24) plus the preselected delay of the single auxiliary timer plus the delay occasioned by the lapsing of the preselected number of cycles of the clock pulse.