Abstract: In an optical disk apparatus, a circuit for counting the number of tracks crossed by an optical head comprises a first storage means for storing a sampling value obtained for each predetermined sampling cycle, a second storage means for storing a sampling value obtained for the immediately preceding sampling cycle and a comparator means for comparing the first and second values each stored within said first and second storage means. If the value obtained by this comparator means is smaller than a predetermined value, then the first value is selected as the count of the number of crossed tracks, and if the opposite is the case, then the second value is selected as such.

Abstract: In the case of setting one comparison timing in one operation period, a select signal is set to the "0" level, by which first, second and third counters are each put in the state of operation of a 1-to-4 frequency dividing counter which produces four frequency-divided outputs sequentially displaced apart in phase in a cyclic order. A first comparison clock is frequency divided by the first counter and its four frequency-divided outputs are used to latch a comparison signal in four first latch circuits in a sequential order, by which the comparison signal is demultiplexed and expanded. A first system clock is frequency divided by the second counter down to 1/4 and its four frequency-divided outputs are used to latch an expected value signal in four second latch circuits in a sequential order, by which the expected value signal is demultiplexed and expanded. The corresponding ones of the outputs from the first and second latch circuits are subjected to logical comparison by four comparators.

Abstract: In a display control apparatus for controlling a display unit for displaying operation performance of an arithmetic processor with reference to a performance signal representative of the operation performance, a first producing circuit (28) produces a peak signal in compliance with a count signal produced by a counting circuit (22) which is for counting an operation number of operation of the arithmetic processor. A comparing circuit (31) carries out comparison between the peak and the performance signals to produce a result signal representative of a result of the comparison. A second producing circuit (29) produces the performance signal with reference to the result signal.

Abstract: A pulse generating apparatus equipped with a first comparator (20) for comparing the count value of a timer register (9) with the reference value of a comparing register (10) in terms of each bit and a coincidence detection circuit (21) responsive to the output values of the first comparator (20) to output a coincidence signal when all the bits of the output values thereof are the same. Between the first comparator (20) and the coincidence detection circuit (21) there are provided a plural-bit mask register (17) whose comparison value is set by a CPU (2) and a second comparator (22) for comparing the comparison value of the mask register (17) with the output value of the first comparator (20) in terms of each bit. With this arrangement, the generation timing of the output pulse can variously be changed by setting one time the mask register (17).

Abstract: A pulse width modulated waveform measurement circuit is provided with a detector for detecting logic level transitions in a pulse width modulated waveform during a measurement interval, a counter for counting clock pulses, and a gate circuit for enabling the counter during a time period corresponding to the width of a preselected pulse in the pulse width modulated waveform. A comparison circuit is provided for comparing the output count from the counter with a predetermined count and for comparing the number of logic level transitions detected during the measurement interval with a predetermined number to obtain an indication of the operational status of the pulse width modulated waveform. In an alternative embodiment, the gate circuit enables the counter during time periods corresponding to the widths of successive pulses in the pulse width modulated waveform.

Abstract: A pulse generating circuit equipped with a data register (17) in which there are stored data to designate output terminals (14a to 14m) which generate output pulses and data to define the output states of the output terminals (14a to 14m). Also included in the pulse generating circuit is a decoder (16) for decoding the contents of the data register (17) to output the decoding result to a port latch (15) having the output terminals (14a to 14m), so that one selected from the output terminals (14a to 14m) generates the output pulse.

Abstract: In a method and circuitry for variable single transition counting, a count signal (178) is provided on a count line. A direction control bit (264) is output on a direction control line. A significant bit (278e) is output on a significant bit line. A first single transition count (278a-d) is incremented in response to the count signal (178) and to the direction control bit (264) having an incrementing logic state. The first single transition count (278a-d) is decremented in response to the count signal (178) and to the direction control bit (264) having a decrementing logic state. The first single transition count (278a-d) and the significant bit (278e) together form a second single transition count (278a-e). The second single transition count (278a-e) is compared against a preselected value (296), and a comparison signal (320) is output in response to the second single transition count (278a-e) being equal to the preselected value (296 ).

Abstract: A method and apparatus for real time processing of digitally encoded pattern information suitable for distributing such information to a large number of individual pattern applicators which are grouped into a number of successive arrays. When applied to a patterning process involving the selective application of dye streams to a moving substrate, the disclosed real time processing includes transforming pattern data to corresponding dye contact times, resequencing the transformed data to compensate for physical spacing between arrays, and converting the resequenced data to logical dye stream contact commands to be sent to the individual applicators.

Abstract: A start-stop synchronous communication speed detecting apparatus includes a counter, a speed determining unit, a clock switching unit, a shift register, a character determining unit, a code generator, and a controller. The counter counts a time period, in which received data is a space polarity, in start-stop synchronous communication. The speed determining unit compares the count value with a time per bit of a specified communication speed. The clock switching unit selects a clock synchronized with the start bit of the received data and having the same frequency as that of the specified communication speed. The shift register stores the received data. The character determining unit compares a received character from the register with a predetermined character. The code generator supplies codes of the first to Nth characters to the character determining unit.

Abstract: A programmable state counter generates an output signal when a predetermined count sequence matches a programmed input data pattern. A synchronous maximal length shift counter generates 2.sup.N -1 unique output states as a predetermined count sequence. A string of first flipflops receive the programmed input data pattern at first data input and the predetermined count sequence at second data inputs. The first and second data inputs of first flipflops are combined as a logical exclusive-NOR operation. A second flipflop has a first data input wired-OR'ed to inverted outputs of a first portion of the first flipflops, and a second data input wired-OR'ed to the inverted outputs of a second portion of the first flipflops. The first and second data inputs of the second flipflop are combined as a logical OR operation for providing the output signal of the programmable state counter.

Abstract: A circuit arrangement for converting the bit rate of a frame structured input signal to a predetermined nominal bit rate. The data bits of the input signal are written into an elastic store (6) at the bit rate of such signal by means of a write address counter (7), and subsequently read out again therefrom by means of a read address counter (8) at a rate within a tolerance range of the nominal bit rate. A phase comparator (16) determines the distance between the counts of such counters and produces a control error signal corresponding to such distance. In order to minimize jitter of the read out signal, the control error signal is supplied to a control circuit (18) which controls the clock produced by a clock generator (17) for the read address counter (8). The clock generator circuit includes a frequency controllable oscillator, the output of which serves as the read clock.

Abstract: A variable frequency dividing circuit according to this invention switches a frequency division ratio immediately after a neew frequency division ratio has been input, and then performs a frequency dividing operation without discarding already counted values. This frequency dividing circuit generates an error signal if a newly input frequency division ratio differs from the previous frequency division ratio and the already counted value is larger than the new frequency division ratio. Furthermore, the frequency dividing circuit performs forcibly a frequency division completion processing according to the consecutively input frequency signal.

Abstract: A frequency discriminator circuit is provided having increased resolution for detecting the frequency of a data input signal above and below a predetermined frequency threshold by monitoring a count value. The output signal of the frequency discriminator circuit remains at a first logic state provided the count value is reset by the data input signal before reaching a predetermined count value signifying that the frequency of data input signal is above the predetermined frequency threshold. The output signal of the frequency discriminator circuit switches to a second logic state if the count value reaches the predetermined count value before receiving a reset signal thereby indicating that the frequency of data input signal is below the predetermined frequency threshold.

Abstract: A method divides a recurrent digital clocking signal into a quotient digital signal having a substantially symmetrical duty cycle within a range of programmable quotients, the quotients being selectable in single increments of the recurrent digital clocking signal within a range as selected by a divisor.

Abstract: A system and method counts the maximum and minimum number of continuous cycles in which a RISC system event occurs. Additionally, a hold enable input offers the functionality of counting max/min events that are not continuous in time. These maximum and minimum counts are useful for benchmarking performance measurements and for performance debugging. The system and method provides a self-test mode for component testing, as well as maximum, minimum, and accumulator counting modes for use in a programmable performance analysis system. These counting modes allow various aspects of a target system to be categorized for performance analysis. The system has applicability in workstations and RISC systems having high frequency requirements typically greater than 50 Mhz.

Abstract: A high speed counter employs a number of functional blocks, flexibly interconnected on a bus structure, to provide efficient and high speed implementation of arbitrary range measuring tasks. A set of independent counters blocks are connected by the bus structure to programmable comparator blocks which establish count thresholds. The output of the comparators are paired by switchable AND/OR blocks to create ranges. The division of functions by block and the interconnecting bus structure allows the structure of each counter to be effectively programmed to fit the application at hand.

Abstract: A watchdog timer capable of detecting clock signals when the opening frequency of a frequency source drifts lower or higher than a normal desired operating range, increasing circuit safety and reliability. The timer uses first and second clock oscillation circuits to generate first and second signals of frequencies f.sub.1 and f.sub.2 which are then divided by 1/N.sub.1 and 1/N.sub.2 in first and second frequency dividers, respectively. Third and fourth frequency dividers are used to divide the second frequency signal f.sub.2 by 1/N.sub.3 and 1/N.sub.4, respectively. A scale of N.sub.5 counter is connected to receive the f.sub.1 /N.sub.1 frequency signal as a clock input and the f.sub.2 /N.sub.3 frequency signal as a reset input, and provides an output signal at a frequency of (f.sub.1 /N.sub.1)/N.sub.5 which is less than f.sub.2 /N.sub.3 when the clock circuits are operating under normal conditions. A scale of N.sub.6 counter is connected to receive the f.sub.2 /N.sub.

Abstract: A programmable circuit for sampling an IR signal is responsive to a clock signal and a plurality of programmable factors which establish the characteristics of the sampling pattern. The circuit provides successive groups of samples whose resolution, phase and periodicity are established by the programmable factors such that IR signals characterized by different formats may be conveniently accommodated by the same hardware.

Abstract: An anti-fraud device for digital measuring instrument includes a sensing encoder integrated circuit combinably packed with a sensor, and a measuring decoder integrated circuit combinably packed with a measuring meter for receiving signal as sensed from the sensor through a transmission line. When an external-signal generator is fraudulently installed on the transmission line for increasing output signals into the meter for cheating a meter fare, an external signal from the external-signal generator will be first checked by the measuring decoder integrated circuit provided before the measuring meter to be different from a prestored data in the measuring. Then the measuring decoder will not output a valid pulse to be counted in the measuring meter, without increasing an unwanted meter fare or fees for preventing a fraud matter.

Abstract: A circuit configuration for improving the resolution of successive pulsed signals over time includes first and second counters each having one clock input, the clock input of the first counter being supplied with a first clock signal, and the clock input of the second counter being supplied with a second clock signal having a n-multiple frequency of the first clock signal. The first counter has a control input and a counter output, the control input of the first counter being supplied with successive pulsed signals. The second counter has a counter input, an overflow output and a write input, the write input of the second counter being connected to the overflow output of the second counter.

Abstract: An automatic anomalous event detection method uses a pair of counters to count the occurrence of main triggers simultaneously with the occurrence of advanced triggers indicative of anomalous events as defined by an operator. The anomalous events may be defined as either time or voltage qualified events that occur at a much lower rate than the repetition rate of an input analog signal being measured. When the main trigger counter reaches a maximum count, the count of the advanced trigger counter is compared with a range greater than zero to less than the maximum count modified by an operator specified divider. If the advance trigger count is within the range, then an anomalous event is detected and the next advanced trigger signal causes a portion of the input analog signal to be acquired for storage in a waveform memory and subsequent display of the anomalous event.

Abstract: A processing circuit is provided for signals (S.sub.1, S.sub.2) supplied by two transducers measuring a physical quantity parameter in a differential mode and delivering a signal representative of this parameter. This processing circuit essentially comprises a first counter for counting within a measurement period an integer N.sub.1 of periods T.sub.1 of the signal S.sub.1, a second counter for counting within this period of measurement an integer N.sub.2 of periods T.sub.2 of the signal S.sub.2, and a logic circuit to deliver a signal S.sub.m representative of the difference between the interval N.sub.1 .multidot.T.sub.1 and the interval N.sub.2 .multidot.T.sub.2, this signal being representative of the value of the physical parameter. The circuit is useful for measuring acceleration, force, pressure or temperature.

Abstract: In a method and an apparatus for determining the frequency of short oscillation bursts of electrical signals firstly oscillation bursts in desired number are read into a storage means and read out again cyclically adjoined to each other so that an oscillation train of any desired length results of which the mean frequency can be easily determined.

Abstract: A dual-edge frequency counter and method for minimizing the effects of duty cycle modulation. In its simplest form, a dual-edge counter (50) includes a first counter (52) that accumulates reference clock pulses between successive rising edges of an input signal. An input signal is also applied to an inverter (54), which inverts the square wave signal prior to applying it to a second counter (56) that also accumulates reference clock cycles between successive rising edges of the inverted sensor signal. A summation junction (60) totals the accumulated counts from the first and second counters so that they can be averaged by a divider (62), which divides the total count by two. The technique is also employed in connection with a frequency counter that includes an integer counter (72) for totaling the number of cycles of the sensor signal occurring during a sample time defined by successive gate signals.

Abstract: Apparatus for controlling the time constant of a signal includes an up/down counter for counting pulses of a clock signal. The count value is utilized as output signal. The output signal is compared with the input signal to provide a first control signal determinative of whether the counter counts up or down. The output signal is compared with the input signal offset by a constant value to provide a signal which is ORed with the first control signal, and the ORed signal is utilized to enable/disable the counter. Applying a constant offset value to the input signal to be compared precludes the system from alternately counting up and down by one unit value during intervals of relatively constant amplitude input signals.

Abstract: In order to compare the total reached by a counter counting pulses from a source with a given number, the more significant digits from the counter are compared with the corresponding digits of the given number. The comparator produces an output when the groups of more significant digits are equal. An adjusted output taking account of the less significant digits of the given number is obtained by delaying the output by a time period equal to that required for the number of pulses from the source to be incremented by the number represented by the less significant digits of the given number. The time delay is provided by a multi-stage shift register using the pulses from the source as shift pulses, the output from the comparator being applied to the first stage and the adjusted output being derived from a stage selected according to the less significant digits of the given number.

Abstract: Digital ratiometer and amplitude analyzer using such a ratiometer.It is possible to solve the problems of the calculation and display of the ratio of two or more quantities, provided that the latter are converted into frequencies. Counting registers are used for evaluating these quantities. The filling of these counting registers (6,13) is prevented by bringing about a shift to the right (10,19) of all the registers as soon as (15) one of them is filled.

Abstract: A machine position detecting apparatus according to the invention detects the absolute position of a machine by a pulse coder or the like attached to a movable element. Whenever the movable element of the machine is stopped, a check is performed to determine whether the detected position of the movable element is accurate. This is accomplished by a counter for counting the amount of shift of an absolute position detector circuit in one revolution based on a rotational position signal, and a collator for collating contents of the counting means with contents of position memory means and checking the stored contents of the position memory means when the movable element is stopped.

Abstract: A card counter (10) prints card inventory information locally and communicates with a remote computer (43) for permanent storage and retrieval of inventory information. A microprocessor controller detects a counting error in response to the actual count failing to match a preset count, failing to match a precount information machine read from a machine readable precount label (130) attached to the cards (18), in the event of a phrase error from a pair of parallel scanning card sensor circuits (58, 59) or if the final counts of the two card sensor circuits (58, 59) do not match. In the event of detection of a counting error, an error indication is provided and entry of the count into an accumulator memory is inhibited. The present number is entered into memory by selectively entering an actual count into the preset memory. A pair of separate accumulators are provided for concurrently accumulating totals of two different groups of cards (18).

Abstract: A multi-function high speed sequencer is provided in a high speed instruction processor. The high speed sequencer comprises a first input latch coupled to logic signals for producing a first sequence signal. A chain of alternately clocked even and odd principal latches are coupled to the output of the first input latch to produce even and odd principal sequence signals for accessing a high speed MSU. A plurality of staging latches are coupled between the odd and the even principal latches for producing even and odd secondary sequence signals for accessing a slower speed MSU.

Abstract: A frequency divider circuit is responsive to first and second digital input signals and an input clock signal for providing an output clock signal operating at a frequency equal to that of the input clock signal divided by the ratio of the first and second digital input signals. A register is initialized to a predetermined digital value for providing a first digital output signal. The first digital input signal is subtracted from the first digital output signal to form a second digital output signal for the first logic state of a digital control signal; otherwise the second digital output signal is set equal to a least significant portion of the first digital input signal for the second logic state of the digital control signal. The second digital output signal and the second digital input signal are added together for providing the next value of the first digital output signal which is stored back in the register to repeat the cycle.

Abstract: A time delay circuit for providing a delayed replica of a digital input signal including first and second counters for providing first and second count outputs offset relative to each other by a predetermined value indicative of a predetermined delay, and further including a first-in first-out (FIFO) memory for controllably storing selected values of the digital input signal together with corresponding first count output values. First comparison circuitry compares each digital input with the immediately prior digital input, and controls the FIFO memory to store (a) each digital input which is different from the immediately prior digital input, and (b) the first counter output value associated therewith.

Abstract: An input/output circuit of an integrated circuit with a programmable input sensing time. The output driver of the input/output circuit is open drain and is designed for use in a wire-OR configuration with other devices. The input/output circuit is coupled to a bonding pad and through the bonding pad to a device pin, and counts a programmable number of clock cycles between a negation of an output drive signal and when the state of the pin is sampled as an input. Since different applications use a wide range of values for external pullup resistors, the input/output circuit allows adjustment of the sample time to fit a particular application.

Abstract: Disclosed herein is a counter circuit which includes a register for temporarily storing a count data signal, a data processing circuit coupled to the register and supplied with a control signal for producing a first count value from the count data signal in response to a first state of the control signal and for producing a second count value from the count data signal in response to a second state of the control signal, and a counter stage coupled to the data processing circuit and supplied with an input signal to be counted for producing a detection signal when the input signal to be counted is supplied thereto by a time number determined by the first or second count value.

Abstract: A card counter (10) prints card inventory information locally and communicates with a remote computer (43) for permanent storage and retrieval of inventory information. A microprocessor controller detects a counting error in response to the actual count failing to match a preset count, failing to match a precount information machine read from a machine readable precount label (130) attached to the cards (18), in the event of a phase error from a pair of parallel scanning card sensor circuits (58, 59) or if the final counts of the two card sensor circuits (58, 59) do not match. In the event of detection of a counting error, an error indication is provided and entry of the count into an accumulator memory is inhibited. The preset number is entered into memory by selectively entering an actual count into the preset memory. A pair of separate accumulators are provided for concurrently accumulating totals of two different groups of cards (18).

Abstract: A serial clock generating circuit for generating a serial clock in phase with a clock included in a received serial data on the basis of an input clock having a frequency N times of a serial data transfer rate of the received serial data, comprises an edge detector for detecting a level transition of the received serial data so as to generate a level transition detection signal, and a counter for counting the input clock. A first comparison register is provided for comparing a count value of the counter with a first programmable predetermined value at each one counting operation of the counter, so as to generate a first coincidence signal when the count value of the counter is coincident with the first programmable predetermined value.

Abstract: A coincidence circuit for detecting when n-bit binary input data coincides with the current value of an n-bit counter. A plurality of "1" detecting circuits determine, when a corresponding input bit is one, whether a corresponding counter bit is also one. A first-coincidence detecting circuit determines the first time that all the "1" input bits have corresponding "1" clock bits. Each "1" detecting circuit includes an inverter and a NOR gate. The first-coincidence detecting circuit includes an OR gate and a latch circuit.

Abstract: An apparatus for accounting for surgical instruments dispensed into and withdrawn from the surgical operating environment to avoid leaving instruments in the environment comprises a plurality of instrument bearing compartments mounted on a base, a stand for storing surgical instruments after use, and a digital computer programmed to receive signals both from the compartments as a sterile instrument is dispensed and from the stand when a used instrument is stored thereon, convert the signals to numbers of instruments dispensed and stored, subtract the latter number from the former and display the difference. A non-zero different means an instrument remains in the operating environment and must be visually accounted for by operating room staff. The signal from the compartments is preferably generated an interruption of beam of light carried by fiber optic filaments when an instrument is dispensed from a compartment.

Abstract: A timer/counter comprising an operation controller coupled to receive a control information for generating control signals for a selected operation, and a register block coupled to a bus and including a plurality of count registers, a corresponding number of timer registers storing various set values and a buffer circuit controlled by the operation controller to sequentially read data from one of the count registers to the bus and then write the data on the bus to the same count register. An incrementer is coupled to the bus and controlled by the operation controller to increment the data on the bus and to output an incremented data to the bus. A coincidence flag coupled to the register block is set when the incremented data in a count register of the timer block has coincided with a value stored in a corresponding timer register. A clear controller coupled to the coincidence flag clears the count register having the count value in coincidence with the value of the corresponding timer register.

Abstract: Frequency counter-locked-loop apparatus for controlling digitally programmable oscillators includes an arrangement for locking the output frequency of the oscillator to an accurate frequency reference. Frequency, reference and delay registers, a counter and a comparator are configured in a feedback path from the output of the oscillator to its input for continuous control of the output frequency.

Abstract: An initial value setting system for an electronic device having system clearing means for generating a trigger pulse in response to power source voltage fluctuation, counter means for counting intervals between the trigger pulses generated successively by the system clearing means, and initial value setting means for undergoing an initialize operation of the electronic device in response to the counter means. In accordance with the present invention, an erroneous execution of all-clear due to electrostatic disturbance noise can be prevented by counting interval or number of the trigger pulses, and discreminating whether or not the initial value setting means should be operated.

Abstract: The pulse signal generator produces a repetitive pulse output signal consisting of repetitive pulse groups which may have either constant pulse intervals or staggered pulse intervals. Each pulse in the group also has an adjustable pulse width and may be time referenced to a clock pulse signal. The pulse generator employs cascaded stages of individual pulse generators: one stage for each pulse in the group. The first stage generates the first pulse in each group of n pulses and additionally controls the pulse group repetition interval and the pulse width of each pulse.A first counter/comparator generates a first start-pulse, when it counts N.sub.1 clock pulses. The start-pulse resets the first counter and triggers an output bistable (multivibrator) circuit, which initiates the leading edge of the first output pulse of the group. When N.sub.

Abstract: A data processor and method includes a timer system for producing a first output compare signal when a counter value equals a compare value. A register alternatively produces a second output compare signal in response to having a given bit value written therein. Logic circuitry provides an output compare function in response to either the first or the second output compare signals.

Abstract: A technique for accurately controlling both the pulse repetition interval and pulse width of a pulse signal generator which uses a crystal oscillator to maintain a very accurate time base. Two separate digital counters clock-in the clock pulses. When the desired number of clock pulses are registered by the first counter, a first digital comparator generates a start pulse which resets the first counter and triggers an output flip-flop. The change of state in the flip-flop enables the second counter to begin its count. When the desired number of clock pulses are registered by the second counter, a second digital comparator generates an end pulse which resets the second counter and triggers the flip-flop a second time. The second change of state of the flip-flop disables the second counter until the first comparator generates a new start pulse.

Abstract: A frequency divider for dividing input pulses by a predetermined number is formed of an input means for receiving input pulses, a plural number of counters, each having a series connection of stages through which a count signal is respectively shifted in response to the input pulses. The numbers of series stages being selected so that they do not have any common divisor and have a minimum common multiple larger than the predetermined number pulse one. The frequency divider also includes a detecting means for detecting common occurrence of said count signals at selected stages of respective counters, and an output means for producing an output pulse in response to the detection by the detecting means.

Abstract: An electronic signal synchronization apparatus useful with radars and other electronic systems requiring synchronizing signals provides, for a range of N pulses, M sets of synchronizing signals which occur at M different range event pulse counts. The signal synchronization apparatus comprises a microprocessor and a synchronizer, the latter including a range pulse counter, a range memory, an event counter and an event memory. The range memory, preferably a RAM, is connected for outputting an event count enabling signal each time the range counter reaches an event pulse count. The event counter increments one count each time a count enabling signal is received from the range memory. At each event count, the event memory outputs the corresponding set of synchronizing signals. At the Nth range pulse count, the event memory provides an END OF RANGE signal which resets the range and event counters to thereby enable the counters to repeat the counting as many times as is necessary.

Abstract: A method for the digital slope control of the output signals of power amplifiers, as well as a power amplifier suitable for carrying out the method as described. One way of representing the actual slope value is via the number of clock pulses applied to a counter during a measuring interval which depends in its duration on the slope. Such a measuring interval is produced by applying the pulses of a ring oscillator containing one of the power amplifiers to another counter until the overflow of the latter. Another mode of representing the actual slope value consists in counting the number of pulses of the ring oscillator during a measuring interval of predetermined duration. Actual and nominal values of the slope are compared. The results of this comparison change the contents of a left/right-shift register.

Abstract: A pulse generating circuit which, when a counting value of a counter and a value previously set at a register are coincident with each other, converts an output into the preset level to thereby generate each elementary pulse, and is provided with a register buffer for storing therein a value for defining the time, when the level of the pulse output is reconverted so that when the level of the pulse signal is converted, the stored value of the register buffer is set in the register through no software to thereby eliminate the influence on software processing with respect to the elemental pulse width, and is provided with a counter buffer for storing therein a counting start value to be set at the counter in addition to the above-mentioned construction so that the value is constructed to be desirably changeable to thereby enable the counting start value of the counter to be changeable each time the overflow occurs, thus enabling the cycle duration of the pulse signal to be changed with ease.

Abstract: Data processing methods and circuit arrangements are provided whereby out of a succession of data, some or most of which are false due to interference or noise, only those most likely to be true are selected for transmission to following stages of processing. Selection is achieved by comparing, according to a predetermined criterion, successive input data words with a data word already held in a data store and updating the store by discarding the stored data word and replacing it with an input data word whenever an input data word meets the predetermined criterion. A stored data word is utilised in further processing only when a predetermined number of input data words have been compared with the stored data word without updating having occurred. The invention has particular relevance to optical pyrometry systems.

Abstract: A multi-marker, multi-destination timing signal generator including a count-setting memory for storing a plurality of pulse-count values in a numerical order and a pulse counter for counting the number of pulses from a master clock. An output selection memory stores, for each pulse count value, enabling signals for a plurality of output elements so that a marker signal generated when the pulse counter equals a pulse-counter value in memory may be selectively routed to one or more output elements. The addresses of the count-setting memory and the output selection memory are maintained by an address counter. When the value of the pulse counter equals a pulse-count value stored in the count-setting memory, the address counter counts to the next address value for locating successive values in the count-settiong memory and the output selection memory.