Abstract: A laser velocimeter signal processor for measuring the signal frequency within a signal burst. The input signal is converted to digital by an ADC 16 and then shifted into shift registers 30 and 31. An automatic gain circuit 15 controls the gain of the input signal. A signal integration circuit 32 determines when a signal burst has been captured by the shift registers and and then transfers the contents of the registers to data latches 33 and 34. The data in data latches 33 and 34 is processed by digital bandpass filters 57-63, square law detectors 64-70, burst counters 71-77 and signal processor 78 to determine the frequency of the signal within the captured signal burst.

Abstract: The circuit comprises two counters, one of which (A) operates at the irregular rate of asynchronous pulses applied to its count input (2), the other of which (B) operates at a regular rate which is not less than the average admissible rate for the asynchronous pulses, being clocked by an oscillator (5) providing pulses at a stable rate, a comparator (6) inhibiting the oscillator (5) each time the counter (B) catches up the counter (A) and a catch-up preventing control logic circuit (9) inhibiting the counter (A) whenever it tends to catch up the counter (B).

Abstract: Apparatus for asynchronous reception of high-speed data in packet form in a receiver in a telecommunication system where transmitter and receiver are in communication in selected time slots over a common bus. The apparatus includes a delay line (7) receiving the incoming signal and having a plurality of taps, each of which feeds the signal to its own shift register. A locking circuit (10) is furthermore arranged, which stops the stepping forward in the shift register when the first "one" therein has come to a given position, and counting means (12) which senses this given position in each shift register and sums the sensed "ones". A comparison circuit (14) compares the obtained sum with a value constituting the criterion for the number of sensed "ones" representing a received "one".

Abstract: A variable timing sequencer for producing sets of data which correspond to different current states of the sequencer, wherein the interval of each such set of data corresponds to said current state and user input, and said current state is determined by a previous state and input data. This separation of the time domain sequencing from the functional sequencing allows operation of functional components at lower frequencies than the timing components and the increase of effective memory density. The ability to affect both current state and interval by means of an input permits the sequencer to be used in a variety of conditions and applications with a minimum amount of reprogramming.

Abstract: An apparatus for recognizing relative extrema in a dispersive digital data word sequence which includes relatively few, simple component elements specifically including a comparator which generates a positive or zero logic signal depending on the sign of the word comparison between two successive words, a counter operating within a limited numerical range for counting the comparator output signals upward or downward, and a threshold detector responding when a given counter status is exceeded or fallen short of for maximum or minimum indication, and which due to its structurally and operatively simple design ensures real-time processing of scattering data word sequences with a high word frequency, e.g., 500 MHz.

Abstract: A programmable counter/timer is responsive to signals on a data line for producing signals on one or more output lines and includes a counter connected to the data line, a comparator connected to said counter for producing a control signal when said counter reaches a stored preselected value, and a qualification unit connected to the comparator, the qualification unit having a register for storing a logic state. The qualification unit is responsive to the control signal and the stored logic state for generating a signal on selected output lines when the counter reaches the predetermined stored value.

Abstract: A pulse generator with adjustable pulse frequency, pulse width and pulse delay contains a start-stop oscillator (1) whose oscillator pulses are counted by a counter (2) in adjustable counting cycles. After each counting cycle, the oscillator (1) is shut down for an adjustable time interval. The pulses of the output signal of the pulse generator are produced at the occurrence of a predetermined count value, and the end of these pulses is essentially determined by a second predetermined count value. As the oscillator (1) has a fixed operating frequency and for the purpose of frequency interpolation is periodically shut down during short time intervals and then restarted, a pulse generator is obtained having very small frequency deviations over a wide frequency spectrum.

Abstract: Pulses of constant pulse frequency but varying duty cycle are generated in a pulse generator which provides pulse trains or pulse sequences, as controlled by a pulse train or pulse length or sequence control unit coupled to the pulse generator and controlling the pulse generator to emit a train or sequence of pulses of similar pulse lengths, and further including a pulse length modulation control unit (12) coupled to the pulse generator and to the pulse train or sequence control unit, to control the length of the pulses of the individual pulse trains, the pulse lengths increasing in sequential pulse trains to provide an output signal of increasing intensity. The output from the pulse generator is filtered with respect to the base frequency, for example 800 Hz, and generated square wave pulses are converted into sawtooth wave pulses by a RC circuit to increase the dynamic range of output obtainable.

Abstract: There is disclosed herein an up/down counter with a programmable terminal count. The up/down counter has a two level input structure such that new terminal counts may be written into the up/down counter asynchronously without disturbing operations of the up/down counter. Although the invention is described in the bidirectional sense, certain of the features are also applicable to unidirectional counters.

Abstract: An all digital equivalent to a voltage controlled oscillator with low intrinsic jitter and the absence of sample aliasing within a nonzero bandwidth, the offset (non-symmetrical) digitally controlled oscillator comprising a divider (divide by n or n-1) which is timed from a high speed reference clock, a 2.sup.m counter and a digital comparator. The divider divides the high speed reference clock signal so that for every thirty second cycle of the high speed reference clock a pulse is output from the present invention. The output pulse is input to the 2.sup.m counter and increments same. The 2.sup.m counter counts the number of output cycles (or pulses) that have occurred since the last phase adjustment and comares this m-bit number to the input to the present invention. When the output of the 2.sup.m counter becomes greater than or equal to the input, a divide by n-1 signal is sent to the divider which shortens the output cycle and adjusts the average output frequency and phase. The 2.sup.

Abstract: A method and apparatus for dividing a clock pulse frequency Cl in a ratio A/B, where the quotient between B and A is the whole number C and the remainder D. A pulse train is generated, which includes (A-D) half pulses with a pulse length of C clock pulses and also includes D half pulses with a length of (C+1) clock pulse lengths. The difference between C and (C+1) is the deviation in pulse length of the divided clock pulse frequency.

Abstract: A delay circuit comprising a plurality of cascaded saturating circuit elements is provided. The delay circuit may be incorporated in such circuits as modulators and demodulators to provide signal delay.

Abstract: Apparatus for sensing the passage of sheets (1) through a nip formed by rollers (5 and 6), includes means for sensing the deflection of one roller relative to the other, the sensing means including an oscillator (18) providing a train of signals the frequency of which varies with the amount of the relative deflection of the rollers, and a counter (19) counting the signals from the oscillator in a fixed time interval. Means (23) are provided for storing counts representing the relative deflections of the rollers in a cycle of movement of the rollers when no sheet is present, and for comparing the difference between a subsequent count and a stored count for a corresponding position in the cycle of rotation of the rollers, with a predetermined threshold, to establish the presence or absence of a sheet between the guide members. The sensing means may comprise a core (14), moving with the shaft of one of the rollers, and a solenoid (15) connected to the oscillator circuit.

Abstract: A pulse width control circuit for providing a control signal to adjust variations of electrical characteristics among a plurality of printing elements has an up/down counter and a plurality of control signal generating circuits. The up/down counter counts the number of pulses of a clock signal and delivers the counted value. The control signal generating circuit compares the counted values from the up/down counter with set values corresponding to conduction time periods of the currents used for driving light emitting diodes, and generates a plurality of control pulse signals having pulse widths whose central positions thereof are in accord with each other.

Abstract: A duty control circuit for controlling a duty factor in various industrial applications is proposed. It comprises a n-pulse counter, a m-pulse counter, another n-pulse counter, and a magnitude comparator. The magnitude comparator compares the count of the first counter with the count of the third counter and the duty control circuit gives a signal corresponding to ON when the former is larger than or equal to the latter and a signal corresponding to OFF when the former is smaller than the latter.

Abstract: A digital filter circuit includes first and second counters which set and reset a latch circuit at predetermined counts. Clock pulses and the input signal are passed through a gate circuit to the first counter which outputs a set signal to the latch circuit only if the input signal is maintained at a high level for the predetermined count. Clock pulses and the inverted input signal are passed through a gate circuit to the second counter which outputs a reset signal to the latch circuit only if the input signal is maintained at a low level for the predetermined count. In this manner noise pulses on the input signal are filtered out of the output signal obtained from the latch circuit.

Abstract: Counter circuit apparatus which sequentially re-allocates lower-order counting operation in order to extend counter life. The counter is comprised of a plurality of lower order counters and at least one higher order counter. A count selection circuit is coupled to the plurality of counters which controls the counting thereof in response to applied event input signals. A map control circuit is coupled between the higher order counter and the count selection circuit which controls the count selection circuit in response to signals derived from the higher order counter. The map control circuit sequentially enables a predetermined one of the lower order counters to count individual ones of the applied event input signals. A count unscrambling circuit is coupled to the plurality of lower order counters and the map control circuit which produces an ordered count output signal that is indicative of the number of event input signals counted by the counter.

Abstract: There is disclosed a digital enhancement circuit which responds to the complementary inductance provided by a planar coil sensor which inductance varies in a complementary manner according to the position of a movable member associated with the planar coil configuration. The complementary inductance is coupled to an oscillator whereby the period of the oscillator is varied in a first mode according to a first inductance value and in a second mode according to a second inductance value. These signals are then processed by means of digital processing circuitry to develop a signal indicative of the difference of the periods as divided by the sum of the periods. This signal is a ratiometric signal, and by employing digital counters, one can provide an output signal having a predetermined gain factor and having the above noted ratiometric characteristic which signal is indicative of the position of the movable member as further enhanced by the gain factor.

Abstract: A means to set spark timing in accordance with engine speed includes a counter to count clock pulses between engine speed reference pulses. A read-only memory has successive memory locations each storing an addend quantity and a repeats number. An adder unit, including an accumulator, operates to access the memory locations, and to add the addend quantities to the contents of the accumulator repeatedly a number of times equal to the respective repeats numbers. A comparator produces an ignition firing pulse when the contents of the accumulator corresponds with the reference period number provided by the counter.

Abstract: A circuit for monitoring digital electrical signals which counts events, compares the event count to a threshold value, generates an equal value signal when the threshold is attained and indicates the time elapsed between an initial value and the generation of the equal value signal. The event counter is automatically cleared or reset upon a user enabled automatic clear logic enabling signal. The circuit is preferably configured as a chip employing GaAs Schottky diode field effect transistor logic (SDFL) gates.

Abstract: In the particular embodiment of the invention described in the specification, a variable resistor is connected in potentiometer fashion to a DC power source and a time interval is selected according to the position of the movable contact. The ratio of the partial voltage provided by the movable contact to the full voltage applied to the resistor is determined and an oscillator signal target count for the selected time interval is computed from a count corresponding to the total voltage. The arrangement permits accurate time interval determination which is independent of variations in the supply voltage, variations in resistance value of the variable resistor, or environmental changes.

Abstract: This circuit provides a digital output indicating the presence or absence of the infrared (IR) carrier signal. The incoming IR signal is sampled by a clock at a frequency which is about 4 times the carrier frequency. The high and low samples are tabulated in two counters in a race. When 8 high or 16 low samples are counted, the envelope status flip flop is set or reset, respectively, and both counters are reset. The output of the envelope status flip flop represents the envelope of the IR carrier signal.

Abstract: An output compare system and method for automatically controlling multiple outputs in a data processor includes an output compare mask register for holding a set bit therein. An output compare data register is coupled to a control output of the output compare mask register for holding a data bit therein. Apparatus for initiating an output compare function are coupled to a control input to the output compare mask register whereby the data bit will be transferred to an output of the data processor if the set bit is present. The system and method allow for simultaneous utilization of multiple output compare functions to achieve one-cycle-wide pulses on a timer output pin.

Abstract: A binary ripple counter having exclusive OR coupling elements between the counter bistables for use in a digital delay by events circuit of a display device such as an oscilloscope. The counter is programmable.

Abstract: A device for detecting a momentary cutoff of an AC power source which is used with a data processing apparatus or the like. The device determines that a momentary cutoff has occurred in the AC power source when an actual rotation speed of a motor energized by the AC power source for rotation is lower than a predetermined rotation speed.

Abstract: The disclosed apparatus automatically retrieves desired information on an information bearing medium having information and marks. In the retrieving apparatus, the marks are detected and counted during the feed of the information bearing medium. In accordance with the number of the counted marks, the feeding of the data bearing medium is controlled to retrieve the desired data. The apparatus is provided with at least three mark-detecting means for successively detecting the mark and memory means for memorizing the detections of the mark by the respective mark-detecting means, and a mark counting signal is formed from the content in said memory means and the counting signal is counted in order to eliminate the possibility that one and same mark may erroneously be counted twice or more when the feeding speed of the information bearing medium is abruptly changed.

Abstract: A high-speed programmable timing generator in which a continuously cycling binary count is compared with an input data word. Predetermined bits, starting from the highest-order end of the counter, can be selectively inhibited to effectively vary the cycle period of the counter. The digital word with which the output of the counter is compared can be varied to set the reference phase of the output timing pulse stream. Further, fine delay adjustment of the phase of the output timing pulse stream is effected by a controllable phase-locked loop.

Abstract: A process and an arrangement for generating control signals in a predeterminable phase position relative to an alternating voltage at an at least short term-stable frequency through the utilization of a higher-frequencied, at least short term-stable auxiliary timing pulse. The process contemplates determining the duration of a presettable number of periods of the alternating voltage, in which there are counted the periods of a first auxiliary timing pulse occurring within this duration; counting the periods of a second auxiliary timing pulse of a different frequency which is correlated over a period of time with the first auxiliary timing pulse; and upon coincidence of the period count of the first and second auxiliary timing pulses, generating the control signal. The circuit arrangement consists of standard digital circuits.

Abstract: A counter/divider apparatus employing an array of counters arranged in parallel. Each counter repeatedly counts through a sequence of a number of clock pulses. The number is different for each counter and the numbers are relatively prime numbers. The outputs of the counters are applied to a detector that recognizes a preset combination of output signals which is present after a predetermined number of clock pulses have been received. The detector then produces an output pulse which clears all the counters to their initial states, and the cycle is repeated. The apparatus thus divides the input clock pulses by the aforementioned predetermined number.

Abstract: The invention provides a conversation device having a space key for instructing feeding of a printing tape without printing, a pulse oscillator for producing pulses of predetermined period upon depression of the space key, a counter for counting the pulses generated from the pulse oscillator, a one-shot multivibrator for producing a pulse to indicate that the count value has reached a predetermined value, a flip-flop which is set by the pulse from the one-shot multivibrator and allows the pulses from the pulse oscillator to be supplied to a motor driver for amplifying the pulses and which is reset when the predetermined number of pulses from the pulse oscillator is received and prohibits the supply of the pulse oscillator to the motor driver, and a pulse motor for feeding the printing tape without printing. Therefore, when the flip-flop is set, the motor driver causes the pulse motor to drive the printing tape for a predetermined length corresponding to a plurality of characters.

Abstract: An electronic postage meter includes electronic circuitry for providing an accounting of the number of mailpieces imprinted with postage, and the amount of postage imprinted on such mailpieces. An electro-optic sensor connects with a mechanical drive of a printing drum of the meter to sense successive rotations of the printing drum, one rotation occurring for each imprinting of postage. A comparison circuit compares the one-bit signal provided by the electro-optic sensor with the least significant bit of a count of the mailpieces, which count is provided electronically by the accounting function. Any discrepancy between the least significant bit of the mechanical count and the least significant bit of the electronic count serves as a warning of a malfunction, or of tampering, of the postage unit. An error-signal circuit connected to the comparison circuit terminates operation of the meter upon the occurrence of a discrepancy between the mechanical and electrical counts.

Abstract: A watchdog timer for monitoring the operation of a computer monitors if the period of a writing signal (W.sub.T) generated by each execution of an instruction of a program is within the predetermined duration. The present watchdog timer comprises a register (2) for storing predetermined DATA upon receipt of the writing signal (W.sub.T), a counter (4) which is incremented by a clock pulse (.phi.), a comparator (3) for providing coincidence output signal when content of the counter reaches said predetermined DATA in the register (2), a first flip-flop (F.sub.1) for storing said coincidence output signal for one period of said clock pulse (.phi.), a second flip-flop (F.sub.2) for storing said coincidence output signal upon receipt of said clock pulse (.phi.), a third flip-flop (F.sub.3) for storing output of said second flip-flop (F.sub.2) upon receipt of said clock pulse (.phi.), an AND circuit (G.sub.1) for providing logical product of reverse output (Q.sub.1) of said first flip-flop (F.sub.

Abstract: Apparatus for monitoring the level of liquid in a tank or reservoir comprises a probe formed by a resistive metal element having a high temperature coefficient, and a supply means for the probe. The apparatus further comprises a voltage-frequency converter which is connected in parallel with the probe, two counters which are connected in parallel to the output of the converter, and a subtracting means connected to the outputs of the counters. A time base controls operation of the supply means during a complete cycle to effect a counting operation of the first counter for a given period of time at the beginning of a cycle, a counting operation of the second counter for the same period of time but at the end of the cycle, and operation of the subtracting means at the end of the cycle.

Abstract: An apparatus for monitoring the operation of a press provides outputs indicating the total number of hits and the operating speed of the press as well as the total amount of product produced by the press.Specifically, an N-Pulser is driven by a proximity switch coupled to the press so as to fill an accumulator that maintains a running total of the amount of product produced. The N-Pulser includes a gate that has an enabling input coupled to the proximity switch and a signal input coupled to a clock. When the gate is enabled the output of the clock is permitted to pass through the gate to the input of a counter, the counter having been preset to a state determined by the amount of product produced during each cycle of the press. The gate is disabled when the counter has counted to a predetermined, ZERO, state. The output of the gate is in a parallel fashion coupled to the accumulator, so that a specified number of pulses are dumped into the accumulator as a result of each cycle of the press.

Abstract: Digital circuitry adaptable for controlling dwell in a spark and dwell ignition control system is disclosed. Maximum advance and reference sensors are utilized to produce pulse transitions which determine positions of maximum and minimum possible advance for spark ignition with respect to the position of the engine crankshaft. For each maximum advance sensor pulse transition a main counter starts a sequential running count of speed independent clock pulses wherein the maximum count obtained by the counter is related to engine crankshaft speed. The running and maximum counts of the main counter are utilized by dwell circuitry to determine the time prior to the next maximum advance pulse at which spark coil excitation should occur.

Abstract: A digital system for monitoring the rotational speed of a rotating body, such as a turbine shaft, in order to indicate an overspeed or underspeed condition, features a readily variable reference speed limit. A reference pulse train is generated. The number of pulses from the reference pulse train is counted for a predetermined period of time proportional to a fixed number of rotations of the rotating body, and the resulting count is compared to a fixed reference count. The reference speed limit is adjusted by variation of the frequency of the reference pulse train.

Abstract: A testable time delay apparatus includes means for testing component operation during any stage of system function and means for continuously monitoring and testing component functions. The device is particularly useful in critical process control applications such as in a nuclear reactor control system.

Abstract: Apparatus for sensing a missing or broken wafer in an automated wafer transfer system. The apparatus includes means for moving a wafer transfer mechanism from a first position along a prescribed path. A counter coupled to an oscillator is enabled when the wafer transfer mechanism and a wafer are moved away from the first position. A photosensor senses the presence of the wafer at a second position along the prescribed path and inhibits the counter. The count stored in the counter is compared with a predetermined count corresponding to the time required for movement of an unbroken wafer to the second position. If the counts do not agree, a missing or broken wafer is indicated and corrective action is taken.

Abstract: Sampling data output in the form of digital signals corresponding to changes in a quantity to be measured within a predetermined period or an average value of the sampling data is compared with display data corresponding to the current display. When the accumulation signal obtained by accumulation of the difference between the sampling data and display data exceeds a predetermined value, or an average value having a predetermined difference from the current display data has been counted a predetermined times, the display data is updated.

Abstract: A timer device includes a multiple bit storage circuit to store a numerical value as a series of binary bits and evaluation circuitry to simultaneously compare the value stored in the storage circuitry with a predetermined value. This invention further includes a counter circuit consisting of a multiple bit storage circuit to store an initial counter value, a counter circuit to receive the initial counter value and to decrement the counter in response to a clock signal and an evaluation circuit to produce an output when the counter value is identical to a circuit defined value.

Abstract: A function generator for extracting the square root or other function of a pulse width modulated input signal is disclosed. The function generator utilizes a ROM table (12) which contains values of the inverse of the desired function. Two eight-bit counters (26, 28) are clocked in proportion to the duty cycle of the input signal and the duty cycle of a flip-flop (22), which is related to the output of the ROM (12). The counters (26, 28) keep a running average of the comparison of the foregoing duty cycles and, in turn, cause a four-bit up/down counter (30) and the ROM (12) to cycle in time between the value in the ROM (12) above and below the exact input value. In this manner, the output of a four-bit up/down counter (30) is an accurate interpolated representation of the square root of the input signal.

Abstract: A system for converting the frequency of a pulse train to a binary number includes an output counter which converts the pulse train to the binary number. Sampling time periods are applied as pulses to a comparator through another counter. The number of desired sampling periods is set into the comparator. The comparator enables the counter during the sampling time periods and inhibits the output counter on the termination of the total sampling time periods. The output of the output counter, therefore, is a binary representation of the frequency of the incoming pulse train during the total sampling time period.

Abstract: Apparatus is disclosed for determining whether the duty cycle of a periodic signal produced by an incremental encoder is within a predetermined acceptable range. The apparatus includes an oscillator which produces clock pulses at a substantially higher frequency than the periodic signal and a counter which is effective during a selected period of the periodic signal to add the number of clock pulses produced during that portion of the period when the square wave signal is high and subtract from the accumulated number, the number of clock pulses produced when the signal is low. A detector, in response to the final number held by the counter, determines whether the duty cycle is within the predetermined acceptable range.

Abstract: A vital timer for energizing a vital relay at the end of a preselected time interval generated by a vitally programmed microprocessor. Diverse time data words of the preselected time interval are generated, loaded into diverse registers within the microprocessor, and are incremented by means of a program loop for the duration of the time interval determined by the magnitude of the diverse time data words. The microprocessor includes checking routines for verifying that the selected time interval has correctly been read, that a microprocessor primary clock bears a predetermined relationship to an external auxiliary clock, and that the diverse registers maintain a predetermined count relationship for the duration of the preselected time interval.

Abstract: A frequency translator receives an input frequency signal and an offset frequency signal, and processes the signals digitally in order to obtain an output from a multiplexer. Pulse trains derived from the input frequency are provided to an N-bit shift register. The outputs from the shift register are provided to a multiplexer which is controlled by count signals from the offset frequency. The multiplexer provides, as its output, a single sideband output at a frequency equal to (f.sub.c -f.sub.os)/N, or (f.sub.c +f.sub.os)/N.

Abstract: A digital frequency relay for use in protecting an electrical power transmission line in the event of frequency deviations indicative of a fault condition, including an input device for receiving AC electric signals, and an oscillator for generating a reference frequency, which are connected to respective first and second counters which respectively count the number of output pulses from the oscillator during the AC electric signal positive half-cycle, and during the AC electric signal negative half-cycle. The resultant output from the first and second counters is added and compared with a set value to produce a trip signal for the frequency relay.

Abstract: A remote meter reading system includes a dial register encoder and a pulse encoder both coupled to the same rotary disc of our induction watthour meter. A first electronic data register stores the non-volatile dial register encoder output, and a second electronic data register stores a value consisting of an initial value set by the dial register encoder at start-up time continuously augmented by the output of the pulse encoder since start up. Comparison and selective readout of the two electronic data registers reduces erroneous meter reading outputs.

Abstract: An electrical circuit arrangement for use in a coin counting device is provided. The arrangement is provided with an abnormality detection circuit for generating an alarm signal when any of the optical sensing member of the coin counting device is hindered from operating normally due to adhesion of dust or other causes. The abnormality detection circuit includes a NAND gate, a NOR gate, an OR gate, a counter and an SR-type flip-flop. The first and second detection signal generated from the optical sensing members are supplied to the NAND gate and the NOR gate. The OR gate is supplied with the output from the NOR gate and a reset signal from a reset operator section. The counter is supplied with the output from the NAND gate and the output from the OR gate. In normal operation, the counter counts the level "1" and "0" of the binary logical level alternately, thereby to leave a counting section to continue the counting operation.

Abstract: A wheel speed measuring circuit includes a counter controlled by a wheel speed signal having a frequency proportional to the rotational speed of the wheel sensed by a wheel speed sensor associated with a wheel; a comparator for comparing the digital output of the counter with a predetermined digital value; a wheel speed generating circuit for generating a digital output corresponding to the rotational speed of the wheel on the basis of the output of the comparator; and a pulse generator for generating pulses of a frequency proportional to the digital output of the wheel speed generating circuit, the pulse generator receiving the digital output of the wheel speed generating circuit, wherein the counter receives the output pulses of the pulse generator to count the output pulses thereof for the period of the wheel speed signal or for a time interval relating to the period of the wheel speed signal, and the digital output of the counter is compared with the predetermined digital value in the comparator.

Abstract: Herein disclosed is a reception control system for use with a paper counting machine, which is intended to prevent the excessive reception of the sheets of paper due to the delay in the reception control timing.