Abstract: An exemplary shift register circuit includes a plurality of shift registers for sequentially outputting a plurality of driving pulse signals. Among each M number of the shift registers for sequentially outputting M number of the driving pulse signals, the shift register for lastly outputting one of the M number of driving pulse signals is enabled, by (M?1) number of start pulse signals sequentially outputted from the remained (M?1) number of the shift registers, to generate the driving pulse signal. Herein, M is a positive integer greater than 2. Moreover, a circuit structure of a shift register also is provided.

Abstract: A shift register unit includes an input module for inputting a second clock signal or a third clock signal, and for inputting a frame starting signal, a first clock signal, a low voltage signal, a reset signal as well as a first signal and a second signal transmitted from a next neighboring shift register unit; a processing module for generating a gate driving signal and allowing a level of at least one of first junctions formed by at least two TFTs to be maintained at low level in a frame interval during which the second clock signal or the third clock signal inputted from the input module is maintained at low level; and an output module for transmitting the gate driving signal generated by the processing module.

Abstract: After a sampling transistor is turned ON at a first timing when a control signal has risen, during a sampling period from a second timing when a video signal has risen from a reference potential to a signal potential to a third timing when the control signal has fallen and is turned OFF, the sampling transistor samples and writes the signal potential in a holding capacitance, and negatively feeds back a current flowing into a drive transistor during the sampling period to the holding capacitance and applies mobility correction of the drive transistor on the written signal potential. A signal driver adjusts the second timing for the video signal supplied to respective signal lines to correct a backward shift of the third timing due to a transmission delay along a scanning line of the control signal output from the control scanner.

Abstract: A shift register, each stage thereof provided to drive a corresponding output line, includes an output transistor that drives the output line and an additional transistor of the same technology and of the same polarity as the output transistor. The additional transistor is connected in such a way as to be subject to bias conditions similar to the output transistor, such that the additional transistor's threshold voltage, identical at the start of life to that of the output transistor, drifts as quickly or more quickly as the threshold voltage of the output transistor. The additional transistor is used to adjust the precharging voltage of a gate of the output transistor to its conduction performance characteristics during the precharging and/or selection phase.

Abstract: A shift register applied on a double-frame-rate LCD is provided. The LCD includes an upper display area with c gate lines, a lower display area with d gate lines, and a gate driving circuit. The gate driving circuit includes a first shift register coupled to the corresponding x gate lines of the upper display area, a second shift register coupled to the corresponding y lines of the lower display area, and a third shift register coupled to the corresponding (c-x) gate lines of the upper display area and the corresponding (d-y) gate lines of the lower display area.

Abstract: A column repair circuit uses a system of circuits that automatically stops the shifting of register contents independently of the number of bits to be shifted. The circuit is only dependent on the number of bits in a column address repair block. By adding shift register positions to one end of each shift register chain, a dedicated block of bits is used to detect the end of the shift chain without explicitly knowing the length of the chain. The shift register positions provide a hard-programmed code that can be used to stop the shifting of data automatically. The shift register positions also provide a space for hard-programmed code bits that can be examined to determine when the shift process ends. A shift chain can be controlled with a controller so long as the information is organized into groups of ‘k’ bits. The controller only requires information regarding the value of the number ‘k’ and the pre-programmed stop code in order to control any number of bits in a shift chain.

Abstract: Disclosed is a shift register which includes first transistor connected between a first clock signal terminal and an output terminal, a second transistor with a gate connected to an input terminal and a source connected to a gate of the first transistor, a third transistor with a gate connected to a second clock signal terminal, an inverter with an input connected to the input terminal, a fourth transistor cascode connected to the third transistor with a gate connected to an output of the inverter, a fifth transistor connected between the gate of the first transistor and a power supply terminal, a sixth transistor connected between the fourth transistor and the power supply terminal with a gate connected to the input terminal, and a seventh transistor connected between the output terminal and the power supply terminal, the fifth and seventh transistors having gates connected in common to a connection node of the fourth and the sixth transistors.

Abstract: Disclosed is a dual shift register that includes a first shift register configured to include a plurality of stages which sequentially output scan pulses using at least two clock signals with sequential and circular phases, and a second shift register configured to a plurality of stages which form pair with the respective stages of the first shift register and sequentially output the scan pulses using at least two clock signals. Each stage includes: a scan direction controller configured to respond to the scan pulses from previous and next stages and to selectively output forward and reverse direction voltages with opposite electric potentials to each other; and an output portion configured to respond to the output signal of the scan direction controller, to generate two sequential scan pulses using two of the at least two clock signals, and to distribute the sequential scan pulses to the previous and next stages.

Abstract: Provided is a scan driver that supplies a scan signal to an organic light emitting display device (OLED). The scan driver includes transistors of the same conductivity type. To generate individual scan signals, the scan driver includes samplers, each of which samples an input signal in synchronization with a clock signal or an inverted clock signal; and an OR gate and a NAND gate, each of which performs a logical operation on output signals of adjacent samplers and generates a scan signal. The samplers, the OR gate and the NOR gate include transistors of the same conductivity type.

Abstract: The present invention provides a display device which includes a drive circuit having a CMOS shift register circuit constituted of a simple CMOS circuit. A drive circuit includes a shift register circuit, and the shift register circuit includes n(n?2) pieces of basic circuits which are connected vertically in multiple stages.

Abstract: The LDPC decoder includes a processor for updating messages exchanged iteratively between variable nodes and check nodes of a bipartite graph of the LDPC code. The decoder architecture is a partly parallel architecture clocked by a clock signal. The processor includes P processing units. First variable nodes and check nodes are mapped on the P processing units according to two orthogonal directions. The decoder includes P main memory banks assigned to the P processing units for storing all the messages iteratively exchanged between the first variable nodes and the check nodes. Each main memory bank includes at least two single port memory partitions and one buffer the decoder also includes a shuffling network and a shift memory.

Abstract: A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal.

Abstract: Disclosed herein is a shift register circuit that is formed on an insulating substrate with thin film transistors having channels of the same conductivity type and includes shift stages, each of the shift stages including: a first thin film transistor; a second thin film transistor; a 3(1)-th thin film transistor; a 3(2)-th thin film transistor; a 4(1)-th thin film transistor; a 4(2)-th thin film transistor; a fifth thin film transistor; and a sixth thin film transistor.

Abstract: A shift register includes first and second stages for sequentially outputting scan pulses to drive first and second gate lines. One of the first and second stages includes a pull-up switching device connected to an enabling node of the one of the first and second stages; a first pull-down switching device connected to a first disabling node of the one of the first and second stages; a second pull-down switching device connected to a second disabling node of the one of the first and second stages; and a node controller. The node controller of the first stage controls the logic state of each of the enabling node of the first stage, the first disabling node of the first stage and the first disabling node of the second stage. The node controller of the second stage controls the logic state of each of the enabling node of the second stage, the second disabling node of the second stage and the second disabling node of the first stage.

Abstract: A shift register applied on a double-frame-rate LCD is provided. The LCD includes an upper display area with c gate lines, a lower display area with d gate lines, and a gate driving circuit. The gate driving circuit includes a first shift register coupled to the corresponding x gate lines of the upper display area, a second shift register coupled to the corresponding y lines of the lower display area, and a third shift register coupled to the corresponding (c-x) gate lines of the upper display area and the corresponding (d-y) gate lines of the lower display area.

Abstract: A bidirectional shift register is disclosed which comprises a first and second flip-flop, a first multiplexer having an output coupled to an input of the first flip-flop, and a second multiplexer having an output coupled to an input of the second flip-flop wherein an output of the first flip-flop is coupled to an input of the second multiplexer, an output of the second flip-flop is coupled to an input of the first multiplexer.

Abstract: A shift register and a shift register are provided. The shift register comprises the switch circuit, the latch circuit, and the inverter circuit 170. The shift register set, by alternately-serially connecting two types of shift registers, can receive two clock signals and an initial pulse signal to control the output waveform. The output of the present stage shift register can be used to control the turn-on time of the nest stage shift register. Further, by changing the circuit driving signal from the dynamic signal to the static signal, the circuit can operate only when the signal is “0” or “1” without being affected by the signal rising time and the falling time so that the circuit can operate in a more stable status.

Abstract: A unit shift register includes first and second transistors for supplying low supply voltage to an output terminal. First and second control signals which are complementary to each other are input to first and second control terminals, respectively. A third transistor is connected between the first transistor and first control terminal, and a fourth transistor is connected between the second transistor and second control terminal. The third and fourth transistors each have its drain connected to the gate of each other in a crossed manner.

Abstract: A shift register of the present disclosure comprises a plurality of shift register units using alternating clock signals to shift signals. The shift register outputs signals having substantially no overlap with adjacent signals. The shift register may be employed in a liquid crystal display.

Abstract: A shift register, a driving circuit and a display device using the same are disclosed. The shift register includes a 1st and a 2nd rectifying elements and 1st˜4th transistors. 1st source/drains of the 1st˜3rd transistors receive a common voltage respectively. The gates of the 1st and 3rd transistors and a 2nd source/drain of the 2nd transistor are coupled to a 2nd terminal of the 2nd rectifying element. The gates of the 2nd and 4th transistors and a 2nd source/drain of the 1st transistor are coupled to a 2nd terminal of the 1st rectifying element. A 1st source/drain of the 4th transistor is coupled to a 2nd source/drain of the 3rd transistor. The 1st terminals of the 1st and 2nd rectifying elements respectively receive input signals and a 1st clock signal. A 2nd source/drain of the 4th transistor receives a 2nd clock signal.

Abstract: A unit shift register includes a first transistor for supplying an output terminal with a clock signal, and second and third transistors for discharging the output terminal, and further includes a fourth transistor having its gate connected to the gate node of the second transistor and discharging the gate node of the first transistor, and a fifth transistor having its gate connected to the gate node of the third transistor and discharging the gate node of the first transistor. Input of the clock signal is prohibited just after the change in level of first and second control signals for switching between the second and third transistors.

Abstract: A shift register includes multiple stages connected with each other in succession. The shift register stores the threshold voltage of an amorphous silicon thin-film transistor in a capacitor. During operation, the bias applied to the transistor is adjusted according to the threshold voltage stored in the capacitor.

Abstract: A shift registers circuit having a series of cascading shift registers comprises a first transistor coupling to an output signal of a pre-stage shift register, a second transistor coupling to the first transistor, an output and a first clock signal, and a pull-down module coupling to the output, output signals of pre-stage and post-stage shift register, a second and a third voltage level. When the second transistor turns on and the first clock signal is at high voltage level, the output is at a first voltage level. When the signal of post-stage shift register is at first voltage level, the output is at the third voltage level.

Abstract: A semiconductor circuit system includes a first signal line and n circuit sections (n is an integer equal to or more than 2), each of which has an input terminal and an output terminal. The input terminals of predetermined k ones (k is an integer satisfying 2?k<n) of the n circuit sections are connected to the first signal line, and the output terminal of a m-th one (1?m?n?k) of the n circuit sections is connected to the input terminal of a (m+k)-th one of the n circuit sections.

Abstract: The present invention provides permutation instructions usable in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. PPERM and PPERM3R instructions are defined to perform permutations by a sequence of instructions with each sequence specifying the position in the source for each bit in the destination. In the PPERM instruction bits in the destination register that change are updated and bits in the destination register that do not change are set to zero. In the PPERM3R instruction bits in the destination register that change are updated and bits in the destination register that do not change are copied from intermediate result of previous PPERM3R instructions. Both PPERM and PPERM3R instructions can individually do permutation with bit repetition. Both PPERM and PPERM3R instructions can individually do permutation of bits stored in more than one register. In an alternate embodiment, a GRP instruction is defined to perform permutations.

Abstract: An image processor arranged in operation to generate an interpolated video signal from a received video signal representative of an image. The image processor comprises an adaptable register store comprising a plurality of register elements and is coupled to a control processor which is operable to receive the video signal and to provide pixels of the received video signal, under control of the control processor to an interpolator, selected regester elements being connected to the interpolator to provide the pixels of the received video signal for interpolation, each of the register elements being arranged to store a pixel of the received video signal and each is connected to a plurality of other register elements and is configurable under control of the control processor to feed the pixel stored in the register element to one of the plurality of other register elements in accordance with a temporal reference and the interpolator being coupled to the adaptable register store.

Abstract: A shift register unit. The shift register unit outputs a shift register signal according to a clock signal, an inverse clock signal and a start signal. The shift register has first and second clock inversion circuits, and an inverter. In the first clock inversion circuit, a third PMOS transistor has a third source coupled to the first voltage, a third gate and a third drain. A fourth PMOS transistor has a fourth source coupled to the third drain, a fourth gate and a fourth drain coupled to the second voltage. A fifth PMOS transistor has a fifth source coupled to the third drain, a fifth drain coupled to the first gate, and a fifth gate. A sixth PMOS transistor having a sixth source coupled to the third gate, a sixth drain coupled to the second gate, and a sixth gate coupled to the fifth gate.

Abstract: A bitstream generator including a plurality of linear feed shift registers (LFSRs) operative to generate a bit stream and including: at least a first LFSR operative, when assigned as a generator during a first time period including at least one clock cycle, to provide an output bit in each clock cycle within the first time period, and at least a second LFSR operative, when assigned as an assignor during the first time period, to provide in each clock cycle an output bit for determining assignments of at least some of the plurality of LFSRs for a second time period following the first time period, the assignments including assignment as a generator, and assignment as an assignor, and a first combiner operative to combine output bits from all of the at least a first LFSR being assigned as generators thereby to produce during each clock cycle a single output bit which is provided to the bit stream. Related apparatus and methods are also provided.

Abstract: It is intended to eliminate a malfunction caused by racing, to minimize the time of delay of output from a shift register with respect to an oscillating clock signal, and to reduce the output delay time difference in the shift register. A shift register is provided, which is divided into blocks using a plurality of flip flops and a clock buffer. In the shift register, a plurality of basic cells are arranged serially so that a clock signal is supplied from an opposite direction to that of data flow.

Abstract: An apparatus for operating on the contents of an input register to generate the contents of an output register which contains a permutation, with or without repetitions, or a combination of the contents of the input register. The apparatus partitions the input register into a plurality of sub-words, each sub-word being characterized by a location in the input register and a length greater than one bit. In response to an instruction specifying a rearrangement of the input register, the present invention directs at least one of the sub-words in the input register to a location in the output register that differs from the location occupied by the sub-word in the input register. The ordering of the sub-words in the output register differ from the order obtainable by a single shift instruction. In the preferred embodiment of the present invention, the invention is implemented by modifying a conventional shifter comprising a plurality of layers of multiplexers.

Abstract: A shift register unit has stages. In each stage, a clamping transistor and the control electrode of an output transistor are connected to the output electrode of an input transistor to which an output one stage behind is input. A pull-down resistor is connected to the output electrode of the output transistor. A capacitor is inserted between the control electrode and output electrode of the output transistor. A clock signal is input to the output transistor, and a signal obtained by inverting a clock signal two stages forward is input to the clamping transistor.

Abstract: A shift register matrix including a matrix of cells having a plurality of rows and a plurality of columns, each cell storing one bit of data. A plurality of pulse generators is included to generate pulses to the cells which cause new data to be shifted into the cells. One pulse generator is included for each column of the matrix. The pulse generator for each column is coupled to all the cells in the column. Each pulse generator supplies a pulse to each of the cells in its respective column to cause new data to be shifted into the cells of that column. The pulses are sent to the respective columns in sequential order, one column at a time, until all the data in the matrix has been shifted by one bit.

Abstract: A shift register having several cascaded stages, each stage containing an output at a first node connected to a next stage, a first input connected to an output of a preceding stage, a second input connected to an output of the next stage and a first terminal connected to a first clock signal and a second terminal connected to a second clock signal, the stage containing a first semiconductor device switching the output of the stage between high and low values of the first clock signal, the first semiconductor device being controlled by the potential of a second node, itself connected to the output of the preceding stage across a second semiconductor device controlled by the output of the preceding stage; to a negative potential across a third semiconductor device controlled by the output of the next stage; and to the second terminal connected to the second clock signal across a first capacitance, wherein a second capacitance is mounted between the second node and the output of the next stage.

Abstract: A flip-flop includes non-volatile storage of a bit for encryption purposes or other applications. The non-volatile bit remains in the flip-flop, substantially unaltered, irrespective of normal flip-flop operation, and is available to be recalled whenever it is needed. The flip-flop is implemented using a pair of CMOS cells. Each cell includes a floating gate formed by connecting the gates of an n-mos transistor and a p-mos transistor. One of the two floating gates is selectively charged by hot electron injection, thereby raising the threshold of that cell. Depending upon which of the two cells is programmed by this process, the flip-flop outputs a logic one or a logic zero during a recall mode.

Abstract: A remote control transmission circuit for generating a multicarrier under control of a single microcomputer. This transmission circuit is arranged so as to allow reduction of the number of the program commands and making it easy to perform a different process during the output of the multicarrier. The number of the shift circuits of the shift circuits 2a to 2f which are connected is set by a switching circuit 4. A change-over switch 6 performs the change-over operation as to whether a new shift circuit 5 is coupled. The change-over switch 6 is controlled by an overflow signal of a counter 7 whose count source is an inversion signal of the carrier (multicarrier) output 1. The control of the change-over switch 6 automatically controls the period for the correction of the carrier output 1 without the control due to the microcomputer.

Abstract: A method for the resetting of a group of series-connected non-transparent synchronous memory cells. The method includes modifying the clock signals that control the transfer gates of these cells on the activation of a resetting signal to set all the transfer gates in the on state. The method is particularly suited to the resetting of long shift registers such as those used in cryptographic applications, especially in micro-circuit cards, and the reset circuitry can be implemented using conventional logic gates.

Abstract: A high-speed rotator array for shifting input data a specified amount. The rotator array includes a plurality of straight shift control lines extending across the array for receiving shift data representative of shift values, and a plurality of input terminals for receiving input data to be shifted. The rotator array also includes a plurality of data lines coupled to the plurality of input terminals that extend both diagonally and horizontally across the array. In response to the rotator array receiving the shift data and the input data, a plurality of output terminals transmit the shifted output data.

Abstract: A barrel shifter performs multi-bit shift and rotate operations on data of different lengths using multiplexors to preprocess the data prior to introducing the data to a transistor array.

Abstract: A system for producing voice message keepsakes includes a message processor which may be accessed over a plurality of communication links, such as telephone lines. The processor may be so accessed by a customer's communication set, such as a conventional telephone set, or by a subscriber set, and it is capable of distinguishing the two. When accessed by a customer's set, the processor permits the caller to create a temporary mailbox associated with his gift purchase, in which he may then record a voice message. When called by a subscriber set, the processor permits previously created mailboxes to be accessed and will transfer the message recorded therein to the subscriber set. The subscriber set includes a receptacle for receiving a voice message keepsake in accordance with the present invention, and it will record thereon stored messages provided from the message processor, under control of the message processor.

Abstract: An array processing system has a plurality of processing elements, each of which includes a processor and an associated memory module, and a router network over which each processing element can transfer messages to other random processing elements. The system further includes a shift register which can shift data either toward a shift-in terminal, or toward a shift-out terminal, either one bit at a time or four bits at a time, thus improving processing system speed for floating point arithmetic operations.

Abstract: An interleaved shift register 20 includes a plurality of data storage elements 22a-22d having a common data input signal. Each of the plurality of data storage elements 22a-22d has an enable control input that is connected to one of a plurality of clock signals, each of the plurality of clock signals being incrementally out of phase with one another. Interleaved shift register 20 provides multiple data bits of the data signal to be stored within a single clock period of one of the plurality of clock signals, thus greatly improving the data rate without increasing the storage rate of the plurality of data storage elements 22a-22d.

Abstract: A flexible data interface (21, 22) for a digital-to-analog converter (25, 26) includes a mute circuit (46, 70, 71 ) to mute and de-mute input data in 6 dB steps over a time period such as one-quarter of a second. The mute circuit includes a counter (46) to provide mute signals, a decoder (70) to decode the mute signals, and a shift matrix (71) to shift the data from zero to the maximum number of bits in response to the decoded signals. The interface (21, 22) includes a programmable shift register (43) to allow different data word lengths, such as 20-, 18-, or 16-bit, to be presented to the digital-to-analog converter (25, 26). The interface (21, 22) also includes a multiplexer (47) to allow left- and right-channel data to be received either time-multiplexed on a single pin, or on two separate pins.

Abstract: A counter circuit includes Johnson-type counters of m stages, each counter including a plurality of flip-flops connected in a cascade connection, each flip-flop receiving a clock signal at a respective clock input end. In the constitution, signals at respective output ends of flip-flops in a (k-1)-th stage counter are simultaneously input to respective clock input ends of flip-flops in each counter of a k-th stage and more. As a result, it is possible to obtain a signal having an arbitrary ratio of frequency division with high speed, while relatively simplifying the circuit constitution.

Abstract: The present invention provides a MRP generator comprising m MRP generating circuits connected in parallel which are operated at a 1/m clock speed and have a predetermined time relation to each other, wherein the MRP generating circuits are operated on the multiplex basis. The operating speed is improved.

Abstract: A semiconductor memory has an output data latch circuit controlled in response to a clock signal shifted by a half period from a control clock input to n one-bit shift register stages. The memory device includes a plurality of read data latch circuits, as well as a plurality of write or address data latch circuits, coupled to the n one-bit shift register stages and to a plurality of selector or multiplexor circuits. A noise filter is inserted in a clock input supply path to the n one-bit shift register stages but is not inserted in a clock input supply path to the output data latch circuit.

Abstract: The input nodes and output nodes of a plurality of storing circuits for storing plural-bit data are connected to one another to constitute a shift register. Each of the plurality of storing circuits includes a selection circuit for selecting 1-bit data from the plural-bit data according to a selection signal, a first latch circuit for latching the 1-bit data selected by the selection circuit in synchronism with a first clock signal, and a number of second latch circuits, which number corresponds to the number of bits of input data, for latching an output of the first latch circuit in synchronism with a plurality of second clock signals having phases different from that of the first clock signal. Data sequentially selected by the selection circuit is latched into the first latch circuit and then sequentially latched into the second latch circuit in a time-sharing fashion.

Abstract: An optical printer with a print head having numerous light emitting elements for reproducing medium densities of a multi-tone document image faithfully. When image data are inputted to individual serial shift registers, the entry of next image data is inhibited and, in response to a clock signal having a predetermined frequency, light emitting elements associated one-to-one with the shift registers are each turned on for a particular period of time associated with a logical value of an internal state stored in the associated shift register. The frequency of the clock signal is variable to adjust the turn-on time of the light emitting elements as desired.

Abstract: A shift register is disclosed in which an n-stage shift-register chain (sr) consists of 2n series-connected, like basic cells (zi) which are driven in antiphase by a first and a second shift clock (C1, C2) from a clock generator (g). The nonoverlap range of the two shift clocks is temperature- and frequency-stable, so that the shift register can be used within a wide frequency and temperature range. Frequency adaptation is accomplished simply by changing resistance values.

Abstract: A two phase shift register comprises four serial registers each having an input section, a transfer section, and a lead-in section disposed between the input section and the transfer section. The input sections provide respective sequences of charge samples, the four sequences being offset in phase relative to each other by 90.degree. within the cycle of a clock signal. At least one of the serial registers comprises a first lead-in gate pair and a second lead-in gate pair over the lead-in section, the second lead-in gate pair being between the first lead-in gate pair and the transfer section. The first lead-in gate pair and the second lead-in gate pair are each driven at the frequency of the clock signal, the drive signal applied to the second lead-in gate pair being retarded in phase relative to that applied to the first lead-in gate pair by 90.degree. within the cycle of the clock signal.

Abstract: An improved shift register uses fewer than 2*N latches, where N is the capacity in bits of the shift register and also the propagation delay from the input to the output of the shift register in terms of the system clock. An m-phase set of clocks are used, where m is an even number larger than two and and the duration of each clock phase is one half of the period of the system clock. The latches are arranged in m/2 strings of length 2N/(m-1), instead of one long string. The strings of latches are offset with respect to each other by two phases in terms of their connection to the multiphase clock, with each successive latch in each string being enabled by the clock signal whose phase immediatedly precedes the phase of the clock signal used to enable the preceding latch in that string. A multiplexer at the output puts the data from the multiple strings of latches back into one serial output stream.