Abstract: Apparatus is disclosed for forming scan data path subchains from the elemental memory units of a digital system, and interconnecting the scan data path subchains to form an extended serial shift register for scan testing. The method and apparatus for forming the interconnections ensures that data is passed from one subchain to another without data being lost due to clocking irregularities.

Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.

Abstract: An electronic counter such as for use in the odometer of a motor vehicle is provided comprising an array (10) of m rows and n columns of single flip-flop data latches and a central shifting unit (14). The central shifting unit (14) comprises a row of n data latches arranged to read data from and write data to each of the m rows of data latches of the array (10). In operation, the central shifting unit (14) reads data from a row of data latches of the array, performs a shift operation on the data and an invert operation on one of n data latches of the central shifting unit (14) and returns the data so operated on to the row of data latches in the array (10). By these steps, a counting operation in Johnson code is performed on the data. This invention uses less chip area than known counters.

Abstract: A first-in, first out data memory minimizes fall-through delay. The FIFO memory has a plurality of cascaded register stages arranged in sections, with the input of each section selectively coupled to a bypass bus. Data is introduced on the bypass bus, and control logic writes the data into the section nearest the output which is currently not full. The individual register stages are self-clocked, so that data is then shifted toward the output through any vacant registers. In another aspect, the register stages are arranged in sections of different length, with the shortes section closest to the output and the longest section closest to the input. Decreased fall-through delay is achieved by minimizing the length of the FIFO buffer actually traversed by the data while insuring that the order of the data remains unchanged.

Abstract: A device, and a corresponding method for its operation, for converting binary electrical signals into optical form and for scrolling the optical signals across an array of liquid crystal cells. The device in its two-dimensional form includes an array of rows of liquid crystal cells of the ferroelectric smectic type, input circuits for applying binary signals to an input cell in each row, and a three-phase clocking circuit connected to the remaining cells in each row, to propagate the states of the input cells rapidly into successive cells across the array, in the same manner as a shift register, but with the signals being stored in optical form for ease of processing in optical processing apparatus.

Abstract: A data conversion circuit is constructed in such a manner that a plurality of flip-flop series, each including tandem connected master/slave flip-flops, are provided and driven by plural phase numbers of clock signals which have no overlap therebetween, so that a parallel data is obtained with a serial data supplied to the flip-flop series, or a serial data is obtained with a parallel data supplied to the flip-flop series. The clock signals employed here have no overlap between each of the corresponding phases of the signals.

Abstract: YA dual clock shift register for use in a computer display system for converting a higher resolution image for a computer screen to a lower resolution image for display on a lower resolution display apparatus. The dual clock shift register includes a first shift register which is used to apportion a second shift register between control by two different clock rates.

Abstract: A multiconfigurable integrated circuit having volatile and nonvolatile segments configured and interconnected so that data can be nonvolatilely entered and transferred at high frequency in the volatile segment, so that formerly entered data can be nonvolatilely stored while new data is entered and volatiley utilized, and so that previously stored nonvolatile data can be recalled and volatilely utilized. In one form, the circuit is comprised of a shift register stage selectively connectable to a nonvolatile memory cell structure. Interconnection of multiple circuits and the addition of analog switches creates electronic equivalents of DIP switches and various other multiple pole selectively controlled switching configurations.

Abstract: A power-saving serial data transfer circuit for outputting an inputted digital data signal through a plurality of serially connected shift register cells comprises n (=m.times.k) cells in k groups each containing m serially connected cells. A digital data signal is applied commonly to the first-stage cells of the groups and inputted in a time-wise segmented sequence to the cells by shift pulses with different phases. The inputted data signal is shifted through the cells within the same groups and is inputted to the last-stage cells of the groups. The inputted data signal is also outputted through a multiplexer connected to the last stage cells.

Abstract: A logic circuit building block, referred to as an M Circuit, is provided which solves various problems of prior art logic circuit building blocks and binary logic systems. The M Circuit responds to transitions of a two level binary input signal to provide a memory and a logic function which has a complete truth table for every possible combination of input signal transitions or changes in logic level at a pair of input terminals A and B. The M Circuit generally includes both logic gating and a memory for placing the M Circuit in a set condition in response to the application of first known combinations of input signal levels or transitions at the A and B terminals, and for placing the M Circuit in a reset condition in response to the application of second known combinations of input signal levels at the A and B input terminals.

Abstract: An electronic circuit for regulating the entry of new data into a static synchronous register comprising a bank of D type, master-slave flip-flops. The circuit selectively passes the first phase of a two-phase, nonoverlapping clock signal used for synchronization and control of the data. A bootstrap operated, series pass, transistor configuration couples the first phase signal to the electrode actuating the master stage of each flip-flop. With provisions for the series pass transistor to transition into a conductive state prior to the onset of the first phase signal, the circuit ensures substantial replication of the first phase signal characteristics in terms of both time and amplitude.

Abstract: A memory device which is effectively utilized as serial access memory with variable shift length of stored data is disclosed. The memory device comprises memory cells arrayed in a matrix form, a shift register whose output is used for selecting memory cells and control means for varying shift length of the shift register.

Abstract: A two-dimensional traveling display method and apparatus for displaying data that may be continuously or intermittently changing in a manner of a traveling sign with the traveling display moving either left, right, up or down depending upon a desired format. The display comprises an electrically actuated two-dimensional dot matrix display panel formed by a plurality of rows and columns of dot-like areas whose light modifying characteristics are changed by application of electrical energization potentials. The panel is provided with respective sets of row and column electrodes for selective application of energization potentials to selected ones of the dot-like areas to form a desired image.