Abstract: A multi-purpose register formed of various cells of a customized integrated circuit gate array chip having input gate cells, multiplexor cells, flip-flop cells and output gate cells. The flip-flop cells may be segmented into registers of different widths or may be employed as individual flip-flop cells depending upon the mode in which the register array is to be employed.

Abstract: A FIFO shift register (100) includes a parallel data in-port (PIN) to each of its cells (101-132) and a means for managing input to determine for each cell whether it is to receive data and, if so, whether through its conventional serial in-port (SIN) or through its parallel in-port. The input manager comprises a bidirectional shift register of input manager cells arranged in one-to-one correspondence with data cells. A one-bit validity indicator stored within a given input manager cell is logically combined with asserted PUSH and PULL signals to determine the source of data for the associated data cell and its immediate successor. This arrangement not only provides greater speed by minimizing bubble-through time, but permits the FIFO shift register to be clocked. This capacity for synchronous operation permits ready VLSI implementation with concomitant advantages in economy, reliability and speed.

Abstract: A power-saving serial data transfer circuit for outputting an inputted digital data signal through a plurality of serially connected shift register cells comprises n (=m.times.k) cells in k groups each containing m serially connected cells. A digital data signal is applied commonly to the first-stage cells of the groups and inputted in a time-wise segmented sequence to the cells by shift pulses with different phases. The inputted data signal is shifted through the cells within the same groups and is inputted to the last-stage cells of the groups. The inputted data signal is also outputted through a multiplexer connected to the last stage cells.

Abstract: A bidirectional barrel shift circuit includes an input switching circuit having a plurality of parallel input lines and the corresponding number of first and second signal line pairs associated to the respective input lines. This input switching circuit is operative to selectively connect each of the input lines to one line of the associated first and second signal line pair. There is also provided an output switching circuit connected to all the first and second singal lines and having output lines of the number corresponding to that of the input lines. This output switching circuit is operative to connect either the first signal lines or the second signal lines to the corresponding output lines. A barrel shift matrix is connected to the first and second signal lines and is controlled by a shift number controller so as to produce between the first and second signal lines a connection pattern sufficient for realizing a given shift number.

Abstract: A transversal filter with an analog shift register has a plurality of parallel inputs and a serial output at which a filtered signal appears. An object is to provide as simple as possible a realization of the n signal evaluators allocated to the n stages of the shift register. This is achieved by providing the n signal evaluators in a signal path proceeding from the input of the first stage over all n stages, and to evaluate according to evaluation factors b.sub.n through b.sub.1 which occur in the system functionH(z)=b.sub.o .multidot.(1+b.sub.1 z(1+b.sub.2 .multidot.z( . . . 1+b.sub.n .multidot.z)))describing the filtered signal, where z is the delay which the signal values respectively experience when traversing a stage of the shift register. The filter is employed as an analog filter in communication technology.

Abstract: An easily testable integrated logic circuit utilizes a plurality of flip-flops to form a feedback shift register. In some embodiments, means are provided for selectively forming the flip-flops into a feedback shift register and for selectively supplying either the flip-flop contents or a random signal as partial inputs to the combinational logic circuit. In other embodiments, the feedback shift register is coupled to the AND logic array outputs of a combinational circuit which also includes and OR logic array.

Abstract: An improved scannable latch circuit allows its output to be monitored during effectively 100% of the system clock cycle. The circuit further provides dual isolated outputs, one of which is used as a latch output and the other of which is used as a shift-register output. A computer system, in which the scannable latch circuit is used, in conjunction with combinatorial logic and error detection circuitry, may thus monitor the latch output, which is not loaded down by the shift register output, for error detection and other purposes without having to slow down the system operating speed. A preferred embodiment of the scannable latch circuit includes first, second, and third latch elements. When operating a latch circuit, the first latch element operates as the "master" and the second latch element operates as the "slave" of a master/slave latch circuit.

Abstract: A CMOS LSI or VLSI integrated circuit chip includes a shift register circuit that provides internal delay testing capability. The shift register circuit is disposed around the periphery of the chip and includes a large number of serially connected stages. One mode of operation allows a data signal to pass through the shift register circuit at a speed limited only by the propagation delays associated with the individual stages thereof. In this mode of operation, one net inversion is introduced into the data path and the output of a final stage of the shift register circuit is coupled to the input of a first stage of the shift register circuit, thereby creating a ring oscillator. The period of oscillation of this ring oscillator represents a measure of the average propagation delay times associated with the various circuit elements employed within the LSI or VLSI circuitry. Such delay measurements can readily be made at any level of packaging or system operation.

Abstract: An image analyzer system employs one or more neighborhood transformation stages. The stage operates to access groups of neighboring pixels in an image matrix, analyzes them and generates a transformation output as a result of the analysis. The stage includes a logic circuit which is programmable from a central controller. In the preferred embodiment, each pixel in the neighborhood is analyzed by the logic circuit and temporarily stored until other pixels in the group have been analyzed. The combination of analyzed pixel values form the basis for generating the transformation output for the stage. Preferably, the logic circuit is designed to perform both two dimensional and three dimensional image analyses.