Vapor Deposition Or Utilizing Vacuum Patents (Class 427/124)
  • Patent number: 6448644
    Abstract: A flip chip assembly, and methods of forming the same, including a single layer or multilayer substrate in which via holes serve as connections between a semiconductor chip and the substrate. The assembling steps comprise attaching an integrated circuit chip to a rigid or flexible dielectric substrate having a plurality of via holes for connecting respective traces on the substrate with respective input/output terminal pads of the integrated circuit chip. The via holes are aligned and placed on top of the pads so that the pads are totally or partially exposed through the opposite side of the substrate. Electrically conductive material is subsequently deposited in the via holes as well as on the surface of the pads to provide electrical connections between the integrated circuit chip and the traces of the dielectric circuitry.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: September 10, 2002
    Inventor: Charles W. C. Lin
  • Patent number: 6447849
    Abstract: A surface processing method for processing the surface of an insulating article in which an ion-implanted surface-modified layer is effectively formed on the article 2. In surface processing the article 2 of an insulating material, an electrically conductive thin metal film 50 is first formed on the article surface. A pulsed voltage containing a positive pulsed voltage and a negative pulsed voltage is applied to the article in a plasma containing ions to be implanted to implant ions in the article surface. This implants ions at right angles to the article surface to generate a surface-modified layer 51. There is no possibility of the article 2 being charged up due to application of a pulsed voltage.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: September 10, 2002
    Assignee: Sony Corporation
    Inventors: Seiichi Watanabe, Kenji Shinozaki, Minoru Kohno, Hiroyuki Mitsuhashi, Minehiro Tonosaki, Masato Kobayashi
  • Patent number: 6444264
    Abstract: A solvent composition for liquid delivery chemical vapor deposition of metal organic precursors, to form metal-containing films such as SrBi2Ta2O9 (SBT) films for memory devices. An SBT film may be formed using precursors such as Sr(thd)2(tetraglyme), Ta(OiPr)4(thd) and Bi(thd)3 which are dissolved in a solvent medium comprising one or more alkanes. Specific alkane solvent compositions may advantageously used for MOCVD of metal organic compound(s) such as &bgr;-diketonate compounds or complexes, compound(s) including alkoxide ligands, and compound(s) including alkyl and/or aryl groups at their outer (molecular) surface, or compound(s) including other ligand coordination species and specific metal constituents.
    Type: Grant
    Filed: January 30, 2001
    Date of Patent: September 3, 2002
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Frank S. Hintermaier, Thomas H. Baum
  • Patent number: 6444257
    Abstract: An evaporation system has fluorocarbon polymer-coated surfaces to permit easy removal of deposited metal. Evaporated lead-tin films will adhere strongly enough to a Teflon-coated shield so that the lead tin does not fall off during vacuum deposition but the bond between the lead-tin and the Teflon is still weak enough so that the lead-tin coating is easily peeled off, leaving the Teflon coating on the shield intact. The peeled lead-tin is substantially free of contamination so it can be reused, for example, in a subsequent deposition.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: September 3, 2002
    Assignee: International Business Machines Corporation
    Inventors: John C. Kutt, Craig J. Gilmond, Jeff R. Kelby, Pat N. McCabe, Jr.
  • Patent number: 6440495
    Abstract: The present invention provides a method of depositing ruthenium films on a substrate via liquid source chemical vapor deposition wherein the source material is liquid at room temperature and utilizing process conditions such that deposition of the ruthenium films occurs at a temperature in the kinetic-limited temperature regime. Also provided is a method of depositing a thin ruthenium film on a substrate by liquid source chemical vapor deposition using bis-(ethylcyclopentadienyl) ruthenium by vaporizing the bis-(ethylcyclopentadienyl) ruthenium at a vaporization temperature of about 100-300° C. to form a CVD source material gas, providing an oxygen source reactant gas and forming a thin ruthenium film on a substrate in a reaction chamber using the CVD source material gas and the oxygen source reactant gas at a substrate temperature of about 100-500° C.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: August 27, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Christopher P. Wade, Elaine Pao, Yaxin Wang, Jun Zhao
  • Patent number: 6436203
    Abstract: The present invention provides a CVD apparatus and a CVD method for use in forming an Al/Cu multilayered film. The Al/Cu multilayered film is formed in the CVD apparatus comprising a chamber for placing a semiconductor wafer W, a susceptor for mounting the semiconductor wafer W thereon, an Al raw material supply system for introducing a gasified Al raw material into the chamber and a Cu raw material supply system for introducing a gasified Cu raw material into the chamber. The Al/Cu multilayered film is formed by repeating a series of steps consisting of introducing the Al raw material gas into the chamber, depositing the Al film on the semiconductor wafer W by a CVD method, followed by generating a plasma in the chamber in which the Cu raw material gas has been introduced and depositing the Cu film on the semiconductor wafer W by a CVD method. The Al/Cu multilayered film thus obtained is subjected to a heating treatment (annealing), thereby forming a desired Al/Cu multilayered film.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: August 20, 2002
    Assignee: Tokyo Electron Limited
    Inventors: Takeshi Kaizuka, Takashi Horiuchi, Masami Mizukami, Takashi Mochizuki, Yumiko Kawano, Hideaki Yamasaki
  • Patent number: 6432819
    Abstract: The present invention generally provides a method and apparatus for forming a doped layer on a substrate to improve uniformity of subsequent deposition thereover. Preferably, the layer is deposited by a sputtering process, such as physical vapor deposition (PVD) or Ionized Metal Plasma (IMP) PVD, using a doped target of conductive material. Preferably, the conductive material, such as copper, is alloyed with a dopant, such as phosphorus, boron, indium, tin, beryllium, or combinations thereof, to improve deposition uniformity of the doped layer over the substrate surface and to reduce oxidation of the conductive material. It is believed that the addition of a dopant, such as phosphorus, stabilizes the conductive material surface, such as a copper surface, and lessens the surface diffusivity of the conductive material.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: August 13, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Vikram Pavate, Murali Narasimhan
  • Patent number: 6413576
    Abstract: Methods for protecting the surface of an uninsulated portion of a copper circuit from environmental contamination detrimental to joining the surface to another metal surface, said method comprising the step of coating the surface with a layer of a ceramic material having a thickness that is suitable for soldering without fluxing and that is sufficiently frangible when the surfaces are being joined to obtain metal-to-metal contact between the surfaces. Coated electronic packages including semiconductor wafers are also disclosed.
    Type: Grant
    Filed: October 5, 1999
    Date of Patent: July 2, 2002
    Assignee: Kulicke & Soffa Investments, Inc.
    Inventors: Timothy W. Ellis, Nikhil Murdeshwar, Mark A. Eshelman, Christian Rheault
  • Patent number: 6413860
    Abstract: A plasma enhanced chemical vapor deposition (PECVD) method for depositing high quality conformal tantalum (Ta) films from inorganic tantalum pentahalide (TaX5) precursors is described. The inorganic tantalum halide precursors are tantalum pentafluoride (TaF5), tantalum pentachloride (TaCl5) and tantalum pentabromide (TaBr5). A TaX5 vapor is delivered into a heated chamber. The vapor is combined with a process gas to deposit a Ta film on a substrate that is heated to 300° C.-500° C. The deposited Ta film is useful for integrated circuits containing copper films, especially in small high aspect ratio features. The high conformality of these films is superior to films deposited by PVD.
    Type: Grant
    Filed: April 27, 1999
    Date of Patent: July 2, 2002
    Assignee: Tokyo Electron Limited
    Inventors: John J. Hautala, Johannes F. M. Westendorp
  • Patent number: 6413456
    Abstract: In a method for manufacturing electronic parts by laminating metal thin films and insulating thin films on a support, a mold releasing agent is applied to the support before the start of lamination. Alternatively, the mold releasing agent is applied to the surface of the laminate during the lamination step, and then lamination is resumed. Therefore, the laminate can be prevented from cracking when the laminate is separated from the support or divided into plural pieces in the lamination direction. Thus, the reliability and productivity of electronic parts improve.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: July 2, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuyoshi Honda, Noriyasu Echigo, Masaru Odagiri, Nobuki Sunagare
  • Patent number: 6410432
    Abstract: A chemical vapor deposition (CVD) method for depositing high quality conformal tantalum/tantalum nitride (Ta/TaNx) bilayer films from inorganic tantalum pentahalide (TaX5) precursors and nitrogen is described. The inorganic tantalum halide precursors are tantalum pentafluoride (TaF5), tantalum pentachloride (TaCl5) and tantalum pentabromide (TaBr5). A TaX5 vapor is delivered into a heated reaction chamber. The vapor is combined with a process gas to deposit a Ta film and a process gas containing nitrogen to deposit a TaNx film on a substrate that is heated to 300° C.-500° C. The deposited Ta/TaNx bilayer film is useful for integrated circuits containing copper films, especially in small high aspect ratio features. The high conformality of these films is superior to films deposited by PVD.
    Type: Grant
    Filed: April 27, 1999
    Date of Patent: June 25, 2002
    Assignee: Tokyo Electron Limited
    Inventors: John J. Hautala, Johannes F. M. Westendorp
  • Patent number: 6383573
    Abstract: A process is provided for producing coated synthetic bodies during which, before the coating, the surface to be coated is subjected to a pretreatment in an excited gas atmosphere. The surface is then coated. The gas atmosphere is predominantly formed of a noble gas and nitrogen and/or hydrogen, and the ionic energy in the gas atmosphere and in the are of the surface to be coated is not more than 50 eV. The ionic energy is selected to be not more than 20 eV, preferable not more than 10 eV. The gas atmosphere is excited by means of a plasma discharge or by means of UV radiation.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: May 7, 2002
    Assignee: Unaxis Balzers Aktiengesellschaft
    Inventors: Eugen Beck, Jürgen Ramm, Heinrich Zimmermann
  • Patent number: 6383555
    Abstract: A substrate is located within a deposition chamber, the substrate defining a substrate plane. A liquid precursor is misted by ultrasonic or venturi apparatus, to produce a colloidal mist. The mist is generated, allowed to settle in a buffer chamber, filtered through a system up to 0.01 micron, and flowed into the deposition chamber between the substrate and barrier plate to deposit a liquid layer on the substrate. The liquid is dried to form a thin film of solid material on the substrate, which is then incorporated into an electrical component of an integrated circuit.
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: May 7, 2002
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinichiro Hayashi, Larry D. McMillan, Carlos A. Paz de Araujo
  • Patent number: 6383669
    Abstract: Zirconium precursors for use in depositing thin films of or containing zirconium oxide using an MOCVD technique have the following general formula: Zrx(OR)yL, wherein R is an alkyl group; L is a &bgr;-diketonate group; x=1 or 2; y=2, 4 or 6; and z=1 or 2.
    Type: Grant
    Filed: December 1, 1999
    Date of Patent: May 7, 2002
    Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: Timothy J Leedham, Anthony C Jones, Michael J Crosbie, Dennis J Williams, Peter J Wright, Penelope A Lane
  • Patent number: 6372364
    Abstract: A thin film product having a nanostructured surface, a laminate product including the thin film and a temporary substrate opposite the nanostructured surface, a laminate product including the thin film and a final substrate attached to the nanostructured surface and a method of producing the thin film products. The thin film is particularly useful in the electronics industry for the production of integrated circuits, printed circuit boards and EMF shielding. The nanostructured surface includes surface features that are mostly smaller than one micron, while the dense portion of the thin film is between 10-1000 nm. The thin film is produced by coating a temporary substrate (such as aluminum foil) with a coating material (such as copper) using any process. One such method is concentrated heat deposition or a combustion, chemical vapor deposition process.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: April 16, 2002
    Assignee: MicroCoating Technologies, Inc.
    Inventors: Andrew T. Hunt, Henry A. Luten, III
  • Publication number: 20020028383
    Abstract: A member having a lithium metal thin film is provided, which is extremely thin, uniform, and not degraded by air. The member includes a substrate and a thin lithium metal film formed on the substrate by a vapor deposition method. The thin film typically has a thickness of 0.1 &mgr;m to 20 &mgr;m. The substrate is typically made of a metal, an alloy, a metal oxide, or carbon. The substrate typically has a thickness of 1 &mgr;m to 100 &mgr;m. The member is used as an electrode member for a lithium cell.
    Type: Application
    Filed: June 18, 2001
    Publication date: March 7, 2002
    Inventors: Hirokazu Kugai, Nobuhiro Ota, Shosaku Yamanaka
  • Patent number: 6352743
    Abstract: Methods of protecting from atmospheric contaminants, or removing atmospheric contaminants from, the bonding surfaces of copper semiconductor bond pads by coating a bond pad with a layer of a ceramic material having a thickness that is suitable for soldering without fluxing and that is sufficiently frangible during ball or wedge wire bonding to obtain metal-to-metal contact between the bonding surfaces and the wires bonded thereto. Coated semiconductor wafers are also disclosed.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: March 5, 2002
    Assignee: Kulicke & Soffa Investments, Inc.
    Inventors: Timothy W. Ellis, Nikhil Murdeshwar, Mark A. Eshelman
  • Patent number: 6344281
    Abstract: IC fabrication employs the deposition of aluminum as a metallization layer. Frequently, the aluminum is doped with copper in small amounts to improve electric properties. Low temperature deposition of these layers is preferred to ensure the proper microstructure and surface roughness. Low temperature deposition (below about 300° C.) results in the formation of copper precipitates which can be difficult to remove. Annealing the layer formed, either prior to, or after formation of capping layers and additional layers thereon, drives the copper precipitate back into solution, permitting small dimension fabrication.
    Type: Grant
    Filed: October 18, 1999
    Date of Patent: February 5, 2002
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mark Smith, Ivan Ivanov, Frederick Eisenmann
  • Patent number: 6340497
    Abstract: Removing the electrical field from the internal volume of high-voltage structures; e.g., bushings, connectors, capacitors, and cables. The electrical field is removed from inherently weak regions of the interconnect, such as between the center conductor and the solid dielectric, and places it in the primary insulation. This is accomplished by providing a conductive surface on the inside surface of the principal solid dielectric insulator surrounding the center conductor and connects the center conductor to this conductive surface. The advantage of removing the electric fields from the weaker dielectric region to a stronger area improves reliability, increases component life and operating levels, reduces noise and losses, and allows for a smaller compact design. This electric field control approach is currently possible on many existing products at a modest cost. Several techniques are available to provide the level of electric field control needed.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: January 22, 2002
    Assignee: The Regents of the University of California
    Inventors: Michael J. Wilson, David A. Goerz
  • Patent number: 6337109
    Abstract: A method of producing a crystalline silicon film having superior crystalline properties is characterized by a method of adding catalytic metal for accelerating crystallization of the amorphous silicon film. The catalytic element is adsorbed on the surface of the amorphous silicon film by using a vapor or a gas, so that a low temperature short time crystallization is made possible by using the catalytic metal at heat crystallization. Especially, by controlling partial pressures, when adsorption state is made into monomolecular layer adsorption with covering rate 1, superior uniform crystalline silicon film can be obtained.
    Type: Grant
    Filed: August 5, 1996
    Date of Patent: January 8, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Patent number: 6331483
    Abstract: A method of forming a tungsten film is capable of forming a tungsten film having a low resistivity. The method of forming a tungsten film (50) on a surface of a workpiece by a vacuum processing system (2) comprises, in sequential steps: a seed crystal growing process for growing tungsten seed crystal grains (48) on the surface of the workpiece in an atmosphere of a film forming gas containing tungsten atoms; a boron-exposure process for exposing the workpiece to an atmosphere of a boron-containing gas for a short time; and a tungsten film forming process for forming a tungsten film by making the tungsten seed crystal grains grow in an atmosphere of a gas containing a film forming gas containing tungsten atoms, and a hydrogen-diluted boron-containing gas. The tungsten film has a low resistivity.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: December 18, 2001
    Assignee: Tokyo Electron Limited
    Inventors: Hotaka Ishizuka, Mitsuhiro Tachibana
  • Publication number: 20010051209
    Abstract: This invention consists of a coating applied to the metal surface which reduces the field emission levels of the surface. This coating could also decrease the secondary electron coefficient of the surface. The preferred embodiment described below is a hybrid coating consisting of two layers. However, a single-layer coating may also be used so long as it decreases field emission. Likewise, any number of coating layers may be used, so long as the resultant coating reduces field emission. The coating may also alter the properties of the interface between the metal surface and any macroparticle debris, in order to reduce field emission levels, but this is not essential, so long as the field emission from the surface is reduced. The invention is a coating which is not harmful to dc and rf vacuum system components, as for example, coatings which contain halogen atoms, such as CaF [J. N. Smith, Jr., J. Appl. Phys. 59, 283 (1986)].
    Type: Application
    Filed: October 11, 1996
    Publication date: December 13, 2001
    Inventors: RICHARD SILBERGLITT, WILLIAM PETER
  • Patent number: 6328871
    Abstract: The invention generally provides a method for preparing a surface for electrochemical deposition comprising forming a high conductance barrier layer on the surface and depositing a seed layer over the high conductance barrier layer. Another aspect of the invention provides a method for filling a structure on a substrate, comprising depositing a high conductance barrier layer on one or more surfaces of the structure, depositing a seed layer over the barrier layer, and electrochemically depositing a metal to fill the structure.
    Type: Grant
    Filed: August 16, 1999
    Date of Patent: December 11, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Peijun Ding, Tony Chiang, Tse-Yong Yao, Barry Chin
  • Patent number: 6319554
    Abstract: The present invention relates generally to a CVD (Chemical Vapor Deposition) process where at least one source metal, such as, nickel (Ni) or alloys thereof, for example, Ni/Cu, Ni/Co, are deposited on metal surfaces which are capable of receiving the source metal, such as, refractory metal, for example, molybdenum, tungsten or alloys thereof, using at least one gaseous Iodide source, such as, an iodic fluid, for example, hydriodic acid gas. The source metal is securely held in place by at least one high strength inert material.
    Type: Grant
    Filed: June 10, 1999
    Date of Patent: November 20, 2001
    Assignee: International Business Machine Corporation
    Inventors: Govindarajan Natarajan, Robert W. Pasco
  • Patent number: 6302318
    Abstract: A method for applying a wear coating on a surface of a substrate is described. A foil of the wear coating is first attached to the substrate surface, and then fused to the surface, e.g., by brazing. The wear coating may be formed from a carbide-type material. The substrate is very often a superalloy material, e.g., a component of a turbine engine. A method for repairing a worn or damaged wear coating applied over a substrate is also described, along with related articles of manufacture.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: October 16, 2001
    Assignee: General Electric Company
    Inventors: Wayne Charles Hasz, Anthony Mark Thompson, Marcus Preston Borom
  • Patent number: 6300245
    Abstract: An apparatus and method for performing material deposition on semiconductor devices. The apparatus provides an enclosure for defining a chamber. The chamber includes a metallic portion such as a conductor coil powered by a voltage generator. A gas, having a suspension of particles for treating the semiconductor devices, is introduced into the chamber and the powered conductor coil converts the gas to inductively coupled plasma and vaporizes the particles. The particles can then be deposited on the semiconductor devices.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: October 9, 2001
    Assignee: Ball Semiconductor, Inc.
    Inventors: Ivan Herman Murzin, Ram K. Ramamurthi
  • Patent number: 6284316
    Abstract: A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second precursor with the seed layer by CVD. The titanium layer is used to form contacts to active areas of substrate and for the formation of interlevel vias.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: September 4, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Singh Sandhu, Donald L. Westmoreland
  • Patent number: 6274293
    Abstract: A method of manufacturing a flexible metallic photonic band gap structure operable in the infrared region, comprises the steps of spinning on a first layer of dielectric on a GaAs substrate, imidizing this first layer of dielectric, forming a first metal pattern on this first layer of dielectric, spinning on and imidizing a second layer of dielectric, and then removing the GaAs substrate. This method results in a flexible metallic photonic band gap structure operable with various filter characteristics in the infrared region. This method may be used to construct multi-layer flexible metallic photonic band gap structures. Metal grid defects and dielectric separation layer thicknesses are adjusted to control filter parameters.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: August 14, 2001
    Assignee: Iowa State University Research Foundation
    Inventors: Sandhya Gupta, Gary L. Tuttle, Mihail Sigalas, Jonathan S. McCalmont, Kai-Ming Ho
  • Patent number: 6271129
    Abstract: A method for forming a refractory metal layer that features two-stage nucleation prior to bulk deposition of the same. The method includes placing a substrate in a deposition zone, flowing, into the deposition zone during a first deposition stage, a silicon source, such as a silane gas, and a tungsten source, such as tungsten-hexafluoride gas, so as to obtain a predetermined ratio of the two gases therein. During a second deposition stage, subsequent to the first deposition stage, the ratio of the two gases is varied. Specifically, in the first deposition stage there is a greater quantity of silane gas than tungsten-hexafluoride gas. In the second deposition stage there may be a greater quantity of tungsten-hexafluoride than silane.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: August 7, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Steve Ghanayem, Maitreyee Mahajani
  • Patent number: 6260266
    Abstract: A silicon substrate on which a silicon dioxide film having a groove is formed is placed on a sample stage disposed in a vacuum chamber. Subsequently, a titanium film and a tungsten film are deposited sequentially on the silicon dioxide film. The surface of the tungsten film is nitrided by using a plasma under the pressure maintained at 10 Pa or higher inside the vacuum chamber, so as to form a tungsten nitride film. After a copper film is deposited on the tungsten nitride film, the portions of the titanium film, tungsten film, tungsten nitride film, and copper film located outside the groove are removed, thus forming a buried interconnecting wire made of copper.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: July 17, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Tokuhiko Tamaki
  • Patent number: 6258710
    Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is deposited by chemical vapor deposition, or by physical vapor deposition in a layer less than about 800 angstroms.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: July 10, 2001
    Assignee: International Business Machines Corporation
    Inventors: Hazara S. Rathore, Hormazdyar M. Dalal, Paul S. McLaughlin, Du B. Nguyen, Richard G. Smith, Alexander J. Swinton, Richard A. Wachnik
  • Patent number: 6254925
    Abstract: The present invention discloses at least one source metal that is embedded in at least one inert material to form a stand-alone structure and process thereof. It is preferred that the source metal is nickel or alloy thereof, and the inert material is at least one ceramic.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: July 3, 2001
    Assignee: International Business Machines Corporation
    Inventors: Govindarajan Natarajan, John U. Knickerbocker, Robert A. Rita
  • Patent number: 6251334
    Abstract: The effects of interfacial transition between organic and inorganic layers of a multilayer construction are ameliorated by incorporating an inorganic component within the matrix of the organic layer. In a first aspect, a construction having adjacent organic and inorganic layers is fabricated by depositing a curable polymer, softening the polymer, and integrating an inorganic material therewith. The polymer is then cured to immobilize the integrated deposition material, and the desired inorganic layer is applied over the deposited inorganic material (and any exposed portions of the polymer). In a second aspect, a graded structure is built up on a substrate in successive deposition steps. Both polymer precursors and an inorganic filler material are deposited in stages, with each stage containing a desired ratio of polymer to filler.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: June 26, 2001
    Assignee: Presstek, Inc.
    Inventor: Thomas E. Lewis
  • Patent number: 6238729
    Abstract: Apparatuses, systems, and methods are disclosed for providing optical communications. Bragg grating used in the optical components and systems of the present invention are produced by selectively hydrogenating one or more selected sections of an optical waveguide in general, and particularly optical fiber. Selective hydrogenation can be performed by selectively establishing local conditions in a first environment conducive to introducing greater quantities of hydrogen into selected sections than into non-selected sections, which are maintained in a second environment. The extent of selective hydrogenation and the hydrogen concentration difference between selected and non-selected section of the waveguide is a function of the temperature, pressure, and time of exposure established in the first and second environments.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: May 29, 2001
    Assignee: Acme Grating Ventures, LLC
    Inventors: Thomas J. Cullen, Timothy E. Hammon, John M. Stockhausen
  • Patent number: 6235112
    Abstract: An apparatus for forming a thin film such as a silicon oxide film on a surface of a substrate such as a semiconductor substrate includes: a reaction chamber having an interior where the substrate is placed when in use; a liquid reaction material supplier for supplying a given amount of liquid reaction material such as TEOS for forming a thin film on the substrate; and a mist-forming device for forming mist of the liquid reaction material and spraying the liquid reaction material onto a surface of the substrate for forming a thin film thereon. The mist-forming device is disposed upstream of the reaction chamber and downstream of the liquid reaction material supplier. Neither of the mist-forming device nor the liquid reaction material supplier includes a heating device for heating the liquid reaction material.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: May 22, 2001
    Assignee: ASM Japan K.K.
    Inventor: Kiyoshi Satoh
  • Patent number: 6228228
    Abstract: A display as for images and/or information comprises a plurality of light-emitting fibers disposed in side-by-side arrangement to define a viewing surface. Each light-emitting fiber includes a plurality of light-emitting elements disposed along its length, each having two electrodes between which are applied electrical signals to cause the light-emitting element to emit light to display a pixel or sub-pixel of the image and/or information. The light-emitting fiber includes an electrical conductor disposed along its length to serve as a first electrode, a layer of light-emissive material disposed thereon, and a plurality of electrical contacts disposed on the light-emissive material to serve as the second electrodes of the light-emitting elements, and are formed in a continuous process wherein a transparent fiber passes through a plurality of processing chambers for receiving the electrical conductor, the light-emissive layer and the plurality of electrical contacts thereon.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: May 8, 2001
    Assignee: Sarnoff Corporation
    Inventors: Bawa Singh, William Ronald Roach, William Chiang
  • Patent number: 6224942
    Abstract: The invention includes methods of forming aluminum containing lines having titanium nitride containing layers thereon, and preferably by physical vapor deposition. In one aspect, a first layer including at least one of elemental aluminum or an aluminum alloy is formed over a substrate. A second layer including an alloy of titanium and the aluminum from the first layer is formed. The alloy has a higher melting point than that of the first layer. A third layer including titanium nitride is formed over the second layer. The first, second and third layers are formed into a conductive line. In one aspect, a method of forming an aluminum containing line having a titanium nitride containing layer thereon includes physical vapor depositing a first layer having at least one of elemental aluminum or an aluminum alloy over a substrate.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: May 1, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Shane P. Leiphart
  • Patent number: 6221218
    Abstract: An inductive write head includes a first pole and a second pole that form a yoke having a write gap between the first pole and second pole. The second pole is formed of a particular Co100-a-bZRaCRb compound. More specifically, the second pole is formed where “a” is in the range of about 2 atomic percent to about 18 atomic percent, and “b” is in the range of about 0.5 atomic percent to about 6 atomic percent. The magnetic write element also includes a conductive coil which lies between the first pole and the second pole. The inductive write head also includes a first yoke pedestal attached to the first pole, and a second yoke pedestal attached to the second pole, with the write gap formed therebetween. Further, the first yoke pedestal has a pedestal width that defines the write element trackwidth and that is smaller than the pedestal width of the second yoke pedestal.
    Type: Grant
    Filed: February 17, 1999
    Date of Patent: April 24, 2001
    Assignee: Read-Rite Corporation
    Inventors: Zhupei Shi, Chun He, Syed Hossain, Mark S. Miller
  • Patent number: 6204174
    Abstract: A method and apparatus to control the deposition rate of a refractory metal film in a semiconductor fabrication process by controlling a quantity of ethylene present. The method includes placing a substrate in a deposition zone, of a semiconductor process chamber, flowing, into the deposition zone, a process gas including a refractory metal source, an inert carrier gas, and a hydrocarbon. Typically, the refractory metal source is tungsten hexafluoride, WF6, and the inert gas is argon, Ar. The ethylene may be premixed with either the argon or the tungsten hexafluoride to form a homogenous mixture. However, an in situ mixing apparatus may also be employed.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: March 20, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Alexander D. Glew, Andrew D. Johnson, Ravi Rajagopalan, Steve Ghanayem
  • Patent number: 6203931
    Abstract: The present invention provides a lead frame material and a process for manufacturing a lead frame material. The process includes forming an intermediate layer on a lead frame substrate by vacuum deposition and forming a top protective layer on the intermediate layer by vacuum deposition. By using vacuum deposition, the coating material can be selected from a wider variety of materials; thus, coatings with novel compositions can be formed. The intermediate layer can be Ni, Ag, W, Zn, Cr, Mo, Cu, Sn, Al, Ta, Co, Nb, or alloys thereof, and the top protective layer can be Pt, Ir, Re, Ru, Rh, Pd, Au, Ag, or alloys thereof.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: March 20, 2001
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Hsun Chu, Shyi-Yi Chen, Jui-Fen Pai
  • Patent number: 6190454
    Abstract: A cartridge for use with a printing apparatus of the type typically employed for digital printing in which a painting material is deposited in metered amounts on a print medium comprises a housing containing a drive wheel, a first idler disposed in a paint reservoir, a wire disposed around the wheel and the idler, and an air nozzle having at least one nozzle orifice therein for directing a jet of air toward said wire. As the drive wheel is rotated, as with an external drive mechanism, paint contained within the paint reservoir coats the wire and is drawn by the wire in the path of the air jet. The air jet removes at least a portion of the paint from the wire and deposits the paint onto a print medium. By employing a plurality of such cartridges into a single print head, each containing a different color of paint, a color image can be painted onto a print medium.
    Type: Grant
    Filed: November 4, 1998
    Date of Patent: February 20, 2001
    Inventor: Dean Robert Gary Anderson
  • Patent number: 6174563
    Abstract: A method for forming metal thin films for wiring wherein the formation of the metal films by chemical vapor deposition technique is carried out in two steps, with the deposition temperature of the second step being set to be higher than the deposition temperature of the first step, whereby a via hole or a wiring groove can be embedded without the formation of voids. As a result a highly reliable wiring can be achieved even on a fine LSI.
    Type: Grant
    Filed: July 6, 1998
    Date of Patent: January 16, 2001
    Assignee: NEC Corporation
    Inventor: Kazumi Sugai
  • Patent number: 6165567
    Abstract: A film is formed over a substrate using a physical vapor deposition method. When using ionized metal plasma physical vapor deposition, the deposition chamber configuration or operating parameters are adjusted to achieve the desired film characteristics. If the film is to be substantially uniform in thickness across a substrate, the deposition species density is made higher at locations away from the center of the substrate.
    Type: Grant
    Filed: April 12, 1999
    Date of Patent: December 26, 2000
    Assignee: Motorola, Inc.
    Inventors: Peter Lowell George Ventzek, Daniel G. Coronell, Michael J. Hartig, John C. Arnold
  • Patent number: 6159543
    Abstract: A process for the manufacture of wires with a brass surface and a predefined zinc content for application in wire electroerosion. Wire (32) made of copper or brass is passed through heated treatment chamber (14) filled with a zinc vapor, wherein the zinc in gas phase diffuses in wire (32). The concentration of zinc in gas phase and the temperature (T.sub.D) of wire (32) in treatment chamber (14) are regulated in such a way that the zinc content of the brass phase forming on the surface of the wire suitably corresponds to the predefined zinc content.
    Type: Grant
    Filed: December 9, 1996
    Date of Patent: December 12, 2000
    Assignee: Charmilles Technologies SA
    Inventor: Jean Paul Briffod
  • Patent number: 6153270
    Abstract: A process of applying an inorganic coating to an electrically conducting body, in particular a metallic workpiece, is characterized with respect to a precisely controllable temperature variation with short temperature changes in an economical and energy-saving operation in that the body first undergoes a preparation. Thereafter, if need be, the body is degreased and/or chemically pretreated and/or blasted. Subsequently, a coating medium is applied to at least the surface region of the body being coated. Then, at least the surface region of the body being coated is heated by induction to a reaction temperature before and/or while and/or after applying the coating medium. Finally, the coating medium is fully reacted to a coating, whereupon the body undergoes a cooling.
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: November 28, 2000
    Assignee: Ewald Dorken AG
    Inventors: Horst Russmann, Thomas Kruse, Hans-Detlef Hinz
  • Patent number: 6153063
    Abstract: In a phase-change recording medium, a recording medium is provided with a barrier layer including Ge--N, Ge--N--O between a recording layer and a dielectric protective layer in order to prevent a chemical reaction and an atom diffusion between the recording layer and the dielectric protective layer. A barrier material can be also applied to the protective layer itself. Thereby, it is possible to considerably suppress a reduction of a reflectivity and a reduction of a signal amplitude due to the repeat of recording and erasing, such reductions being observed in a conventional phase-change optical information recording medium, and thereby the number of overwriting times can be increased.
    Type: Grant
    Filed: July 29, 1998
    Date of Patent: November 28, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Noboru Yamada, Mayumi Otoba, Kenichi Nagata, Katsumi Kawahara
  • Patent number: 6143362
    Abstract: A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second precursor with the seed layer by CVD. The titanium layer is used to form contacts to active areas of substrate and for the formation of interlevel vias.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: November 7, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Singh Sandhu, Donald L. Westmoreland
  • Patent number: 6139905
    Abstract: The present invention provides a method and apparatus for forming an interconnect with application in small feature sizes (such as quarter micron widths) having high aspect ratios. Generally, the present invention provides a method and apparatus for depositing a wetting layer for subsequent physical vapor deposition to fill the interconnect. In one aspect of the invention, the wetting layer is a metal layer deposited using either CVD techniques or electroplating, such as CVD aluminum (Al). The wetting layer is nucleated using an ultra-thin layer, denoted as .di-elect cons. layer, as a nucleation layer. The .di-elect cons. layer is preferably comprised of a material such as Ti, TiN, Al, Ti/TiN, Ta, TaN, Cu, a flush of TDMAT or the like. The .di-elect cons. layer may be deposited using PVD or CVD techniques, preferably PVD techniques to improve film quality and orientation within the feature. Contrary to conventional wisdom, the .di-elect cons.
    Type: Grant
    Filed: April 11, 1997
    Date of Patent: October 31, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Liang-Yuh Chen, Mehul Naik, Ted Guo, Roderick Craig Mosely
  • Patent number: 6126988
    Abstract: A method for forming a planar aluminum layer in a flat panel display structure. In one embodiment, the present invention creates a flat panel display structure having a raised black matrix defining wells within the matrix. The present embodiment then deposits a non-conformal layer of acrylic-containing aluminizing lacquer over a layer of phosphors residing within the wells of the black matrix. In so doing, the lacquer layer forms a substantially planar surface on top of the phosphors. The present invention then deposits a layer of catalyst material over the layer of lacquer so that the aluminizing lacquer can be burned off completely and cleanly at a relatively low temperature. The catalytic layer conforms to the planar surface of the lacquer layer. The present invention then deposits an aluminum layer over the catalytic layer. The aluminum layer, in turn, conforms to the planar surface of the catalytic layer. Finally, the present invention bakes off the non-conformal lacquer layer.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: October 3, 2000
    Assignee: Candescent Technologies Corporation
    Inventor: Paul M. Drumm
  • Patent number: 6117771
    Abstract: A method and apparatus are provided for forming cobalt on a silicon substrate containing native silicon oxide on the surface thereof wherein a modified vapor sputtering device is used. The vapor sputtering device is modified by providing an electrical circuit to ground whereby the wafer disposed in the device is electrically connected to the ground circuit. The ground circuit preferably contains a resistor therein to control wafer voltage and current flow from the wafer to ground. It has been found that providing a current flow from the wafer to ground and particularly in a ground circuit containing a resistor, provides an in-situ simultaneous cleaning of native oxide on the silicon surface and deposition of cobalt on cleaned silicon. The deposited cobalt containing substrate may then be readily annealed to form cobalt silicide evenly and uniformly across the desired regions of the wafer surface.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: September 12, 2000
    Assignee: International Business Machines Corporation
    Inventors: William J. Murphy, Prabhat Tiwari