Including Control Feature Responsive To A Test Or Measurement Patents (Class 430/30)
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Patent number: 8124300Abstract: A method of correcting a lithographic mask is disclosed. The method can include detecting a location of the mask that corresponds to a wafer location having a structure that is printed with a larger than desired dimension and reducing a thickness of at least a portion of a mask feature corresponding to the wafer structure to locally increase transmissivity of the mask feature.Type: GrantFiled: November 30, 2004Date of Patent: February 28, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Bhanwar Singh, Luigi Capodieci
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Patent number: 8119313Abstract: A method for manufacturing a semiconductor device, includes: supplying a liquid resist containing a water-repellent additive to a surface of a rotating semiconductor wafer fixed to a rotary support to form a resist film to a design thickness on the surface of the semiconductor wafer; spin drying the resist film; bringing a liquid into contact with the resist film and exposing the resist film through the liquid after the spin drying; developing the resist film to form a resist pattern; and performing processing on the semiconductor wafer. A condition for adjusting contact angle between the resist film surface and the liquid is controlled so that the contact angle assumes a desired value, the condition including at least one selected from the group consisting of spin drying time for the resist film, resist temperature during the supplying, pressure of an atmosphere above the semiconductor wafer surface, and humidity of the atmosphere above the semiconductor wafer surface.Type: GrantFiled: January 29, 2010Date of Patent: February 21, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Katsutoshi Kobayashi, Daizo Muto, Koutarou Sho, Tsukasa Azuma
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Patent number: 8119312Abstract: In a manufacturing method for divisionally exposing a wafer, a focus correction processing is performed after a shot is moved to a position where the focus correction processing for all foci is enabled when the shot is at a wafer outer periphery, and a portion overlapped with an adjacent exposure area is shielded from light by a reticle blind to expose only an opening area unshielded by the reticle blind.Type: GrantFiled: February 5, 2010Date of Patent: February 21, 2012Assignee: Seiko Instruments Inc.Inventor: Michihiro Murata
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Patent number: 8119310Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.Type: GrantFiled: August 31, 2010Date of Patent: February 21, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Chung Lu, Yi-Kan Cheng, Hsiao-Shu Chao, Ke-Ying Su, Cheng-Hung Yeh, Dian-Hau Chen, Ru-Gun Liu, Wen-Chun Huang
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Publication number: 20120040280Abstract: A mechanism is provided for simultaneous optical proximity correction (OPC) and decomposition for double exposure lithography. The mechanism begins with two masks that are equal to each other and to the target. The mechanism simultaneously optimizes both masks to obtain a wafer image that both matches the target and is robust to process variations. The mechanism develops a lithographic cost function that optimizes for contour fidelity as well as robustness to variation. The mechanism minimizes the cost function using gradient descent. The gradient descent works on analytically evaluating the derivative of the cost function with respect to mask movement for both masks. It then moves the masks by a fraction of the derivative.Type: ApplicationFiled: August 13, 2010Publication date: February 16, 2012Applicant: International Business Machines CorporationInventors: Kanak B. Agarwal, Shayak Banerjee
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Patent number: 8112726Abstract: The present invention discloses a method of designing a set of two tiled masks, as well as, a mask including: a first tile, the first tile being transparent to a light, the first tile having a first characteristic linear dimension that is 15% or less of a wavelength of the light; a second tile, the second tile being transparent to the light, the second tile having a second characteristic linear dimension that is 15% or less of the wavelength of the light; and a third tile, the third tile being opaque to the light, the third tile having a third characteristic linear dimension that is 15% or less of the wavelength of the light.Type: GrantFiled: December 9, 2008Date of Patent: February 7, 2012Assignee: Intel CorporationInventors: Bin Hu, Vivek Singh, Yan Borodovsky
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Patent number: 8110325Abstract: A substrate treatment method including a first treatment process (S13 to S16) for exposing, heating, and developing a substrate on which a first resist is formed, thereby forming a first resist pattern, and a second treatment process (S17 to S20) for forming a second resist film on the substrate on which the first resist pattern is formed, exposing, heating, and developing the substrate on which the second resist film is formed, thereby forming a second resist pattern. Also, the substrate treatment method compensates a first treatment condition in a first treatment process (S22 to S25) based on a measured value of a line width of the second resist pattern and a second treatment condition in a second treatment process (S26 to S29) based on a measured value of a line width of the first resist pattern.Type: GrantFiled: February 8, 2011Date of Patent: February 7, 2012Assignee: Tokyo Electron LimitedInventors: Takafumi Niwa, Hiroshi Nakamura, Hideharu Kyouda
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Patent number: 8111398Abstract: According to an example, a first layer of a substrate comprises a plurality of gratings having a periodicity P. A second layer of the substrate comprises a plurality of gratings, overlapping with the first set of gratings, and having a periodicity of NP, where N is an integer greater than 2. A first set of gratings has a bias of +d and the second set of gratings has a bias of ?d. A beam of radiation is projected onto the gratings and the angle resolved spectrum of the reflected radiation detected. The overlay error is then calculated using the angle resolved spectrum of the reflected radiation.Type: GrantFiled: April 29, 2010Date of Patent: February 7, 2012Assignee: ASML Netherlands B.V.Inventors: Maurits Van der Schaar, Arie Jeffrey Den Boef, Everhardus Cornelis Mos
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Publication number: 20120028174Abstract: A method includes performing a lithography process on a wafer to form a patterned photo resist, and measuring the wafer to determine an overlay error of the patterned photo resist. A high/low specification is determined using the overlay error. An overlay process value setting is generated and compared with the high/low specification to determine whether the overlay process value setting is within a range defined by the high/low specification.Type: ApplicationFiled: July 27, 2010Publication date: February 2, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shin-Rung Lu, Chih Ming Hong, Yen-Di Tsen
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Publication number: 20120028173Abstract: Disclosed are printing methods, apparatus and systems for developing a latent image recorded on a surface, for example, a photoreceptor with developer material. According to an exemplary embodiment, the development method applies a development field voltage between a development station donor member and a development station transport member as a function of a humidity measurement associated with the developer material, the humidity measurement providing a surrogate tribo measurement of the developer material.Type: ApplicationFiled: July 27, 2010Publication date: February 2, 2012Applicant: XEROX CORPORATIONInventors: W. Bradford Willard, Kimberly Anne Stoll, David R. Stookey, Paul L. Jacobs, Robert W. Phelps, Jyothsna Ram
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Patent number: 8105737Abstract: A method of correcting patterns includes attaining a correcting amount distribution map using a photo mask, the photo mask including a transparent substrate having first and second surfaces opposite to each other and a mask pattern on the first surface, attaining a plurality of shadowing maps based on the correction amount distribution map, each of the shadowing maps including a unit section having a different plane area, and forming a plurality of shadowing regions with shadowing elements in the transparent substrate of the photo mask using respective shadowing maps.Type: GrantFiled: July 7, 2010Date of Patent: January 31, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: MyoungSoo Lee, Byunggook Kim
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Patent number: 8105738Abstract: Disclosed is a developing method that performs a developing for forming a second resist pattern after forming and exposing a resist film on a surface of a substrate on which a first resist pattern is formed. The method includes a first process for developing the substrate for a first time period t1 in the state where the substrate stops, and a second process for developing the substrate for a second time period while rotating the substrate. The time ratio of first time period and second time period is adjusted so that a critical dimension of the first resist pattern is equal to a first predetermined value, and a total time of first time period and second time period is adjusted so that a critical dimension of the second resist pattern is equal to a second predetermined value.Type: GrantFiled: April 28, 2011Date of Patent: January 31, 2012Assignee: Tokyo Electron LimitedInventor: Kousuke Yoshihara
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Patent number: 8107079Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.Type: GrantFiled: November 9, 2010Date of Patent: January 31, 2012Assignees: International Business Machines Corporation, Nanometrics IncorporatedInventors: Christopher P. Ausschnitt, Lewis A. Binns, Jaime D. Morillo, Nigel P. Smith
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Patent number: 8105757Abstract: Disclosed is a method of making a semiconductor device in which a main pattern is formed through a photolithography process over a low-density pattern area having a relatively small number of patterns to be formed in certain areas as compared to the other areas. According to the method at least one or more dummy patterns are formed over inactive areas, adjacent to active areas, where the main pattern is formed, and are spaced a predetermined distance from the sides of the main pattern. This method can improve the process margin and improve the uniformity of critical regions of patterns to thus improve the yield of a semiconductor device by making a low-density pattern area with the same pattern density as high-density or intermediate-density pattern areas by forming dummy patterns, which do not affect the semiconductor device, on the sides of a main pattern of the low-density pattern area according to a design rule.Type: GrantFiled: July 6, 2005Date of Patent: January 31, 2012Assignee: Hynix Semiconductor Inc.Inventor: Jae Seung Choi
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Patent number: 8105736Abstract: A method of performing overlay error correction includes forming a photoresist layer over a substrate and exposing a first set of apertures to incident radiation. The method also includes determining an overlay error associated with the first set of apertures and determining an overlay correction as a function of the determined overlay error. The method further includes exposing a data area and a second set of apertures. The data area and the second set of apertures are exposed based, in part, on the determined overlay correction. Moreover, the method includes verifying the determined overlay correction.Type: GrantFiled: March 13, 2008Date of Patent: January 31, 2012Assignee: Miradia Inc.Inventors: Xiao Yang, Yuxiang Wang, Ye Wang, Justin Payne, Wook Ji
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Patent number: 8102507Abstract: A lithographic apparatus, includes a support structure configured to hold a patterning device, the patterning device configured to impart a beam of radiation with a pattern in its cross-section; a substrate table configured to hold a substrate; a projection system configured to project the patterned beam onto a target portion of the substrate; a liquid supply system configured to provide liquid to a space between the projection system and the substrate table; a sensor configured to measure an exposure parameter using a measuring beam projected through the liquid; and a correction system configured to determine an offset based on a change of a physical property impacting a measurement made using the measuring beam to at least partly correct the measured exposure parameter.Type: GrantFiled: January 27, 2010Date of Patent: January 24, 2012Assignee: ASML Netherlands B.V.Inventors: Bob Streefkerk, Johannes Jacobus Matheus Baselmans, Sjoerd Nicolaas Lambertus Donders, Jeroen Johannes Sophia Mertens, Johannes Catharinus Hubertus Mulkens, Christiaan Alexander Hoogendam
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Patent number: 8103980Abstract: A beam dose computing method includes specifying a matrix of rows and columns of regions as divided from a surface area of a target object to include first, second and third regions of different sizes, the third regions being less in size than the first and second regions, determining first corrected doses of a charged particle beam for correcting fogging effects in the first regions, determining corrected size values for correcting pattern line width deviations occurring due to loading effects in the second regions, using said corrected size values in said second regions to create a map of base doses of the beam in respective ones of said second regions, using said corrected size values to prepare a map of proximity effect correction coefficients in respective ones of said second regions, using the maps to determine second corrected doses of said beam for correction of proximity effects in said third regions, and using the first and second corrected doses to determine an actual beam dose at each position onType: GrantFiled: September 24, 2009Date of Patent: January 24, 2012Assignee: NuFlare Technology, Inc.Inventors: Keiko Emi, Junichi Suzuki, Takayuki Abe, Tomohiro Iljima, Jun Yashima
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Position aligning apparatus, position aligning method, and semiconductor device manufacturing method
Patent number: 8092961Abstract: A position aligning apparatus performs position alignment of a pattern in a current process of a pattern exposure process by using a pattern formed before the current process. The position aligning apparatus includes: a correction calculating section configured to calculate a correction value set of a current lot about each of misalignments in scale and rotation of a pattern in a chip in the current process based on a correction value set in an immediately-preceding lot in the current process, a completeness value set in the immediately-preceding lot in the current process, a summation of completeness value sets in the immediately-preceding lot to a process immediately-preceding to the current process, and a summation of completeness value sets in the current lot to the immediately-preceding process; and a correction control unit configured to control correction of the scale and the rotation of the pattern in the chip by using the correction value sets.Type: GrantFiled: April 27, 2009Date of Patent: January 10, 2012Assignee: Renesas Electronics CorporationInventors: Yoshiaki Yanagawa, Yuki Okada -
Patent number: 8092960Abstract: An exposure mask forms a three-dimensional shape in simple structure and obtainable sufficient number of gray scales by exposure. In an exposure mask (M) for use in an exposure apparatus (S), the present invention is provided such that a plurality of pattern blocks constituted by a pair of a light blocking pattern blocking light emitted from the exposure apparatus (S) and a transmissive pattern transmitting the light are continuously arranged while a pitch of the continuous pattern blocks is constant and a ratio of the light blocking pattern to the transmissive pattern is varied gradually.Type: GrantFiled: October 8, 2008Date of Patent: January 10, 2012Assignee: Sony CorporationInventor: Ken Ozawa
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Patent number: 8095897Abstract: A method of laying out features for alternating aperture phase shift masks. The method includes defining features on a grid of a uniform basic pitch, orienting the features such that those of the features defined, at least in part, by phase shifting shapes are oriented along a primary direction, and spacing two features terminating adjacent one another such that the two features have space between them sufficient to prevent phase conflicts if both of the two features are defined, at least in part, by phase shifting shapes.Type: GrantFiled: October 22, 2008Date of Patent: January 10, 2012Assignee: International Business Machines CorporationInventor: Kevin W. McCullen
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Patent number: 8088539Abstract: In an exposure aligning method, a first shift amount indicating a shift amount of a lower layer pattern of an exposure target substrate from an origin point position is determined and a second shift amount indicating a shift amount of the lower layer pattern in at lease one past lot which has been processed before said exposure target substrate is processed, from the origin point position is determined. A third shift amount indicating a difference between the first shift amount and the second shift amount is calculated and a first correction value is determined based on the third shift amount. An exposure position of an exposure target pattern is adjusted based on the first correction value.Type: GrantFiled: May 15, 2009Date of Patent: January 3, 2012Assignee: Renesas Electronics CorporationInventor: Eiichirou Yamanaka
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Patent number: 8084194Abstract: A method of substrate edge treatment includes forming a processing target film on a treatment target substrate, applying an energy line to a predetermined position on the processing target film to form a latent image on the processing target film, heating the treatment target substrate in which the latent image is formed on the processing target film, developing the processing target film after the heating, inspecting whether a residue is present at an edge of the treatment target substrate after the developing, and cleaning an end of the treatment target substrate to remove the residue at the edge of the treatment target substrate determined to be defective in the inspecting.Type: GrantFiled: February 16, 2007Date of Patent: December 27, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tomoyuki Takeishi, Yuji Kobayashi
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Patent number: 8086973Abstract: A pattern management method includes extracting patterns having process margins equal to or below a predetermined value from a chip layout of an integrated circuit, screening a plurality of types of representative patterns from the extracted pattern, extracting patterns closest to the most outer periphery of the chip from the representative patterns, and representatively managing the extracted patterns which is closest to the most outer periphery of the chip.Type: GrantFiled: December 18, 2007Date of Patent: December 27, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Yoshida, Soichi Inoue
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Patent number: 8081294Abstract: A method of evaluating an exposure optical beam source of an exposure device used in an exposure process in manufacturing a semiconductor device is disclosed, in which the method includes dividing an exposure optical beam source into a plurality of unit optical beam sources in a unit size determined by an exposure device, acquiring a difference between an evaluation amount of a target pattern on a semiconductor substrate when a unit optical beam source is turned on and an evaluation amount of the target pattern on the semiconductor substrate when the unit optical beam source is turned off, and evaluating the exposure optical beam source by using the acquired difference as an index.Type: GrantFiled: April 11, 2008Date of Patent: December 20, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Akiko Mimotogi
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Patent number: 8078996Abstract: A pattern verification method includes preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, and computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges. The positional displacement is a displacement between first point and the evaluation point. The method further includes computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.Type: GrantFiled: June 19, 2009Date of Patent: December 13, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kyoko Izuha, Shigeki Nojima, Toshiya Kotani, Satoshi Tanaka
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Patent number: 8076252Abstract: In a substrate processing method, a substrate to be processed is mounted on a mounting table in a processing chamber of a substrate processing apparatus, and while heating the substrate by a heating unit through the mounting table to a processing temperature of 700° C. or higher, the substrate is processed. The substrate to be processed is loaded into the processing chamber, a first preliminary heating is performed until the substrate reaches a prescribed temperature while being mounted on the mounting table. Then, substrate supporting pins of the mounting table are elevated, and a second preliminary heating is performed in a state where the substrate is held on the substrate supporting pins. Then, the substrate supporting pins are moved down to mount the substrate on the mounting table and a process such as plasma oxidation is performed thereon.Type: GrantFiled: July 28, 2006Date of Patent: December 13, 2011Assignee: Tokyo Electron LimitedInventor: Koichi Takatsuki
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Patent number: 8074188Abstract: A method for designing a mask is disclosed. A chip region can be defined and reduced to form a parent dummy pattern. A mesh dummy pattern can be formed, and portions where the parent dummy pattern and the mesh dummy pattern overlap each other can be removed to form offspring dummy patterns.Type: GrantFiled: May 9, 2008Date of Patent: December 6, 2011Assignee: Dongbu HiTek Co., Ltd.Inventors: Sang Hee Lee, Gab Hwan Cho
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Patent number: 8068213Abstract: A photomask has a monitoring pattern configured to obtain information required for adjusting optical system of a projection lithography tool. The monitoring pattern encompasses a mask substrate and an asymmetrical diffraction grating delineated on the mask substrate, configured to generate a positive first order diffracted light and a negative first order diffracted light in different diffraction efficiencies. The asymmetrical diffraction grating includes a plurality of probing-phase shifters, disposed periodically on the mask substrate in parallel, and a plurality of opaque strips disposed on light-shielding faces of the probing-phase shifters. An asymmetrically recessed ridge implements each of the probing-phase shifters.Type: GrantFiled: December 10, 2008Date of Patent: November 29, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Sato, Takashi Sakamoto
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Patent number: 8067135Abstract: Metrology systems and methods for lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a mask having a plurality of corner rounding test patterns formed thereon. A first semiconductor device is provided, and a layer of photosensitive material of the first semiconductor device is patterned with a plurality of corner rounding test features using the mask and a lithography process. An amount of corner rounding of the lithography process is measured by analyzing the plurality of corner rounding test features relative to other of the plurality of corner rounding test features formed on the layer of photosensitive material of the semiconductor device. The lithography process or the mask is altered in response to the amount of corner rounding measured, and a second semiconductor device is provided. The second semiconductor device is affected using the altered lithography process or the altered mask.Type: GrantFiled: July 23, 2010Date of Patent: November 29, 2011Assignee: Infineon Technologies AGInventors: Chandrasekhar Sarma, Jingyu Lian, Matthias Lipinski, Haoren Zhuang
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Patent number: 8067134Abstract: The field of this disclosure is making three-dimensional topographic structures by means of graduated exposure in a photosensitive material, such as a photoresist, photosensitive polymide, or similar. Such patterns may be written either to be used directly as optical, mechanical, fluidic, etc. components, e.g. diffusors, non-reflecting surfaces, Fresnel lenses and Fresnel prisms, computer-generated holograms, lenslet arrays, etc, or to be used as masters for the fabrication of such components by replication. Replication can be done by molding, pressing, embossing, electroplating, etching, as known in the art. This disclosure includes descriptions of using passive absorbing components in thin resist, using high gamma thick resists with high resolution pattern generators, using multiple focal planes including at least one focal plane in the bottom half of the resist, and iterative simulation of patterning and adjustment of an exposure map.Type: GrantFiled: October 22, 2009Date of Patent: November 29, 2011Assignee: Micronic MyData ABInventors: Torbjörn Sandström, Mikael Wahlsten, Mats Ekberg, Anders Svensson
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Patent number: 8068212Abstract: A lithographic apparatus configured to apply corrections to the dose, within and/or between fields, to compensate for critical dimension variations due to heating of elements of the projection system is disclosed.Type: GrantFiled: September 28, 2010Date of Patent: November 29, 2011Assignee: ASML Netherlands B.V.Inventors: Marcus Adrianus Van De Kerkhof, M'Hamed Akhssay, Mamoun El Ouasdad, Asis Uasghiri
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Patent number: 8068663Abstract: The intensity distribution of an optical image in a resist film is calculated (S1); the intensity distribution of the optical image is transformed through a Fourier transform in a periodic direction of the intensity distribution of the optical image (S2) and is transformed through a spectral transform in an aperiodic direction of the intensity distribution of the optical image by use of a base which satisfies a boundary condition (S3); a modulation function for modulating the intensity distribution of the optical image is transformed through a Fourier transform in the periodic direction (S4) and is transformed through a spectral transform in the aperiodic direction by use of the base satisfying the boundary direction (S5); a product of the post-transformed intensity distribution of the optical image and the post-transformed modulation function is computed (S6), is transformed through an inverse Fourier transform in the periodic direction (S7), and is transformed through an inverse spectral transform in the apType: GrantFiled: August 7, 2008Date of Patent: November 29, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masanori Takahashi, Satoshi Tanaka
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Patent number: 8062813Abstract: In the field of semiconductor device production, a method for manufacturing a surface using two-dimensional dosage maps is disclosed. A set of charged particle beam shots for creating an image on the surface is determined by combining dosage information such as dosage maps for a plurality of shots into the dosage map for the surface. A similar method is disclosed for fracturing or mask data preparation of a reticle image.Type: GrantFiled: March 31, 2010Date of Patent: November 22, 2011Assignee: D2S, Inc.Inventors: Harold Robert Zable, Akira Fujimura
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Patent number: 8057971Abstract: The field of this disclosure is making three-dimensional topographic structures by means of graduated exposure in a photosensitive material, such as a photoresist, photosensitive polymide, or similar. Such patterns may be written either to be used directly as optical, mechanical, fluidic, etc. components, e.g. diffusors, non-reflecting surfaces, Fresnel lenses and Fresnel prisms, computer-generated holograms, lenslet arrays, etc, or to be used as masters for the fabrication of such components by replication. Replication can be done by molding, pressing, embossing, electroplating, etching, as known in the art. This disclosure includes descriptions of using passive absorbing components in thin resist, using high gamma thick resists with high resolution pattern generators, using multiple focal planes including at least one focal plane in the bottom half of the resist, and iterative simulation of patterning and adjustment of an exposure map.Type: GrantFiled: October 22, 2009Date of Patent: November 15, 2011Assignee: Micronic MyData ABInventors: Torbjörn Sandström, Mikael Wahlsten, Mats Ekberg, Anders Svensson
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Patent number: 8057970Abstract: A method for forming circular patterns on a surface using a character projection (CP) charged particle beam writer is disclosed, wherein circular patterns of different sizes may be formed using a single CP character, by varying dosage. A method for forming circular patterns on a surface using a variable shaped beam (VSB) charged particle beam writer is also disclosed, wherein the dosages of the shots may vary, and wherein the union of the shots is different than the set of target patterns. A method for forming circular patterns on a surface using a library of glyphs is also disclosed, wherein the glyphs are pre-calculated dosage maps that can be formed by one or more charged particle beam shots.Type: GrantFiled: August 12, 2009Date of Patent: November 15, 2011Assignee: D2S, Inc.Inventors: Akira Fujimura, Michael Tucker
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Patent number: 8057967Abstract: A method for identifying process window signature patterns in a device area of a mask is disclosed. The signature patterns collectively provide a unique response to changes in a set of process condition parameters to the lithography process. The signature patterns enable monitoring of associated process condition parameters for signs of process drift, analyzing of the process condition parameters to determine which are limiting and affecting the chip yields, analyzing the changes in the process condition parameters to determine the corrections that should be fed back into the lithography process or forwarded to an etch process, identifying specific masks that do not transfer the intended pattern to wafers as intended, and identifying groups of masks that share common characteristics and behave in a similar manner with respect to changes in process condition parameters when transferring the pattern to the wafer.Type: GrantFiled: February 23, 2010Date of Patent: November 15, 2011Assignee: ASML Netherlands B.V.Inventors: Jun Ye, Moshe E. Preil, Xun Chen, Shauh-Teh Juang, James Wiley
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Patent number: 8057972Abstract: The invention relates to a method for forming a pattern on a substrate surface of a target by means of a beam of electrically charged particles in a number of exposure steps, where the beam is split into a patterned beam and there is a relative motion between the substrate and the pattern definition means. This results in an effective overall motion of the patterned particle beam over the substrate surface and exposition of image elements on the substrate surface in each exposure step, wherein the image elements on the target are exposed to the beamlets multiply, namely several times during a number of exposure steps according to a specific sequence. The sequence of exposure steps of the image elements is arranged in a non-linear manner according to a specific rule from one exposure step to the subsequent exposure step in order to reduce the current variations in the optical column of the multi-beam exposure apparatus during the exposure of the pattern.Type: GrantFiled: November 16, 2009Date of Patent: November 15, 2011Assignee: IMS Nanofabrication AGInventors: Heinrich Fragner, Elmar Platzgummer, Adrian Bürli
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Publication number: 20110275015Abstract: A disclosed fixing device applying a bubble-like fixing liquid to resin-containing particles adhered to a medium so that the resin-containing particles are fixed to the medium, the bubble-like fixing liquid being formed by transforming a fixing liquid into foam that dissolves or swells at least a part of the resin, includes a control device that, based on a difference between a moisture content included in the medium after fixing and a target value of the moisture content, adjusts an application amount of the fixing liquid for a next medium.Type: ApplicationFiled: April 13, 2011Publication date: November 10, 2011Inventors: Kazuya NAGAO, Takuma Nakamura, Yuichi Aoyama, Masafumi Yamada, Shunichi Abe, Tetsurou Sasamoto, Takanori Inadome
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Patent number: 8056032Abstract: Methods of measuring a mean-to-target (MTT) based on pattern area measurements are provided including providing a design pattern. A plurality of design pattern measurements are measured for calculating an area of the design pattern based on a shape of the design pattern. A series of calculation measurements are calculated by continuously substituting a same variation into the design pattern measurements, and calculating a series of calculation areas corresponding respectively to the calculation measurements to generate a database including the calculation measurements and the calculation areas. An actual pattern is formed using the design pattern and an area of the actual pattern is measured. A calculation area corresponding to the area of the actual pattern is selected from the database and calculation measurements corresponding to the calculation area are selected. A difference between the design pattern measurements and the calculation measurements is calculated and the difference is set as an MTT.Type: GrantFiled: November 24, 2008Date of Patent: November 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-joo Lee, So-yoon Bae, Yo-han Choi, Jong-won Kim, Dong-hoon Chung
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Patent number: 8055099Abstract: An exposure method capable of performing accurate exposure without using a large photomask. The exposure method performs exposure while relatively moving a photomask above a substrate and includes a step of performing position correction of the photomask by performing, on a front side of the photomask relatively moved in a moving direction, image recognition of a pattern prearranged on the substrate such as a line and a black matrix and by correcting deviation of the photomask with respect to the pattern, and a step of checking the position correction of the photomask by performing image recognition of a reference mark arranged on the photomask and by determining whether or not the position correction of the photomask is accurately performed in the step of performing the position correction of the photomask.Type: GrantFiled: December 8, 2006Date of Patent: November 8, 2011Assignee: Sharp Kabushiki KaishaInventors: Shouichi Ogata, Daisuke Fuse, Yasuo Minami
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Publication number: 20110269061Abstract: Disclosed is a developing method that performs a developing for forming a second resist pattern after forming and exposing a resist film on a surface of a substrate on which a first resist pattern is formed. The method includes a first process for developing the substrate for a first time period t1 in the state where the substrate stops, and a second process for developing the substrate for a second time period while rotating the substrate. The time ratio of first time period and second time period is adjusted so that a critical dimension of the first resist pattern is equal to a first predetermined value, and a total time of first time period and second time period is adjusted so that a critical dimension of the second resist pattern is equal to a second predetermined value.Type: ApplicationFiled: April 28, 2011Publication date: November 3, 2011Applicant: TOKYO ELECTRON LIMITEDInventor: Kousuke YOSHIHARA
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Patent number: 8048588Abstract: A method and structure for removing side lobes is provided by positioning first and second radiation transparent regions of respective first and second phases at a first plane with the first and second phases being substantially out of phase. Further, positioning the first and the second region to cause radiation at a second plane to be neutralized in a first region, not to be neutralized in a second region, and to have a side lobe in a third region. Further, positioning a non-transparent region at the first plane to assure radiation at the second plane to be neutralized in the first region and positioning a third radiation transparent region of the first or second phase at the first plane to neutralize the side lobes in the third region at the second plane.Type: GrantFiled: October 20, 2004Date of Patent: November 1, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Sia Kim Tan, Soon Yoeng Tan, Qunying Lin, Huey Ming Chong, Liang-Choo Hsia
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Patent number: 8048600Abstract: A parameter extracting method capable of accurately and effectively extracting parameters used for charged particle beam exposure. The method comprises the steps of forming an unknown parameter layer on a known parameter layer, forming a resist on the unknown parameter layer, subjecting the resist to exposure through patterns changed in an existing range, and extracting parameters of the unknown parameter layer using the exposure result. In the parameter extraction method, parameters of layers lower than the unknown parameter layer are known. Therefore, layer combinations to be considered and the number of experimental data can be drastically reduced. After parameter extraction of the unknown parameter layer, an unknown parameter layer is newly formed on the layer. Then, the parameter thereof is extracted in the same manner.Type: GrantFiled: October 31, 2005Date of Patent: November 1, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Kozo Ogino
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Patent number: 8051390Abstract: A method of design of a standard cell and a standard cell is disclosed. The method design comprising the steps of: identifying a non-uniformity in a boundary condition of said standard cell that would affect a characteristic of a neighbouring standard cell; introducing a further non-uniformity into said cell to mitigate the effect of said identified non-uniform boundary condition on said characteristic of said neighbouring standard cell.Type: GrantFiled: October 7, 2008Date of Patent: November 1, 2011Assignee: ARM LimitedInventors: Marlin Wayne Frederick, David Paul Clark
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Patent number: 8043797Abstract: A method for transferring an image of a mask pattern through a pitch range onto a substrate is presented. In an embodiment, the method includes illuminating the mask pattern of an attenuated phase shift mask using a multipole illumination that includes an on-axis component and an off-axis component, the mask pattern including non-printing assist features configured for a pitch larger than twice a minimum pitch of the mask pattern, and projecting an image of the illuminated mask pattern onto the substrate.Type: GrantFiled: April 27, 2005Date of Patent: October 25, 2011Assignee: ASML Netherlands B.V.Inventor: Steven George Hansen
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Patent number: 8043772Abstract: In an exposure process forming a predetermined circuit pattern of a semiconductor device on a wafer, a resist dimension of the resist pattern formed on a wafer and a focus position in the exposure process at a past time are measured. A resist dimension and a focus position of a wafer to which the exposure process is secondly performed are estimated by using measurement results of the measured resist dimension and focus position, and a focus offset value is calculated by using estimated values of the estimated resist dimension and focus position. Then, an exposure dose is calculated with considering this focus offset value, and a resist pattern is formed on the wafer to which the exposure process is performed by using the calculated exposure dose and focus offset value.Type: GrantFiled: May 15, 2009Date of Patent: October 25, 2011Assignee: Renesas Electronics CorporationInventors: Toshiharu Miwa, Junko Konishi, Toshihide Kawachi, Shigenori Yamashita, Takeshi Tashiro, Hidekimi Fudo
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Patent number: 8040497Abstract: By encoding process-related non-uniformities, such as different height levels, which may be caused by CMP or other processes during the fabrication of complex device levels, such as metallization structures, respective focus parameter settings may be efficiently evaluated on the basis of well-established CD measurement techniques.Type: GrantFiled: May 30, 2007Date of Patent: October 18, 2011Assignee: GLOBALFOUNDRIES Inc.Inventors: Thomas Werner, Frank Feustel, Kai Frohberg
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Patent number: 8042067Abstract: A pattern forming method of forming a desired pattern on a semiconductor substrate is disclosed, which comprises extracting a first pattern of a layer, extracting a second pattern of one or more layers overlapped with the layer, the second pattern being arranged close to or overlapped with the first pattern, calculating a distance between the first and second patterns on a semiconductor substrate in consideration of a predetermined process variation, determining whether or not the distance between the first and second patterns satisfy an allowable margin given for the distance between the first and second patterns, and correcting, if the distance does not satisfy the allowable margin, at least one of the first and second patterns to satisfy the allowable margin.Type: GrantFiled: July 1, 2008Date of Patent: October 18, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Ayako Nakano, Toshiya Kotani
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Patent number: 8039176Abstract: In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a series of curvilinear character projection shots are determined for a charged particle beam writer system, such that the set of shots can form a continuous track, possibly of varying width, on a surface. A method for forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed. Methods for manufacturing a reticle and for manufacturing a substrate such as a silicon wafer by forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed.Type: GrantFiled: November 14, 2009Date of Patent: October 18, 2011Assignee: D2S, Inc.Inventors: Akira Fujimura, Michael Tucker
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Patent number: 8039181Abstract: By taking into consideration the combination of the substrate holders in various lithography tools used during the imaging to two subsequent device layers, enhanced alignment accuracy may be accomplished. Furthermore, restrictive tool dedications for critical lithography processes may be significantly relaxed by providing specific overlay correction data for each possible process flow, wherein, in some illustrative embodiments, a restriction of the number of possible process flows may be accomplished by implementing a rule for selecting a predefined substrate holder when starting the processing of an associated group of substrates.Type: GrantFiled: June 2, 2009Date of Patent: October 18, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Rolf Seltmann, Jens Busch, Uwe Schulze