Including Control Feature Responsive To A Test Or Measurement Patents (Class 430/30)
  • Patent number: 8354209
    Abstract: A lithographic apparatus, includes a support structure configured to hold a patterning device, the patterning device configured to impart a beam of radiation with a pattern in its cross-section; a substrate table configured to hold a substrate; a projection system configured to project the patterned beam onto a target portion of the substrate; a liquid supply system configured to provide liquid to a space between the projection system and the substrate table; a sensor configured to measure an exposure parameter using a measuring beam projected through the liquid; and a correction system configured to determine an offset based on a change of a physical property impacting a measurement made using the measuring beam to at least partly correct the measured exposure parameter.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: January 15, 2013
    Assignee: ASML Netherlands B.V.
    Inventors: Bob Streefkerk, Johannes Jacobus Matheus Baselmans, Sjoerd Nicolaas Lambertus Donders, Jeroen Johannes Sophia Maria Mertens, Johannes Catharinus Hubertus Mulkens, Christiaan Alexander Hoogendam
  • Patent number: 8352892
    Abstract: The present invention provides a generation method that obtains a position at which an auxiliary pattern is to be placed and generates a mask pattern (its data), which achieves excellent imaging performance, even when a halftone mask is used as an original.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: January 8, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Manabu Hakko, Miyoko Kawashima
  • Patent number: 8343693
    Abstract: A focus test reticle for measuring focus information includes an outer pattern. The outer pattern has a line pattern composed of a light shielding film extending in the Y direction, a phase shift portion provided on a side in the +X direction of the line pattern and formed to have a line width narrower than the line pattern, a transmitting portion provided on a side in the ?X direction of the line pattern and formed to have a line width narrower than the line pattern, a transmitting portion provided on a side in the +X direction of the phase shift portion, and a phase shift portion provided on a side in the ?X direction of the transmitting portion. Focus information of a projection optical system is measured at a high measuring reproducibility and a high measuring efficiency.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: January 1, 2013
    Assignee: Nikon Corporation
    Inventors: Shigeru Hirukawa, Shinjiro Kondo
  • Patent number: 8343695
    Abstract: In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a series of curvilinear character projection shots are determined for a charged particle beam writer system, such that the set of shots can form a continuous track, possibly of varying width, on a surface. In some embodiments, characteristics of the continuous track will be within a predetermined tolerance.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: January 1, 2013
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Michael Tucker
  • Patent number: 8345244
    Abstract: An exposure apparatus includes a controller configured to calculate a position of an alignment mark detected by a detector, to approximate a deformation of a substrate by using an approximation equation, to calculate a correction amount of each of the plurality of shots, and to control driving of a stage in exposing each shot based on a correction amount that is calculated. The approximation equation is defined as a sum of a first term representative of a deformation of the entire substrate, and at least one of a second term representative of a distortion of a shot arrangement and a third term representative of a shot shape.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: January 1, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shinichiro Koga
  • Patent number: 8341561
    Abstract: Methods and apparatus are disclosed that arrange mask patterns in response to the contribution of a second pattern to image intensity. In some methods of arranging mask patterns, a distribution of functions h(??x) is obtained which represents the contribution of a second pattern to image intensity on a first pattern. Neighboring regions of the first pattern are discretized into finite regions, and the distribution of the functions h(??x) is replaced with representative values h(x,?) of the discretized regions. A position of the second pattern is determined using polygonal regions having the same h(x,?). As described, the term x is the position of the first pattern and the term ? is the position of the assist.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: December 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-woon Park, Woo-sung Han, Seong-woon Choi, Jeong-ho Yeo
  • Patent number: 8338063
    Abstract: The energy distribution of exposure light directed passing through the slit of an exposure apparatus is determined. A photoresist layer on a substrate is exposed over a plurality of shots while changing the intensity of the exposure light for each shot. Then the photoresist layer is developed to form a sample photoresist layer. An image of the developed sample photoresist layer is analyzed for color intensity. Values of the color intensity across a selected one of the shots are correlated with values of the intensity of the exposure light to produce an energy distribution of the exposure light along the length of the slit. The energy distribution is used to change the slit so that a more desirable energy distribution may be realized when the slit is used in a process of manufacturing a semiconductor device.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: December 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Seok Heo, Seok-Hwan Oh, Jeong-Ho Yeo
  • Patent number: 8334083
    Abstract: A method of patterning a multi-layer mask is described. The method includes preparing a multi-layer mask on a substrate, wherein the multi-layer mask includes a lithographic layer and an intermediate mask layer underlying the lithographic layer, and wherein the intermediate mask layer comprises a carbon-containing compound.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: December 18, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Vinh Hoang Luong, Akiteru Ko
  • Patent number: 8336005
    Abstract: A pattern dimension calculation method according to one embodiment calculates a taper shape of a mask member used as a mask when a circuit pattern is processed in an upper layer of the circuit pattern formed on a substrate. The method calculates an opening angle facing the mask member from a shape prediction position on the circuit pattern on the basis of the taper shape. The method calculates a dimension of the circuit pattern according to the opening angle formed at the shape prediction position.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: December 18, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takafumi Taguchi, Toshiya Kotani, Hiromitsu Mashita, Fumiharu Nakajima, Ryota Aburada, Chikaaki Kodama
  • Patent number: 8336002
    Abstract: An integrated circuit (IC) design method includes providing IC design layout data; simulating a chemical mechanical polishing (CMP) process to a material layer based on the IC design layout, to generate various geometrical parameters; extracting resistance and capacitance based on the various geometrical parameters from the simulating of the CMP process; and performing circuit timing analysis based on the extracted resistance and capacitance.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: December 18, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gwan Sin Chang, Yi-Kan Cheng, Ivy Chiu, Ke-Ying Su
  • Patent number: 8330104
    Abstract: A pattern measurement apparatus includes a beam intensity distribution creation unit to scan a charged particle beam over a reference pattern having edge portions formed at a right angle to create a line profile of the reference pattern and thus create a reference-beam intensity distribution, an edge width detection unit to determine line profiles for pattern models including edges formed at various inclination angles by use of the reference-beam intensity distribution and calculate edge widths reflecting an influence of a width of a reference beam, and a correspondence table creation unit to calculate correction values for edge positions from the calculated edge widths and the pattern models and create a correspondence table in which the edge widths and the correction values are associated with one another.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: December 11, 2012
    Assignee: Advantest Corp.
    Inventor: Jun Matsumoto
  • Patent number: 8329365
    Abstract: A method for fracturing or mask data preparation or optical proximity correction is disclosed, wherein a plurality of variable shaped beam (VSB) shots are determined for at least one exposure pass, where the plurality of VSB shots forms a line pattern which is at a diagonal to the axes of a Cartesian coordinate plane, and where at least two neighboring shots in the same exposure pass overlap. Methods for manufacturing a surface using charged particle beam lithography and for manufacturing an integrated circuit using an optical lithography process are also disclosed.
    Type: Grant
    Filed: November 20, 2011
    Date of Patent: December 11, 2012
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Harold Robert Zable
  • Patent number: 8318393
    Abstract: According to the embodiment, an optical image intensity distribution to be formed in a resist arranged on a lower layer side of a diffraction pattern is calculated by performing a whole image exposure from an upper surface side of the diffraction pattern formed on a substrate. The optical image intensity distribution is calculated by using a multimode waveguide analysis model or a fractional Fourier transform with respect to the diffraction pattern.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: November 27, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanori Takahashi, Satoshi Tanaka
  • Patent number: 8318392
    Abstract: An alignment method is disclosed, in which a distance between a substrate and a photomask is set at a predetermined exposure gap. The photomask is rectangular, and includes a first side, and a second side opposite to the first side. A distance between a midpoint of the first side and the substrate is matched with the exposure gap. The photomask is rotated about, as an axis, a line that connects the midpoint of the first side and a midpoint of the second side to each other, whereby distances between both ends of the first side and the substrate are individually matched with the exposure gap. The photomask is rotated about the first side taken as an axis, whereby a distance between the midpoint of the second side and the substrate is matched with the exposure gap.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: November 27, 2012
    Assignee: Panasonic Corporation
    Inventors: Ryota Hamada, Tomohiro Murakoso
  • Patent number: 8318391
    Abstract: A method for identifying process window signature patterns in a device area of a mask is disclosed. The signature patterns collectively provide a unique response to changes in a set of process condition parameters to the lithography process. The signature patterns enable monitoring of associated process condition parameters for signs of process drift, analyzing of the process condition parameters to determine which are limiting and affecting the chip yields, analyzing the changes in the process condition parameters to determine the corrections that should be fed back into the lithography process or forwarded to an etch process, identifying specific masks that do not transfer the intended pattern to wafers as intended, and identifying groups of masks that share common characteristics and behave in a similar manner with respect to changes in process condition parameters when transferring the pattern to the wafer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: November 27, 2012
    Assignee: ASML Netherlands B.V.
    Inventors: Jun Ye, Moshe E. Preil, Xun Chen, Shauh-Teh Juang, James Wiley
  • Patent number: 8321822
    Abstract: A method optical proximity correction includes the following steps. First, a layout of an integrated circuit with an exposure intensity specification is provided. The integrated circuit includes a plurality of patterns and each pattern has an exposure intensity distribution. Second, a quadratic polynomial equation of each exposure intensity distribution is approximated. Third, a local extreme intensity of each exposure intensity distribution is computed by fitting the quadratic polynomial equation. Fourth, the local extreme intensity is determined whether violating the exposure intensity specification or not. Then, the layout is corrected when the local extreme intensity violates the exposure intensity specification.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: November 27, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Shiang Yang, Ming-Jui Chen, Te-Hung Wu
  • Patent number: 8308381
    Abstract: The substrate processing system includes a measuring apparatus that measures any of film thickness, a refractive index, an absorption coefficient, and warpage. The system includes an apparatus for performing photolithography on the substrate to form a resist pattern and an etching apparatus that etches a processing film. A control unit includes a first relation between an initial condition and a dimension of the pattern of the processing film and a second relation between a processing condition of the predetermined processing and the dimension of the pattern of the processing film. The control unit estimates a dimension of the pattern of the processing film after the etching treatment from the first relation based on a measurement result and corrects the processing condition of the predetermined processing in the photolithography or the etching from the second relation based on an estimation result of the dimension of the pattern.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: November 13, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Masahide Tadokoro, Kunie Ogata
  • Patent number: 8309283
    Abstract: A writing method includes calculating a proximity effect-corrected dose for correcting a proximity effect in charged particle beam writing, for each first mesh region made by virtually dividing a writing region of a target object into a plurality of first mesh regions of a first mesh size, calculating a fogging effect-corrected dose by using the proximity effect-corrected dose calculated and an area density in the first mesh size with respect to a part of a calculation region for calculating the fogging effect-corrected dose for correcting a fogging effect in the charged particle beam writing, and by using an area density in a second mesh size larger than the first mesh size with respect to a remaining part of the calculation region, synthesizing the fogging effect-corrected dose and the proximity effect-corrected dose for the each first mesh region, and writing a pattern on the target object by using a charged particle beam based on a synthesized correction dose.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: November 13, 2012
    Assignee: NuFlare Technology, Inc.
    Inventors: Yasuo Kato, Jun Yashima, Hiroshi Matsumoto, Tomoo Motosugi, Tomohiro Iijima, Takayuki Abe
  • Patent number: 8309282
    Abstract: An apparatus and method for aligning a mask that includes disposing and firstly aligning a mask over a first substrate, with a space interposed therebetween, bringing the mask into contact with the first substrate and then measuring the alignment state of the mask with respect to the first substrate to detect an alignment error, secondly aligning the mask with respect to the first substrate based on the alignment error, transferring the first substrate to the next process, disposing and thirdly aligning the mask over a second substrate with the space interposed therebetween, and bringing the mask into contact with the second substrate.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: November 13, 2012
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kyung-Hoon Chung, Hyung-Min Kim
  • Publication number: 20120282774
    Abstract: Masks for patterning material layers of semiconductor devices, methods of patterning and methods of manufacturing semiconductor devices, and lithography systems are disclosed. A lithography mask includes a pattern of alternating lines and spaces, wherein the lines and spaces comprise different widths. When the lithography mask is used to pattern a material layer of a semiconductor device, the pattern of the material layer comprises alternating lines and spaces having substantially the same width.
    Type: Application
    Filed: July 12, 2012
    Publication date: November 8, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Yayi Wei
  • Patent number: 8304148
    Abstract: A method for fracturing or mask data preparation or proximity effect correction of a pattern to be formed on a surface is disclosed in which a plurality of variable shaped beam (VSB) shots are determined, and in which charged particle beam simulation is used to calculate the pattern which the plurality of VSB shots will form on the surface. At least two shots in the plurality of VSB shots overlap each other. In some embodiments, assigned dosages of at least two shots differ before proximity effect correction (PEC). In other embodiments an optimization technique may be used embodiments.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: November 6, 2012
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Lance Glasser
  • Patent number: 8298732
    Abstract: An exposure method includes generating a reticle exposure pattern based on a target pattern, performing a lithography simulation based on the reticle exposure pattern to generate a simulation pattern that simulates a resist pattern formed by reticle exposure, generating differential data between the target pattern and the simulation pattern, generating a first electron-beam exposure pattern based on the differential data, generating a reticle based on the reticle exposure pattern, performing an optical exposure process with respect to a resist by use of the reticle, and performing an electron-beam exposure process with respect to the resist based on the first electron-beam exposure pattern.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: October 30, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masahiko Minemura, Seiji Makino, Kanji Takeuchi, Noboru Sugiyama, Kozo Ogino
  • Patent number: 8302035
    Abstract: A method for verifying an optical proximity correction includes: performing an optical proximity correction on a target pattern layout; performing a primary verification on the target pattern layout which has undergone the optical proximity correction; performing a secondary verification on defect weak points detected in the primary verification; and performing an additional optical proximity correction on hot spot points which are detected in the secondary verification and which may be generated as defects when transferred to a real wafer.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: October 30, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin Young Choi
  • Publication number: 20120270144
    Abstract: Presented are methods for forming a predetermined pattern in a predetermined area of an elongated sheet material. The methods include applying a two-dimensional tension to a portion including the predetermined area of the sheet material, and allowing a flat reference surface to adsorb a rear surface portion corresponding to the predetermined area of the sheet material applied with the two-dimensional tension. The methods then illuminate an energy beam corresponding to the pattern to the predetermined area of the sheet material adsorbed to the reference surface.
    Type: Application
    Filed: June 18, 2012
    Publication date: October 25, 2012
    Inventors: Tohru KIUCHI, Hideo MIZUTANI
  • Patent number: 8289516
    Abstract: A method of measuring focus of a lithographic projection apparatus includes exposure of a photoresist covered test substrate with a plurality of verification fields. Each of the verification fields includes a plurality of verification markers, and the verification fields are exposed using a predetermined focus offset FO. After developing, an alignment offset for each of the verification markers is measured and translated into defocus data using a transposed focal curve. The method according to an embodiment of the invention may result in a focus-versus alignment shift sensitivity up to 50 times higher (typically dX,Y/dZ=20) than conventional approaches.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: October 16, 2012
    Assignee: ASML Netherlands B.V.
    Inventors: Gerardus Carolus Johannus Hofmans, Hubertus Antonius Geraets, Mark Zellenrath, Sven Gunnar Krister Magnusson
  • Patent number: 8288063
    Abstract: A method includes performing a lithography process on a wafer to form a patterned photo resist, and measuring the wafer to determine an overlay error of the patterned photo resist. A high/low specification is determined using the overlay error. An overlay process value setting is generated and compared with the high/low specification to determine whether the overlay process value setting is within a range defined by the high/low specification.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: October 16, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Rung Lu, Chih Ming Hong, Yen-Di Tsen
  • Patent number: 8288064
    Abstract: A method for examining at least one wafer (13) with regard to a contamination limit, in which the contamination potential of the resist (13a) of the wafer (13), which resist (13a) outgasses contaminating substances, is examined with regard to a contamination limit before the wafer (13) is exposed in an EUV projection exposure system (1). The method preferably includes: arranging the wafer (13) and/or a test disc coated with the same resist (13a) as the resist (13a) of the wafer (13) in a vacuum chamber (19), evacuating the vacuum chamber (19), and measuring the contamination potential of the contaminating substances outgassed from the wafer (13) in the evacuated vacuum chamber (19), and also comparing the contamination potential of the wafer (13) with a contamination limit. An EUV projection exposure system (1) for carrying out the method is also disclosed.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: October 16, 2012
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Andreas Dorsel, Stefan Schmidt
  • Patent number: 8288061
    Abstract: A reticle includes: a repetition pattern; and a peripheral pattern. One of the repetition pattern and peripheral pattern is a first pattern with a first side in a first direction and the other is a second pattern with a second side in the first direction. The first side has a first length equal to or longer than a second length of the second side. The first length is n (n is an integer equal to or larger than 1) times as large as the second length. The first pattern has at least one of first misalignment measurement patterns provided at positions distant by a third length and ((the third length)+(n?1)×(the second length)) from an upper end of the first pattern. The third length is equal to or smaller than the second length. The second pattern has a second misalignment measurement pattern provided at a position distant by the third length from an upper end of the second pattern.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: October 16, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Taro Moriya
  • Publication number: 20120258391
    Abstract: The present invention provides a measurement apparatus which measures a position of a second object relative to a first object, the apparatus including a first measurement unit which includes a diffraction grating provided on the first object, and a first head and a second head provided on the second object, and is configured to measure the position of the second object relative to the first object by the first head or the second head, and a processing unit configured to perform a process of obtaining the position of the second object relative to the first object.
    Type: Application
    Filed: March 23, 2012
    Publication date: October 11, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Nobuo IMAOKA
  • Patent number: 8283094
    Abstract: In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a plurality of shots of circular or nearly-circular character projection characters, having at least two shots that overlap, can form a non-circular pattern on a surface. Methods for manufacturing a reticle and for manufacturing a substrate such as a silicon wafer by forming non-circular patterns on a surface using a plurality of circular or nearly-circular character projection shots, where at least two shots overlap, is also disclosed.
    Type: Grant
    Filed: October 16, 2011
    Date of Patent: October 9, 2012
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Michael Tucker
  • Publication number: 20120244461
    Abstract: Overlay control methods, semiconductor manufacturing method and a semiconductor manufacturing apparatus are provided for restraining overlay error between lithography processes, of a semiconductor manufacturing process, within a tolerance of a semiconductor device. According to one or more aspects, enhanced overlay control mechanisms are provided to enable previous layers to perform corrections to an extent that does not exceed a correction ability of a next layer. For instance, the next layer can inform the previous layer of a tolerated range that is correctable so that the previous layer can perform corrections without exceeding the tolerate range. Accordingly, a feedback loop is established that extends across two exposure events and is not closed within a single exposure event as with conventional systems.
    Type: Application
    Filed: March 25, 2011
    Publication date: September 27, 2012
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Satoshi Nagai
  • Patent number: 8266556
    Abstract: A method, system, and computer usable program product for fracturing a continuous mask usable in photolithography are provided in the illustrative embodiments. A first origin point is selected from a set of points on an edge in the continuous mask. A first end point is identified on the edge such that a separation metric between the first origin point and the first end point is at least equal to a threshold value. Several alternatives are determined for fracturing using the first origin point and the first end point. A cost associated with each of the several alternatives is computed and one of the alternatives is selected as a preferred fracturing. Several pairs of origin points and end points are formed from the set of points. Each pair has a cost of a preferred fracturing between the pair. The continuous mask is fractured using a subset of the several pairs.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: September 11, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ying Liu, David Osmond Melville, Alan E Rosenbluth, Kehan Tian
  • Patent number: 8263296
    Abstract: A lithographic system includes a monitored lithographic projection apparatus arranged to project a patterned beam onto a substrate. A scatterometer measures a plurality of parameters of the pattern transferred to the substrate including at least one CD-profile parameter and at least one further parameter of the pattern transferred to the substrate which is indicative of a machine setting of the monitored lithographic projection apparatus. A matching system includes a database storing information representative of reference CD values and reference values for the further feature. A comparison arrangement compares the measured values with the corresponding stored values, a lithographic parameter calculation means calculating a corrected set of machine settings for the monitored lithographic apparatus dependent on the differences between the measured and reference values.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: September 11, 2012
    Assignee: ASML Netherlands B.V.
    Inventors: Paul Christiaan Hinnen, Marcus Adrianus Van De Kerkhof, Reiner Maria Jungblut, Koenraad Remi André Maria Schreel
  • Patent number: 8263295
    Abstract: A method for optical proximity correction (OPC) of a desired pattern for a substrate is disclosed in which a plurality of variable shaped beam (VSB) shots are determined which can form on a surface an OPC-corrected version of the desired substrate pattern. Shots within the plurality of VSB shots are allowed to overlap each other. Dosages of the shots may also be allowed to vary with respect to each other. The union of the plurality of shots may deviate from the OPC-corrected version of the desired pattern for the substrate. In some embodiments, optimization may be used to minimize shot count. In other embodiments, the plurality of shots may be optionally selected from one or more pre-computed VSB shots or groups of VSB shots, that is, glyphs. A method for creating glyphs is also disclosed, in which patterns that would result on a surface from one or a group of VSB shots are pre-calculated.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: September 11, 2012
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Lance Glasser
  • Publication number: 20120226466
    Abstract: Non-uniformity of a rotatable electrophotographic imaging component is compensated. The component has an intentional periodic variation that produces density variations in a test target. The angular position on the component of the intentional variation is correlated with the amount of an unintentional variation at several points to produce a non-uniformity map. An image signal with multiple regions of data is received. For each region, the angular position of the intentional variation in that region is determined, and the non-uniformity map is used to determine the correction required for the unintentional variation. The image data in the region are adjusted to compensate, and corresponding toner is deposited.
    Type: Application
    Filed: March 4, 2011
    Publication date: September 6, 2012
    Inventor: Thomas Allen Henderson
  • Patent number: 8260033
    Abstract: A method is provided for determining the relative overlay shift of stacked layers, said method comprising the steps of: a) providing a reference image including a reference pattern that comprises first and second pattern elements; b) providing a measurement image of a measurement pattern, which comprises a first pattern element formed by a first one of the layers and a second pattern element formed by a second one of the layers; c) weighting the reference or measurement image such that a weighted first image is generated, in which the first pattern element is emphasized relative to the second pattern element; d) determining the relative shift of the first pattern element on the basis of the weighted first image and of the measurement or reference image not weighted in step c); e) weighting the reference or measurement image such that a weighted second image is generated, in which the second pattern element is emphasized relative to the first pattern element; f) determining the relative shift of the second pat
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: September 4, 2012
    Assignee: Carl Zeiss SMS GmbH
    Inventors: Michael Arnz, Gerd Klose
  • Patent number: 8257888
    Abstract: A first exposure dose for a shot area based upon layout data is determined. A correction dose compensating a dose deviation between a first point in time, at which a control unit configured to control a shot time period of a particle beam writing apparatus considers a charged particle beam as having reached a nominal current density, and a second point in time, at which the charged particle beam has actually reached a nominal current density, at a target substrate is determined.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: September 4, 2012
    Assignee: Advanced Mask Technology Center GmbH + Co. KG
    Inventors: Martin Sczyrba, Christian Buergel, Eugen Foca
  • Patent number: 8257911
    Abstract: A method for patterning a substrate is described. In particular, the invention relates to a method for double patterning a substrate using dual tone development. Further, the invention relates to optimizing a dual tone development process.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: September 4, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Roel Gronheid, Sophie Bernard, Carlos A. Fonseca, Mark Somervell, Steven Scheer
  • Patent number: 8253077
    Abstract: A processing temperature of thermal processing is corrected based on measurement of a first dimension of a resist pattern on a substrate from a previously obtained relation between a dimension of a resist pattern and a temperature of thermal processing, a second dimension of the resist pattern after thermal processing is performed at the corrected processing temperature is measured, a distribution within the substrate of the second dimension is classified into a linear component expressed by an approximated curved surface and a nonlinear component, a processing condition of exposure processing is corrected based on the linear component from a previously obtained relation between a dimension of a resist pattern and a processing condition of exposure processing, and thermal processing at the processing temperature corrected in a temperature correcting step and exposure processing under the processing condition corrected in an exposure condition correcting step are performed to form a predetermined pattern.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: August 28, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Kunie Ogata, Masahide Tadokoro, Tsuyoshi Shibata, Shinichi Shinozuka
  • Patent number: 8252489
    Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift. The step of simulating the worst-case performance includes calculating capacitance values corresponding to mask shifts, and the capacitance values are calculated using a high-order equation or a piecewise equation.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: August 28, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ke-Ying Su, Chung-Hsing Wang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng
  • Patent number: 8250496
    Abstract: A semiconductor device fabrication method is disclosed. The method includes obtaining an inverse layout of an original circuit layout, reducing the inverse layout in size, thereby obtaining a reduced layout, obtaining a dummy pattern layout having an outline identical to an outline of the reduced layout and a given line width such that the dummy pattern layout is self-assembled to the circuit layout, and transferring the self-aligned or self-assembled dummy pattern layout and circuit layout to a semiconductor substrate.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: August 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae In Moon
  • Patent number: 8241823
    Abstract: Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: August 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Shinn-Sheng Yu, Anthony Yen, Shao-Ming Yu, Chang-Yun Chang, Jeff J. Xu, Clement Hsingjen Wann
  • Patent number: 8243222
    Abstract: A method of manufacturing an array substrate for a liquid crystal display device includes forming a gate electrode and a gate line on a substrate through a first mask process, forming a first insulating layer, an active layer, an ohmic contact layer, a buffer metallic layer, and a data line on the substrate including the gate electrode and the gate line through a second mask process, and forming a source electrode, a drain electrode, and a pixel electrode through a third mask process, the pixel electrode extending from the drain electrode, wherein the active layer is disposed over and within the gate electrode.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: August 14, 2012
    Assignee: LG Display Co., Ltd.
    Inventors: Chang-Bin Lee, Byung-Kook Choi
  • Patent number: 8239788
    Abstract: A method includes receiving an integrated circuit chip size and determining a frame structure segment size based on the chip size. The frame structure segment size is less than the chip size. An initial shot layout having a chip count is established in which a number of shots, each including at least one frame structure segment and at least one chip, are arranged in vertically and horizontally aligned columns and rows. At least one additional shot layout is established in which at least one of a row or column of shots is offset from an adjacent row or column of shots. The initial shot layout is compared to the at least one additional shot layout, and a final shot layout is selected based in part on the total number of shots in the shot layout and has a final chip count that is greater than or equal to the initial chip count.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: August 7, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Lin, Yung-Cheng Chen, Heng-Jen Lee
  • Patent number: 8236467
    Abstract: An exposure method comprises: forming an immersion region on a substrate; exposing the substrate by irradiating the substrate with an exposure light via a liquid of the immersion region; and preventing an integration value of a contact time during which the liquid of the immersion region and a first region on the substrate are in contact, from exceeding a predetermined tolerance value.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: August 7, 2012
    Assignee: Nikon Corporation
    Inventors: Kenichi Shiraishi, Tomoharu Fujiwara
  • Patent number: 8239789
    Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Timothy A. Brunner, Stephen E. Greco, Bernhard R. Liegl, Hua Xiang
  • Patent number: 8234602
    Abstract: A semiconductor-device manufacturing method includes steps of performing a sidewall fabrication thereby forming a first pattern structure; measuring an amount of displacement of line portions of the first pattern structure; correcting an overlay specification for an overlay of the first pattern structure and a second pattern structure dynamically based on the amount of displacement; and determining whether an error in the overlay of the first pattern structure and the second pattern structure meets the corrected overlay specification.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: July 31, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuji Kobayashi
  • Patent number: 8231285
    Abstract: A resist pattern forming method using a coating and developing apparatus and an aligner being connected thereto which are controlled to form a resist film on a surface of a substrate with a base film and a base pattern formed thereon, followed by inspecting at least one of a plurality of measurement items selected from: reflection ratio and film thickness of the base film and the resist film, line width after a development, an accuracy that the base pattern matches with a resist pattern, a defect on the surface after the development, etc. A parameter subject to amendment is selected based on corresponding data of each measurement item, such as the film thickness of the resist and the line width after the development, and amendment of the parameter is performed. This results in a reduced workload of an operator, and the appropriate amendment can be performed.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: July 31, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Kunie Ogata, Koki Nishimuko, Hiroshi Tomita, Yoshio Kimura, Ryouichi Uemura, Michio Tanaka
  • Patent number: 8233159
    Abstract: An image forming device includes a sheet carrying body carrying a sheet thereon in a predetermined direction, a pattern selecting unit selecting one of a plurality of patterns that includes a first pattern and a second pattern, the first pattern including a plurality of marks aligned at intervals of a predetermined distance within a first range, the second pattern including a plurality of marks aligned at intervals of a predetermined distance within a second range shorter than the first range, a forming unit configured to form the selected pattern on the sheet carrying body and form an image on the sheet being carried on the sheet carrying body, a deviation determining unit determining a positional deviation of the image based upon the pattern formed, and a correcting unit performing positional deviation correction for the image to be formed on the sheet based upon the positional deviation determined.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: July 31, 2012
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Takashi Ohmiya
  • Patent number: 8234600
    Abstract: A computer readable storage medium stores a program for generating reticle data for producing a reticle used in an exposure apparatus, the program including the steps of classifying target patterns to be formed on a substrate into a plurality of direction groups, extracting, for each of the plurality of direction groups, a region suited to resolution of a target pattern belonging to the direction group from an effective light source distribution formed on a pupil of a projection optical system by an illumination optical system, thereby determining the extracted region as a partial light source, executing, for each of a plurality of partial light sources determined in the step of extracting a region, processing of determining a pattern to be placed on a reticle when each partial light source is used as an illumination condition, and merging patterns determined in the step of executing processing.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: July 31, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Miyoko Kawashima