Including Control Feature Responsive To A Test Or Measurement Patents (Class 430/30)
  • Patent number: 10120973
    Abstract: There are provided system and method of performing metrology operations related to a specimen.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: November 6, 2018
    Assignee: APPLIED MATERIALS ISRAEL LTD.
    Inventors: Ron Katzir, Imry Kissos, Lavi Jacov Shachar, Amit Batikoff, Shaul Cohen, Noam Zac
  • Patent number: 10114290
    Abstract: A parameter acquiring method for dose correction of a charged particle beam includes writing evaluation patterns on a substrate coated with resist; writing, while varying writing condition, a peripheral pattern on a periphery of any different one of the evaluation patterns, after an ignorable time as to influence of resist temperature increase due to writing of an evaluation pattern concerned has passed; and calculating a parameter for defining correlation among a width dimension change amount of the evaluation pattern concerned, a temperature increase amount of the evaluation pattern concerned, and a backscatter dose reaching the evaluation pattern concerned, by using, under each writing condition, a width dimension of the evaluation pattern concerned, the temperature increase amount of the evaluation pattern concerned at each shot time, and the backscatter dose reaching the evaluation pattern concerned from each shot.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: October 30, 2018
    Assignee: NuFlare Technology, Inc.
    Inventor: Haruyuki Nomura
  • Patent number: 10109046
    Abstract: Systems for and methods of detecting faults in semiconductor wafers are provided. One method includes, for instance: monitoring, with at least one sensor, a recipe for manufacturing a semiconductor wafer; tracking, with a fault detection system, a set of steps for the recipe; determining a start of a step; sensing a set of data related to at least one parameter of the step; generating, by an imaging system, an image of the set of data; displaying, on a display, the image of the set of data; calculating, by the fault detection system, a pixel area ratio from the image of the set of data; determining if a fault exists in the wafer based upon the pixel area ratio; and displaying, on the display, an indication of the fault during real-time and at an end of the step.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Robert Boyd Finlay, Yunsheng Song
  • Patent number: 10101674
    Abstract: Disclosed are apparatus and methods for determining optimal focus for a photolithography system. A plurality of optical signals are acquired from a particular target located in a plurality of fields on a semiconductor wafer, and the fields were formed using different process parameters, including different focus values. A feature is extracted from the optical signals related to changes in focus. A curve is fitted to the extracted feature of the optical signals as a function of focus. An extreme point in the curve is determined and reported as an optimal focus for use in the photolithography system.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: October 16, 2018
    Assignee: KLA-Tencor Corporation
    Inventor: Stilian Ivanov Pandev
  • Patent number: 10095116
    Abstract: Systems and methods are disclosed herein for enhancing lithography printability, and in particular, for enhancing image contrast. An exemplary method includes receiving an integrated circuit (IC) design layout and generating an exposure map based on the IC design layout. The IC design layout includes a target pattern to be formed on a workpiece, and the exposure map includes an exposure grid divided into dark pixels and bright pixels that combine to form the target pattern. The method further includes adjusting the exposure map to increase exposure dosage at edges of the target pattern. In some implementations, the adjusting includes locating an edge portion of the target pattern in the exposure map, where the edge portion has a corresponding bright pixel, and assigning exposure energy from at least one dark pixel to the corresponding bright pixel, thereby generating a modified exposure map.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: October 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Ming Chang, Wen Lo
  • Patent number: 10083270
    Abstract: Target optimization methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an IC design layout for a target pattern, wherein the target pattern has a corresponding target contour; modifying the target pattern, wherein the modified target pattern has a corresponding modified target contour; and generating an optimized target pattern when the modified target contour achieves functionality of the target pattern as defined by a constraint layer. The method can further include defining a cost function based on the constraint layer, where the cost function correlates a spatial relationship between a contour of the target pattern and the constraint layer.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Ming Chang, Ken-Hsien Hsieh, Shuo-Yen Chou, Ru-Gun Liu
  • Patent number: 10054862
    Abstract: Disclosed is a method of monitoring a focus parameter during a lithographic process. The method comprises acquiring first and second measurements of, respectively first and second targets, wherein the first and second targets have been exposed with a relative best focus offset. The method then comprises determining the focus parameter from first and second measurements. Also disclosed are corresponding measurement and lithographic apparatuses, a computer program and a method of manufacturing devices.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: August 21, 2018
    Assignee: ASML Netherlands B.V.
    Inventors: Anton Bernhard Van Oosten, Paul Christiaan Hinnen, Robertus Cornelis Martinus De Kruif, Robert John Socha
  • Patent number: 10048595
    Abstract: A method of controlling a manufacturing process, the method including the steps of a) providing a testing area with a periodic structure, where the periodic structure includes a series of sets of patterned features, b) illuminating the periodic structure with a light, thereby producing a non-zero order diffraction signal, c) collecting the diffraction signal to produce a test signature, d) matching the test signature with a reference signature, where the reference signature was previously produced by performing steps a), b), and c) with respect to a reference structure that is at least similar to the periodic structure, and e) controlling a manufacturing process using a control setting set associated with the matching reference signature.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: August 14, 2018
    Assignee: NOVA MEASURING INSTRUMENTS LTD.
    Inventor: Boaz Brill
  • Patent number: 10042261
    Abstract: In one embodiment, a method of aperture alignment for a multi charged particle beam writing apparatus includes irradiating a shaping aperture member with a charged particle beam while changing an incident direction, detecting a current for each of the incident directions of the charged particle beam, producing a current distribution map based on the incident direction and the current, and moving the shaping aperture member or a blanking aperture member based on the current distribution map to align the shaping aperture member with the blanking aperture member.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: August 7, 2018
    Assignee: NuFlare Technology, Inc.
    Inventor: Tsubasa Nanao
  • Patent number: 10043719
    Abstract: A semiconductor-wafer evaluation method includes: before the mirror-polishing step, measuring warp data of displacement of the surface of the semiconductor wafer with a capacitive shape measurement device; setting a prescribed width of an outer circumferential portion of the semiconductor wafer as a sampling range; performing fitting of the warp data within the sampling range with a fitting function in a predetermined fitting range; calculating a difference (Range) between a maximum and a minimum of the warp data after the fitting within the sampling range; and, after the mirror-polishing step, evaluating the nanotopography of the surface of the semiconductor wafer on the basis of the calculated difference (Range).
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: August 7, 2018
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Yuichi Shimizu
  • Patent number: 10032609
    Abstract: Plasma applications are disclosed that operate with helium or argon at atmospheric pressure, and at low temperatures, and with high concentrations of reactive species in the effluent stream. Laminar gas flow is developed prior to forming the plasma and at least one of the electrodes is heated which enables operation at conditions where the helium plasma would otherwise be unstable and either extinguish, or transition into an arc. The techniques can be employed to remove organic materials from a substrate, thereby cleaning the substrate; activate the surfaces of materials thereby enhancing adhesion between the material and an adhesive; kill microorganisms on a surface, thereby sterilizing the substrate; etches thin films of materials from a substrate, and deposit thin films and coatings onto a substrate.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: July 24, 2018
    Assignee: Surfx Technologies LLC
    Inventors: Siu Fai Cheng, Thomas Scott Williams, Toby Desmond Oste, Sarkis Minas Keshishian, Robert F. Hicks
  • Patent number: 10025201
    Abstract: A method to improve a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus having an illumination system and projection optics, the method including: obtaining an illumination source shape and a mask defocus value; optimizing a dose of the lithographic process; and optimizing the portion of the design layout for each of a plurality of slit positions of the illumination source.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: July 17, 2018
    Assignee: ASML Netherlands B.V.
    Inventors: Duan-Fu Stephen Hsu, Rafael C. Howell, Xiaofeng Liu
  • Patent number: 10025885
    Abstract: Methods according to the present invention provide computationally efficient techniques for designing gauge patterns for calibrating a model for use in a simulation process. More specifically, the present invention relates to methods of designing gauge patterns that achieve complete coverage of parameter variations with minimum number of gauges and corresponding measurements in the calibration of a lithographic process utilized to image a target design having a plurality of features. According to some aspects, a method according to the invention includes transforming the space of model parametric space (based on CD sensitivity or Delta TCCs), then iteratively identifying the direction that is most orthogonal to existing gauges' CD sensitivities in this new space, and determining most sensitive line width/pitch combination with optimal assist feature placement which leads to most sensitive CD changes along that direction in model parametric space.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: July 17, 2018
    Assignee: ASML Netherlands B.V.
    Inventors: Jun Ye, Yu Cao, Hanying Feng, Wenjin Shao
  • Patent number: 10018571
    Abstract: A defect inspection system includes an inspection sub-system and a controller communicatively coupled to the detector. The inspection sub-system includes an illumination source configured to generate a beam of illumination, a set of illumination optics to direct the beam of illumination to a sample, and a detector configured to collect illumination emanating from the sample. The controller includes a memory device and one or more processors configured to execute program instructions. The controller is configured to determine one or more target patterns corresponding to one or more features on the sample, define one or more care areas on the sample based on the one or more target patterns and design data of the sample stored within the memory device of the controller, and identify one or more defects within the one or more care areas of the sample based on the illumination collected by the detector.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: July 10, 2018
    Assignee: KLA-Tencor Corporation
    Inventors: Vijayakumar Ramachandran, Ravikumar Sanapala, Vidyasagar Anantha, Philip Measor, Rajesh Manepalli, Jing Fang
  • Patent number: 10007185
    Abstract: Disclosed is an electron beam lithography method. The method comprises obtaining a target pattern having a first width to be formed on a substrate, acquiring a dose pattern including a fixed dose cell which corresponds to a region of the dose pattern with a constant dose amount of electron beam to be provided onto the substrate and a variable dose cell which corresponds to a region of the dose pattern with a variable dose amount which is varied based on the first width of the target pattern, and providing the electron beam to expose the substrate according to the dose pattern.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: June 26, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sook Hyun Lee, Jin Choi, Sinjeung Park, Seombeom Kim, Inkyun Shin
  • Patent number: 9989843
    Abstract: Aspects of the present invention relate to a test photomask and a method for evaluating critical dimension changes in the test photomask. Various embodiments include a test photomask. The test photomask includes a plurality of cells having a varied density pattern. The plurality of cells include a first group of cells arranged along a first line, the first group of cells having a first combined density ratio. The plurality of cells also include a second group of cells arranged along a second line, the second group of cells having a second combined density ratio. In the plurality of cells, the second combined density ratio for the second group of cells is equal to the first combined density ratio of the first group of cells. The varied density pattern is configured to substantially neutralize fogging effects.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: June 5, 2018
    Assignees: International Business Machines Corporation, Toppan Printing Co., Ltd.
    Inventors: Brian N. Caldwell, Yuki Fujita, Raymond W. Jeffer, James P. Levin, Joseph L. Malenfant, Jr., Steven C. Nash
  • Patent number: 9989842
    Abstract: Provided is a method of generating test patterns. The method includes generating a first polygon, disposing the first polygon in a pattern region, selecting one region from peripheral regions of the first polygon, generating a second polygon, disposing the second polygon in the selected region, and repeating the above processes.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: June 5, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeeeun Jung, Jeonghoon Lee
  • Patent number: 9977344
    Abstract: Disclosed is a substrate comprising a combined target for measurement of overlay and focus. The target comprises: a first layer comprising a first periodic structure; and a second layer comprising a second periodic structure overlaying the first periodic structure. The target has structural asymmetry which comprises a structural asymmetry component resultant from unintentional mismatch between the first periodic structure and the second periodic structure, a structural asymmetry component resultant from an intentional positional offset between the first periodic structure and the second periodic structure and a focus dependent structural asymmetry component which is dependent upon a focus setting during exposure of said combined target on said substrate. Also disclosed is a method for forming such a target, and associated lithographic and metrology apparatuses.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: May 22, 2018
    Assignee: ASML Netherlands B.V.
    Inventors: Wim Tjibbo Tel, Frank Staals
  • Patent number: 9964866
    Abstract: A method of forming an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure field includes a target portion and a set of alignment marks. Measure the set of alignment marks of each exposure field by a measuring system to obtain alignment data for the respective exposure field. Determine an exposure parameter corresponding to each exposure field and an exposure location on the target portion from the alignment data for the respective exposure field by a calculating system. Feedback the alignment data to a next substrate.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: May 8, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Che-Yi Lin, En-Chiuan Liou, Chia-Hsun Tseng, Yi-Ting Chen, Chia-Hung Wang, Yi-Jing Wang
  • Patent number: 9964853
    Abstract: A method of determining exposure dose of a lithographic apparatus used in a lithographic process on a substrate. Using the lithographic process to produce a first structure on the substrate, the first structure having a dose-sensitive feature which has a form that depends on exposure dose of the lithographic apparatus on the substrate. Using the lithographic process to produce a second structure on the substrate, the second structure having a dose-sensitive feature which has a form that depends on the exposure dose of the lithographic apparatus but which has a different sensitivity to the exposure dose than the first structure. Detecting scattered radiation while illuminating the first and second structures with radiation to obtain first and second scatterometer signals. Using the first and second scatterometer signals to determine an exposure dose value used to produce at least one of the first and second structures.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: May 8, 2018
    Assignee: ASML Netherlands B.V.
    Inventors: Peter Clement Paul Vanoppen, Eric Jos Anton Brouwer, Hugo Augustinus Joseph Cramer, Jan Hendrik Den Besten, Adrianus Franciscus Petrus Engelen, Paul Christiaan Hinnen
  • Patent number: 9934346
    Abstract: Disclosed herein is a computer-implemented method for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus, the method comprising defining a multi-variable cost function, the multi-variable cost function being a function of a stochastic effect of the lithographic process.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: April 3, 2018
    Assignee: ASML NETHERLANDS B.V.
    Inventor: Steven George Hansen
  • Patent number: 9927720
    Abstract: A substrate can include a feature pattern included in an integrated circuit on the substrate and an in-situ metrology pattern spaced apart from the feature pattern on the substrate, the in-situ metrology pattern and the feature pattern both configured to have equal heights relative to a surface of the substrate.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: March 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-myung Kim, Gyu-min Jeong, Tae-hwa Jeong, Kwang-sub Yoon
  • Patent number: 9915878
    Abstract: An exposure apparatus transfers a pattern on a wafer by irradiating a reticle with an illumination light, and the pattern is formed on a pattern surface of the reticle. The exposure apparatus is provided with a reticle stage that moves holding the reticle, and a sensor that irradiates a measurement light on the pattern surface of the reticle held by the reticle stage and detects speckles from the pattern.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: March 13, 2018
    Assignee: NIKON CORPORATION
    Inventor: Yuichi Shibazaki
  • Patent number: 9904993
    Abstract: A system and method are presented for use in inspection of patterned structures. The system comprises: data input utility for receiving first type of data indicative of image data on at least a part of the patterned structure, and data processing and analyzing utility configured and operable for analyzing the image data, and determining a geometrical model for at least one feature of a pattern in said structure, and using said geometrical model for determining an optical model for second type of data indicative of optical measurements on a patterned structure.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: February 27, 2018
    Assignee: NOVA MEASURING INSTRUMENTS LTD.
    Inventor: Boaz Brill
  • Patent number: 9891525
    Abstract: This exposure method comprises a first step of performing the exposure processing by irradiating a projection optical system (the system) by a first pupil plane illumination distribution (the first distribution) of the system; a second step of performing the exposure processing by irradiating the system by a second pupil plane illumination distribution (the second distribution) that is different from the first distribution, after the first step; a change amount obtaining step of obtaining a change amount of an imaging performance of the system in a condition of the second distribution, with respect to the imaging performance in the first step; and a correction amount obtaining step of obtaining a correction amount for correcting the imaging performance in the second step, by using the change amount, wherein, in the second step, the exposure processing is performed by correcting the imaging performance using the correction amount.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: February 13, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Nobuhiko Yabu
  • Patent number: 9892500
    Abstract: A method for measuring a critical dimension of a mask pattern, including generating a mask pattern using an optically proximity-corrected (OPC) mask design including at least one block; measuring a first critical dimension of a target-region of interest (target-ROI) including neighboring blocks having a same critical dimension (CD), in the mask pattern; determining a group region of interest including the target-ROI and at least one neighboring block adjacent to the target-ROI; measuring second CDs of the neighboring blocks of the group region of interest; and correcting a measuring value of the first CD using a measuring value of the second CDs.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: February 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyung-Joo Lee, Won-Joo Park, Seuk-Hwan Choi, Byung-Gook Kim, Dong-Hoon Chung
  • Patent number: 9891528
    Abstract: A method of lithography patterning includes forming a resist layer over a substrate and providing a radiation with a first exposure dose to define an opening to be formed in the resist layer. The opening is to have a target critical dimension CD1 after developed by a negativ-tone development (NTD) process. The method further includes exposing the resist layer to the radiation with a second exposure dose less than the first exposure dose and developing the resist layer in a negative-tone development process to remove unexposed portions of the resist layer, resulting in an opening between resist patterns. A critical dimension CD2 of the opening is greater than CD1 by a delta. The method further includes forming an interfacial layer on sidewalls of the resist patterns. The interfacial layer has a thickness that is substantially equal to half of the delta.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Yu Liu, Ching-Yu Chang
  • Patent number: 9870443
    Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
  • Patent number: 9869849
    Abstract: A projection optical system is constituted by, in order from the reduction side, a first optical system constituted by a plurality of lenses for forming an image displayed by image display elements as an intermediate image, and a second optical system constituted by a plurality of lenses for forming the intermediate image on a magnification side conjugate plane. Conditional Formula (1) below is satisfied. 8.20<Im?·f2/f2<20.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: January 16, 2018
    Assignee: FUJIFILM Corporation
    Inventor: Masaru Amano
  • Patent number: 9846368
    Abstract: An apparatus and method are used to form patterns on a substrate. The apparatus comprises a projection system, a patterning device, a low-pass filter, and a data manipulation device. The projection system projects a beam of radiation onto the substrate as an array of sub-beams. The patterning device modulates the sub-beams to substantially produce a requested dose pattern on the substrate. The low-pass filter operates on pattern data derived from the requested dose pattern in order to form a frequency-clipped target dose pattern that comprises only spatial frequency components below a selected threshold frequency. The data manipulation device produces a control signal comprising spot exposure intensities to be produced by the patterning device, based on a direct algebraic least-squares fit of the spot exposure intensities to the frequency-clipped target dose pattern. In various examples, filters can also be used.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: December 19, 2017
    Assignee: ASML Netherlands B.V.
    Inventors: Patricius Aloysius Jacobus Tinnemans, Johannes Jacobus Matheus Baselmans
  • Patent number: 9842185
    Abstract: Methods and apparatuses for configuring group constraints of features of cells for a multi-patterning process are provided. The apparatus determines features within a circuit layout, distance constraints for at least one of the features, group constraints for the features based on the distance constraints, the group constraints defining limits on groups assignable to each of the features. In addition, the apparatus receives an integrated circuit layout including a plurality of abutting cells. The apparatus then determines whether group constraints of a second cell conflict with group constraints of a first cell, the second cell abutting with the first cell, and configures a subset of the group constraints of the second cell based on the group constraints of the first cell and based on the group constraints of the second cell that conflict with the group constraints of the first cell.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: December 12, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Lionel Riviere-Cazaux
  • Patent number: 9798241
    Abstract: A method of patterning a photoresist layer includes forming a photoresist layer on a substrate, exposing the photoresist layer to light using a first light source so as to induce a chemical change in the photoresist layer, performing a post-exposure bake process on the photoresist layer, the post-exposure bake process including irradiating the photoresist layer with at least two shots of laser light from a second light source such that the photoresist layer is heated to a first temperature, and performing a developing process on the photoresist layer after the post-exposure bake process, the development process selectively removing a portion of the photoresist layer.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: October 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Hyun Kim, Dong-Gun Lee, Byoung-Hun Park, Byung-Gook Kim, Chan-Uk Jeon
  • Patent number: 9797828
    Abstract: The present invention discloses a method for measuring the concentration of a photoresist in a stripping liquid. In the method for measuring the concentration of a photoresist in a stripping liquid, a plurality of standard photoresist samples are prepared at first, then the spectrum of the standard photoresist samples and the spectrum of the test photoresist sample are collected, and the nth derivative of the spectrum of the standard photoresist samples and the spectrum of the test photoresist sample are taken, wherein n is an integer equal to or greater than 1, a standard curve based on the nth derivative curves and calculating the concentration of the test photoresist sample is established, the concentration of a photoresist in a stripping liquid can be measured accurately according to the standard curve.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: October 24, 2017
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD
    Inventor: Li Wang
  • Patent number: 9798248
    Abstract: The invention relates to a method for producing a structure in a lithographic material, wherein the structure in the lithographic material is defined by means of a writing beam of an exposure device, in that a plurality of partial structures are written sequentially, wherein for writing the partial structures a write field of the exposure device is displaced and positioned sequentially and that a partial structure is written in the write field in each case, and wherein for positioning of the write field a reference structure is detected by means of an imaging measuring device.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: October 24, 2017
    Assignee: Nanoscribe GmbH
    Inventors: Joerg Hoffmann, Philipp Simon, Michael Thiel, Martin Hermatschweiler, Holger Fischer
  • Patent number: 9798252
    Abstract: According to measurement results of an encoder system, a stage driving system that is a magnetic levitation type planar motor is controlled to drive and control a wafer stage, and in the case where an abnormality of the driving and control of the wafer stage has been detected, the stage driving system is controlled to apply a thrust in a vertical direction to the wafer stage. With this operation, the pitching of the wafer stage can be avoided, which makes it possible to prevent damage of the wafer stage and structures placed immediately above the stage upper surface.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: October 24, 2017
    Assignee: NIKON CORPORATION
    Inventor: Tomoki Miyakawa
  • Patent number: 9760017
    Abstract: According to one embodiment, wafer lithography equipment includes an exposure unit transferring a circuit pattern onto a wafer, a measurement unit measuring a dimension of the circuit pattern and a calculator. The calculator includes calculating a first difference. The first difference is the difference between a first dimension and a second dimension. The first dimension is obtained by substituting a first exposure amount and a first focus distance into an approximate response surface function. The second dimension is measured by the measurement unit. The calculator also includes calculating a second difference. The second difference is the sum total of the first difference for all of the circuit patterns. The calculator also includes calculating a second exposure amount and a second focus distance causing the difference between the approximate response surface function and the second difference to be a minimum. The calculator also includes calculating a correction exposure amount.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: September 12, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazufumi Shiozawa, Toshihide Kawachi, Masamichi Kishimoto, Nobuhiro Komine, Yoshimitsu Kato
  • Patent number: 9748110
    Abstract: Provided is a method for increasing pattern density of a structure on a substrate using an integration scheme, the method comprising: providing a substrate having a first spacer pattern and an underlying layer, the underlying layer comprising a first underlying layer, a second underlying layer, and a target layer; performing a conformal spacer deposition using an oxide, the deposition creating a conformal layer; performing a spacer RIE process and a pull process, thereby generating a second spacer pattern, the spacer RIE process includes adsorption of N-containing gas on a surface of the substrate which activates the surface to react with an F- and/or an H-containing gas to form fluorosilicates; and wherein the integration targets include selectively etching spacer films within a target spacer etch rate, enhanced simultaneous selectivity to the first underlying layer and the second underlying layer and preventing pattern damage.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: August 29, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Subhadeep Kal, Angelique D. Raley, Nihar Mohanty, Aelan Mosden
  • Patent number: 9740814
    Abstract: A method, system, and computer program product for triple patterning technology (TPT) violation detection and visualization within an integrated circuit design layout are disclosed. In a first aspect, the method comprises mapping a plurality of violations of the integrated circuit design layout to a graph, generating a color graph corresponding to the graph, detecting at least one TPT violation from the color graph; and visualizing the at least one TPT violation on a layout canvas. In a second aspect, the system comprises a graph generator module for mapping a plurality of violations of the integrated circuit design layout to a graph and to generate a color graph corresponding to the graph, a detector module for detecting at least one TPT violation from the color graph, and a visualizer module for visualizing the at least one TPT violation on a layout canvas.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: August 22, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventor: Sanjib Ghosh
  • Patent number: 9710903
    Abstract: Various systems and methods for detecting design and process defects on a wafer, reviewing defects on a wafer, selecting one or more features within a design for use as process monitoring features, or some combination thereof are provided. One system is configured to detect design defects and process defects at locations on a wafer at which images are acquired by an electron beam review subsystem based on defects in a design, additional defects in the design, which are detected by comparing an image of a die in the design printed on the wafer acquired by the electron beam review subsystem to an image of the die stored in a database, and defects detected on the wafer by a wafer inspection system.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: July 18, 2017
    Assignee: KLA-Tencor Corp.
    Inventors: Christophe Fouquet, Zain Saidin, Sergio Edelstein, Savitha Nanjangud, Carl Hess
  • Patent number: 9709510
    Abstract: Methods and systems for determining a configuration for an optical element positioned in a collection aperture during wafer inspection are provided. One system includes a detector configured to detect light from a wafer that passes through an optical element, which includes a set of collection apertures, when the optical element has different configurations thereby generating different images for the different configurations. The system also includes a computer subsystem configured for constructing additional image(s) from two or more of the different images, and the two or more different images used to generate any one of the additional image(s) do not include only different images generated for single collection apertures in the set. The computer subsystem is further configured for selecting one of the different or additional configurations for the optical element based on the different images and the additional image(s).
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: July 18, 2017
    Assignee: KLA-Tencor Corp.
    Inventors: Pavel Kolchin, Mikhail Haurylau, Junwei Wei, Dan Kapp, Robert Danen, Grace Chen
  • Patent number: 9690898
    Abstract: Candidate layout patterns can be generated using a generative model trained based on known data, such as historical hot spot data, features extraction, and geometrical primitives. The generative model can be sampled to obtain candidate layouts that can be ranked and repaired using error optimization, design rule checking, optical proximity checking, and other methods to ensure that resulting candidates are manufacturable.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: June 27, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ioana C. Graur, Ian P. Stobert, Dmitry A. Vengertsev
  • Patent number: 9685378
    Abstract: Disclosed herein is a method of dividing rectangular plate-shaped workpieces into individual device chips including a detecting step wherein an annular frame to which a plurality of rectangular plate-shaped workpieces are stuck is held on a chuck table and the positions and angles of the projected dicing lines on each of the plate-shaped workpieces are detected, and a dividing step wherein a laser beam having a wavelength which is absorbable by the plate-shaped workpieces is applied from a laser beam applying unit to the plate-shaped workpieces while the chuck table and the laser beam applying unit are being relatively processing-fed and finely adjusted for each of the plate-shaped workpieces on the basis of the positions and angles detected in the detecting step, thereby dividing the plate-shaped workpieces into a plurality of device chips along the projected dicing lines.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: June 20, 2017
    Assignee: Disco Corporation
    Inventors: Toshiyuki Yoshikawa, Takashi Sampei
  • Patent number: 9678442
    Abstract: An analysis system that includes a processor and an memory module; wherein the memory module is arranged to store aerial images of an area of a mask, each aerial image corresponds to focus value out of a set of different focus values; wherein the processor is arranged to find weak points by processing the aerial images using different printability thresholds; and wherein the processor is arranged to determine focus and exposure values for generating a Process Window Qualification (PWQ) wafer to be manufactured using the mask in response to focus and exposure values associated with the weak points.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: June 13, 2017
    Assignee: APPLIED MATERIALS ISRAEL LTD.
    Inventors: Aviram Tam, Lei Zhong
  • Patent number: 9651872
    Abstract: A projection lens for imaging a pattern arranged in an object plane of the projection lens into an image plane of the projection lens via electromagnetic radiation having an operating wavelength ?<260 nm has a multiplicity of optical elements having optical surfaces which are arranged in a projection beam path between the object plane and the image plane. Provision is made of a wavefront manipulation system for dynamically influencing the wavefront of the projection radiation passing from the object plane to the image plane.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: May 16, 2017
    Assignee: Carl Zeiss SMT GmbH
    Inventor: Heiko Feldmann
  • Patent number: 9625692
    Abstract: Disclosed is a projection optical system including a first optical system configured to form a first image conjugate to an object and have an optical axis and a second optical system configured to project a second image conjugate to the first image onto a surface to be projected on, wherein the first image satisfies a condition of: Im×Tr?1.70 wherein Im denotes a length of the first image in a direction of an optical axis of the first optical system, normalized by a focal length of the first optical system, and Tr denotes a throw ratio for the projection optical system.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: April 18, 2017
    Assignee: Ricoh Company, Ltd.
    Inventors: Tatsuya Takahashi, Kazuhiro Fujita, Issei Abe
  • Patent number: 9606452
    Abstract: A lithography metrology method is provided. Focus sensitivity data and dose sensitivity data of sample patterns to be formed on a substrate are acquired. At least one focus pattern selected in descending order of focus sensitivity from among the acquired focus sensitivity data of the sample patterns is determined. At least one low-sensitivity focus pattern in ascending order of the focus sensitivity from among the acquired dose sensitivity data of the sample patterns is selected, and at least one dose pattern selected in descending order of dose sensitivity from among the at least one low-sensitivity focus pattern is determined. A split substrate having a plurality of chip regions is prepared. A plurality of focus split patterns having a shape corresponding to the at least one focus pattern and a plurality of dose split patterns having a shape corresponding to the at least one dose pattern in the plurality of chip regions are formed.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: March 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Je Jung, Yong-Jin Chun, Byoung-Il Choi
  • Patent number: 9607808
    Abstract: A method of electron-beam lithography by direct writing solves the reliability of design of etched components through rounding of the corners of contiguous patterns, notably in patterns to be etched of critical dimension of the order of 35 nm. The method determines critical patterns, and correction patterns by subtracting patterns of corrections of dimensions and of locations as a function of rounding of external or internal corners to be corrected and etching of the corrected design. The corrections may be by a correction model taking account of the parameters of the critical patterns. A correction of the proximity effects specific to these methods is also performed, by resizing of edges of blocks to be etched in combination optimized by the energy latitude with a modulation of the radiated doses. A rescaling and negation functions and eRIF functions may be used to optimize the parameters and the realization of the extrusion.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: March 28, 2017
    Assignee: Commissariat A L'Energie Atomique ET AUX Energies Alternatives
    Inventor: Serdar Manakli
  • Patent number: 9594866
    Abstract: A method includes receiving layout data representing a plurality of patterns. The layout data includes a plurality of layers and spaces identified between adjacent patterns. In at least one layer of the plurality of layers, the adjacent patterns violate a G0-rule. The method further includes determining whether each identified space is a critical G0-space. The identified space is determined to be a critical G0-space if a portion of at least one adjacent pattern that is removed merges two adjacent odd-loops of G0-spaces into a single even loop or G0 spaces or alternatively, if a portion of an adjacent pattern that is removed converts one odd-loop of G0-spaces to a non-loop of G0-spaces. The method further includes receiving a modification of at least one adjacent pattern and updating a spacing of a layer that is adjacent to the layers within the adjacent pattern that violate the G0-rule.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: March 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Dio Wang, Ken-Hsien Hsieh, Huang-Yu Chen, Li-Chun Tien, Ru-Gun Liu, Lee-Chung Lu
  • Patent number: 9594311
    Abstract: The present invention makes the use of measurement of a diffraction spectrum in or near an image plane in order to determine a property of an exposed substrate. In particular, the positive and negative first diffraction orders are separated or diverged, detected and their intensity measured. The intensity of each of the first diffraction orders from the diffraction spectrum are compared to determine overlay (or other properties) of exposed layers on the substrate.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: March 14, 2017
    Assignee: ASML Netherlands B.V.
    Inventors: Marcus Adrianus Van De Kerkhof, Maurits Van Der Schaar, Andreas Fuchs, Martyn John Coogans
  • Patent number: 9594310
    Abstract: The present invention makes the use of measurement of a diffraction spectrum in or near an image plane in order to determine a property of an exposed substrate. In particular, the positive and negative first diffraction orders are separated or diverged, detected and their intensity measured. The intensity of each of the first diffraction orders from the diffraction spectrum are compared to determine overlay (or other properties) of exposed layers on the substrate.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: March 14, 2017
    Assignee: ASML Netherlands B.V.
    Inventors: Marcus Adrianus Van De Kerkhof, Maurits Van Der Schaar, Andreas Fuchs, Martyn John Coogans