Abstract: The present disclosure describes methods of forming a mask. In an example, the method includes receiving an integrated circuit (IC) design layout, modifying the IC design layout data using an optical proximity correction (OPC) process, thereby providing an OPCed IC design layout, and modifying the OPCed IC design layout data using a mask rule check (MRC) process, wherein the MRC process corrects rule violations of the OPCed IC design layout data using a mask error enhancement factor (MEEF) index, thereby providing a MRC/OPCed IC design layout.

Abstract: A method comprises: selecting a circuit pattern or network of circuit patterns in a layout of an integrated circuit (IC) to be fabricating using double patterning technology (DPT). Circuit patterns near the selected circuit pattern or network are grouped into one or more groups. For each group, a respective expected resistance-capacitance (RC) extraction error cost is calculated, which is associated with a mask alignment error, for two different sets of mask assignments. The circuit patterns in the one or more groups are assigned to be patterned by respective photomasks, so as to minimize a total of the expected RC extraction error costs.

Abstract: After a cassette is mounted on a cassette mounting part, a control unit instructs a substrate treatment apparatus to start treatment on substrates in the cassette. Thereafter, the control unit indicates, to the substrate treatment apparatus, a cassette on the cassette mounting part to which a substrate is transferred at completion of the treatment. If the transfer destination cassette for the substrate at the completion of treatment has not been indicated when a number of remaining treatment steps for the substrate reaches a predetermined set number, an alarm is given from the substrate treatment apparatus. This alarm is sent from the substrate treatment apparatus to the control unit, and the control unit indicates a transfer destination cassette for the substrate.

Abstract: The invention provides a phase shift focus monitor reticle, a manufacturing method thereof, and a method of monitoring focus difference using the phase shift focus monitor reticle. The phase shift focus monitor reticle comprises a shield comprising a plurality of light-transmitting portions with a certain width; and a glass layer positioned on the shield layer comprising a plurality of openings at the light-transmitting portions; wherein the width of the openings is half of the width of the light-transmitting portions; the depth of the openings is n*?/(N?1), wherein ? is the wavelength of the lights incident on the phase shift focus monitor reticle in air, N is the refractive index of the glass layer, n is a positive integer. The invention can be applied to thicker photoresist and different process machines.

Abstract: An inspection method for inspecting a device mounted on a substrate, includes generating a shape template of the device, acquiring height information of each pixel by projecting grating pattern light onto the substrate through a projecting section, generating a contrast map corresponding to the height information of each pixel, and comparing the contrast map with the shape template. Thus, a measurement object may be exactly extracted.

Abstract: A method of fabricating a semiconductor device is disclosed. The exemplary method includes providing a substrate including a device layer and a sacrificial layer formed over the device layer and patterning the sacrificial layer thereby defining a cut pattern. The cut pattern of the sacrificial layer having an initial width. The method further includes depositing a mask layer over the device layer and over the cut pattern of the sacrificial layer. The method further includes patterning the mask layer thereby defining a line pattern including first and second portions separated by the cut pattern of the sacrificial layer and selectively removing the cut pattern of the sacrificial layer thereby forming a gap that separates the first and second portions of the line pattern of the mask layer. The method further includes patterning the device layer using the first and second portions of the line pattern of the mask layer.

Abstract: A method for correcting topography proximity effects (TPE) for an integrated circuit (IC) design is described. This method includes dividing the IC design into a plurality of levels (z-direction). Each level can be decomposed into one or more elementary geometries. These elementary geometries can be top view geometries, cross-sectional geometries, half-plane geometries, geometries with single slope sides, and/or geometries with multiple slope sides. The one or more elementary geometries can be compared to primitives in a library. A transfer matrix can be generated using the matching primitives and the elementary geometries. A disturbance matrix can be calculated based on the transfer matrix. This disturbance matrix can advantageously capture a spectrum of a reflective electric field from a spectrum of an incident electric field. Wave propagation through a photoresist layer can be performed using the disturbance matrix for the plurality of levels.

Abstract: A pattern from a patterning device is applied to a substrate by a lithographic apparatus. The applied pattern includes product features and metrology targets. The metrology targets include large targets and small targets which are for measuring overlay. Some of the smaller targets are distributed at locations between the larger targets, while other small targets are placed at the same locations as a large target. By comparing values measured using a small target and large target at the same location, parameter values measured using all the small targets can be corrected for better accuracy. The large targets can be located primarily within scribe lanes while the small targets are distributed within product areas.

Abstract: Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.

Abstract: In a method of generating a three-dimensional process window qualification, a photoresist layer is coated on a substrate including an underlying structure. A plurality of circular-shaped regions of the substrate are distinguished into 1 to n regions to partition the substrate into a center portion and an edge portion, n being a natural number greater than 2. 1 to n exposing ranges are set, including a common exposing condition for the 1 to n regions. A photoresist pattern is fox led by exposing each shot portion in the 1 to n regions using a split exposing condition in the 1 to n exposing ranges. The photoresist pattern is detected, and a normal photoresist pattern with respect to each of the 1 to n regions is selected to generate the three-dimensional process window qualification.

Abstract: In a method for fracturing or mask data preparation or mask process correction for charged particle beam lithography, a plurality of shots are determined that will form a pattern on a surface, where shots are determined so as to reduce sensitivity of the resulting pattern to changes in beam blur (?f). At least some shots in the plurality of shots overlap other shots. In some embodiments, ?f is reduced by controlling the amount of shot overlap in the plurality of shots, either during initial shot determination, or in a post-processing step. The reduced sensitivity to ?f expands the process window for the charged particle beam lithography process.

Abstract: In one or more embodiments, the disclosure relates to a method of setting a photolithography exposure machine, comprising: forming on a photolithography mask test patterns and circuit patterns, transferring the patterns to a resin layer covering a wafer, measuring a critical dimension of each test pattern transferred, and determining a focus setting error value of the photolithography machine from the measure of the critical dimension of each pattern, the test patterns formed on the mask comprising a first reference test pattern and a second test pattern forming for a photon beam emitted by the photolithography machine and going through the mask, an optical path having a length different from an optical path formed by the first test pattern and the circuit patterns formed on the mask.

Abstract: A process for use in lithography, such as photolithography for patterning a semiconductor wafer, is disclosed. The process includes receiving an incoming semiconductor wafer having various features and layers formed thereon. A unit-induced overlay (uniiOVL) correction is received and a deformation measurement is performed on the incoming semiconductor wafer in an overlay module. A deformation-induced overlay (defiOVL) correction is generated from the deformation measurement results by employing a predetermined algorithm on the deformation measurement results. The defiOVL and uniiOVL corrections are fed-forward to an exposure module and an exposure process is performed on the incoming semiconductor wafer.

Abstract: The present invention provides an irradiation apparatus which irradiates an object with a charged particle beam, the apparatus including a first charged particle optical system including a charged particle source, a second charged particle optical system into which a charged particle beam is incident from the first charged particle optical system, a detector configured to be moved and to detect a charged particle beam from the first charged particle optical system, and a regulator configured to regulate relative positions between the first charged particle optical system and the second charged particle optical system based on an output from the detector disposed between the first charged particle optical system and the second charged particle optical system.

Abstract: A measuring member has a first face and a plurality of first marks arranged on the first face. The first marks have respective orientations corresponding to their positions in a first direction.

Abstract: A local exposure method includes steps of: dividing a large block into a plurality of small blocks; setting irradiation illuminances different in a stepwise fashion; controlling light emission of light emitting elements based on the irradiation illuminances respectively set for the small blocks for a photosensitive film on a substrate moving with respect to light emitting elements; developing the photosensitive film having been subjected to exposure processing by irradiation by the light emitting elements; measuring a residual film thickness of the photosensitive film for each of the small blocks to obtain correlation data between the illuminance set for the small block and the residual film thickness; and obtaining a required illuminance of irradiation to each of the large blocks from a target residual film thickness of the photosensitive film set for each of the large blocks based on the correlation data.

Abstract: A method of fabricating a semiconductor device includes preparing a layout of the semiconductor device, obtaining contrast of an exposure image of the layout through a simulation under a condition of using a crosspole illumination system, separating the layout into a plurality of sub-layouts based on the contrast of the exposure image, forming a photomask having a mask pattern corresponding to the plurality of sub-layouts, and performing an exposure process using the photomask under an exposure condition of using a dipole illumination system.

Abstract: A method to enable wafer result prediction includes collecting manufacturing data from various semiconductor manufacturing tools and metrology tools; choosing key parameters using an autokey method based on the manufacturing data; building a virtual metrology based on the key parameters; and predicting wafer results using the virtual metrology.

Abstract: Embodiments of the present disclosure disclose a method of forming a new integrated circuit design on a semiconductor wafer using a photolithography tool. The method includes selecting a previously processed wafer having a past integrated circuit design different than the new integrated circuit design, selecting a plurality of critical dimension (CD) data points extracted from the previously processed wafer after the previously processed wafer was etched, and creating a field layout and associated baseline exposure dose map for the new integrated circuit design. The method also includes refining each field in the baseline exposure dose map based on a difference between an average CD for the previously processed wafer and an average CD for each field in the field layout and controlling the exposure of the photolithography tool according to the refined baseline exposure dose map to form the new integrated circuit design on the semiconductor wafer.

Abstract: This invention relates to the manufacture of semiconductor substrates such as wafers and to a method for monitoring the state of polarization incident on a photomask in projection printing using a specially designed polarization monitoring reticle for high numerical aperture lithographic scanners. The reticle measures 25 locations across the slit and is designed for numerical apertures above 0.85. The monitors provide a large polarization dependent signal which is more sensitive to polarization. A double exposure method is also provided using two reticles where the first reticle contains the polarization monitors, clear field reference regions and low dose alignment marks. The second reticle contains the standard alignment marks and labels. For a single exposure method, a tri-PSF low dose alignment mark is used. The reticles also provide for electromagnetic bias wherein each edge is biased depending on that edge's etch depth.

Abstract: A method for manufacturing a photomask includes forming a photoresist film on a substrate, and forming a defect detecting pattern on the photoresist film. The defect detecting pattern has a first pattern elongated in a first direction and a second pattern overlapping one end of the first pattern and elongated in a second direction different from the first direction. The first pattern and the second pattern are formed using electron beams (e-beam) diffracted by a same amplifier.

Abstract: In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a series of curvilinear character projection shots are determined for a charged particle beam writer system, such that the set of shots can form a continuous track, possibly of varying width, on a surface. A method for forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed. Methods for manufacturing a reticle and for manufacturing a substrate such as a silicon wafer by forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed.

Abstract: Method of adjusting the melt flow index of a toner is described, the method including adjusting the pH of the toner after the toner particles have been coalesced and the adjusting alters the melt flow index of the toner.

Abstract: An exposure apparatus according to an embodiment controls the positioning between layers using an alignment correction value calculated on the basis of lower layer position information of a lower-layer-side pattern and upper layer position information of an upper-layer-side pattern. The lower layer position information includes alignment data, a focus map, and a correction value which is set on the basis of the previous substrate. The upper layer position information includes alignment data, a focus map, and a correction value which is a correction value for the positioning and is used when the upper-layer-side pattern is transferred.

Abstract: A lithographic apparatus includes an illuminator for receiving a beam of EUV radiation from a radiation source apparatus and for conditioning the beam to illuminate a target area of a patterning device, such as a reticle. The reticle forms a patterned radiation beam. A projection system transfers the pattern from said patterning device to a substrate by EUV lithography. Sensors are provided for detecting a residual asymmetry in the conditioned beam as the beam approaches the reticle, particularly in a non-scanning direction. A feedback control signal is generated to adjust a parameter of said radiation source in response to detected asymmetry. The feedback is based on a ratio of intensities measured by two sensors at opposite ends of an illumination slit, and adjusts the timing of laser pulses generating an EUV-emitting plasma.

Abstract: Some embodiments include methods for correcting for variation across substrates. A difference map is created to indicate differences between a desired pattern that is to be formed across the substrates utilizing photolithographic processing and a signature pattern representing the actual pattern formed with an initial setting of illumination optics. Modifications to the illumination optics are determined for improving problematic regions identified in the difference map, and the illumination optics are then modified. Substrates are photolithographically processed utilizing the modified illumination optics.

Abstract: The present application describes a method and a device for keeping the mask dimensions of a mask (6) constant in the mask plane in lithography. The mask (6) is heated due to the exposure during lithography. By means of thermal and/or mechanical methods, the dimensions of the mask (6) are kept constant. It is possible to use additional methods or devices, e.g. an air cooler (17) or an air heater (17), in order to prevent a change in the mask dimensions in the mask plane.

Abstract: A method of optimizing a die size in a method of manufacturing devices using a lithographic apparatus, wherein the lithographic apparatus is arranged to expose an image field of variable size in a single exposure step, the image field having a certain maximum size, the method comprising: receiving a desired area for the die; and calculating a target aspect ratio for the die, wherein the target aspect ratio is determined so as to maximize the number of good dies that can be imaged per hour using the lithographic apparatus. Desirably, calculating a target aspect ratio comprises finding a first target aspect ratio that maximizes a figure of merit MF, where MF is the ratio of the number of dies exposed in each image field divided by the number of exposures on each substrate.

Abstract: There is provided a computer-implemented method of creating a recipe for a manufacturing tool and a system thereof. The method comprises: upon obtaining data characterizing periodical sub-arrays in one or more dies, generating candidate stitches; identifying one or more candidate stitches characterized by periodicity characteristics satisfying, at least, a periodicity criterion, thereby identifying periodical stitches among the candidate stitches; and aggregating the identified periodical stitches and the periodical sub-arrays into periodical arrays, said periodical arrays to be used for automated recipe creation.

Abstract: A method for manufacturing a semiconductor device is disclosed, wherein during the physical design process, a curvilinear path is designed to represent an interconnecting wire on the fabricated semiconductor device. A method for fracturing or mask data preparation (MDP) is also disclosed in which a manhattan path which is part of the physical design of an integrated circuit is modified to create a curvilinear pattern, and where a set of charged particle beam shots is generated, where the set of shots is capable of forming the curvilinear pattern on a resist-coated surface.

Abstract: A process for use in lithography, such as photolithography for patterning a semiconductor wafer, is disclosed. The process includes receiving an incoming semiconductor wafer having various features and layers formed thereon. A unit-induced overlay (uniiOVL) correction is received and a deformation measurement is performed on the incoming semiconductor wafer in an overlay module. A deformation-induced overlay (defiOVL) correction is generated from the deformation measurement results by employing a predetermined algorithm on the deformation measurement results. The defiOVL and uniiOVL corrections are fed-forward to an exposure module and an exposure process is performed on the incoming semiconductor wafer.

Abstract: An apparatus and a method for determining an overlap distance of an optical head is disclosed. Positions and light amount distributions of each light spot can be measured, which may be provided from an optical head to a substrate. Gaussian distribution may be applied to the positions and the light amount distributions to calculate a compensation model of each of the light spots. A first accumulated light amount corresponding to each first area of the substrate may be calculated if the optical head is scanning along a first direction of the substrate using the compensation model. A second accumulated light amount corresponding to each second area overlapped with the each first area is calculated if the optical head is scanning along the first direction, which is moved in a second direction by a first distance using the compensation model. An overlap distance may be determined based on a uniformity of summations of the first and second accumulated light amount.

Abstract: Disclosed are systems and methods for time differential reticle inspection. Contamination is detected by, for example, determining a difference between a first signature of at least a portion of a reticle and a second signature, produced subsequent to the first signature, of the portion of the reticle.

Abstract: A semiconductor wafer is aligned using a double patterning process. A first resist layer having a first optical characteristic is deposited and foams at least one alignment mark. The first resist layer is developed. A second resist layer having a second optical characteristic is deposited over the first resist layer. The combination of first and second resist layers and alignment mark has a characteristic such that radiation of a pre-determined wavelength incident on the alignment mark produces a first or higher order diffraction as a function of the first and second optical characteristics.

Abstract: A method for calibrating an apparatus for the position measurement of measurement structures on a lithography mask comprises the following steps: qualifying a calibration mask comprising diffractive structures arranged thereon by determining positions of the diffractive structures with respect to one another by means of interferometric measurement, determining positions of measurement structures arranged on the calibration mask with respect to one another by means of the apparatus, and calibrating the apparatus by means of the positions determined for the measurement structures and also the positions determined for the diffractive structures.

Abstract: A method for printing a desired periodic or quasi-periodic pattern of dot features into a photosensitive layer disposed on a substrate including the steps of designing a mask pattern having a periodic or quasi-periodic array of unit cells each having a ring feature, forming a mask with said mask pattern, arranging the mask substantially parallel to the photosensitive layer, arranging the distance of the photosensitive layer from the mask and illuminating the mask according to one of the methods of achromatic Talbot lithography and displacement Talbot lithography, whereby the illumination transmitted by the mask exposes the photosensitive layer to an integrated intensity distribution that prints the desired pattern.

Abstract: A method of electron beam lithography for producing wafers and masks. To reduce the impacts of the disturbing proximity effect, an expanded correction algorithm that enables a more accurate correction is used to control the electron beam. To create an improved correction method by means of which the contrast and the feature width (CD) of all figures of a pattern can be optimally controlled additional contrast frames (KR) and remaining figures (R) are produced using a geometric method for the purpose of contrast control with respect to all figures (F). Then smaller figures (KRsize-S and Rsize-S) are produced from the contrast frame figures (KR) and remaining figures (R) by means of a negative sizing operation, and subsequently figures (KRsize-S and Rsize-S) are transferred to the proximity correction algorithm with the condition that the resist threshold is reached at the edges of the figures (KR, R) by the dose assignment.

Abstract: A computer is programmed to use at least one rule to identify from within a layout of an IC design, a set of regions likely to fail if fabricated unchanged. An example of such a rule of detection is to check for presence of two neighbors neither of which fully overlaps a short wire or an end of a long wire. The computer uses at least another rule to change at least one region in the set of regions, to obtain a second layout which is less likely to fail in the identified regions. An example of such a rule of correction is to elongate at least one of the two neighbors. The computer may perform optical rule checking (ORC) in any order relative to application of the rules, e.g. ORC can be performed between detection rules and correction rules i.e. performed individually on each identified region prior to correction.

Abstract: Methods, computer program products and apparatuses for optimizing design rules for producing a mask are disclosed, while keeping the optical conditions (including but not limited to illumination shape, projection optics numerical aperture (NA) etc.) fixed. A cross-correlation function is created by multiplying the diffraction order functions of the mask patterns with the eigenfunctions from singular value decomposition (SVD) of a TCC matrix. The diffraction order functions are calculated for the original design rule set, i.e., using the unperturbed condition. ILS is calculated at an edge of a calculated image of a critical polygon using the cross-correlation results and using translation properties of a Fourier transform. The use of the calculated cross-correlation of the mask and the optical system, and the translation property of the Fourier transform for perturbing the design reduces the computation time needed for determining required changes in the design rules.

Abstract: The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved.

Abstract: An internal defect or the like of a transfer mask is detected using transmitted light quantity distribution data of an inspection apparatus. Using a die-to-die comparison inspection method, inspection light is irradiated to a first region of a thin film to obtain a first transmitted light quantity distribution, the inspection light is also irradiated to a second region of the thin film to obtain a second transmitted light quantity distribution, a predetermined-range difference distribution is produced by plotting coordinates at which difference light quantity values calculated from a comparison between the first transmitted light quantity distribution and the second transmitted light quantity distribution are each not less than a first threshold value and less than a second threshold value, and a selection is made of a transfer mask in which a region with high density of plotting is not detected in the predetermined-range difference distribution.

Abstract: Provided is a thin film evaluation method for a transfer mask which is adapted to be applied with ArF excimer laser exposure light and comprises a thin film formed with a pattern on a transparent substrate. The method includes intermittently irradiating pulsed laser light onto the thin film to thereby evaluate the irradiation durability of the thin film.

Abstract: A method for fracturing or mask data preparation for shaped beam charged particle beam lithography is disclosed, in which a square or nearly-square contact or via pattern is input, and a set of charged particle beam shots is determined which will form a circular or nearly-circular pattern on a surface, where the area of the circular or nearly-circular pattern is within a pre-determined tolerance of the area of the input square or nearly-square contact or via pattern. Methods for forming a pattern on a surface and for manufacturing a semiconductor device are also disclosed.

Abstract: A detector (550) for detecting light (248B) from a light source (248A) comprises a single array of pixels (574) and a first mask (576). The single array of pixels (574) includes a plurality of rows of pixels (574R), and a plurality of columns of pixels (574C) having at least a first active column of pixels (574AC) and a spaced apart second active column of pixels (574AC). The first mask (576) covers one of the plurality of columns of pixels (574C) to provide a first masked column of pixels (574MC) that is positioned between the first active column of pixels (574AC) and the second active column of pixels (574AC). Additionally, a charge is generated from the light (248B) impinging on the first active column of pixels (574AC), is transferred to the first masked column of pixels (574MC), and subsequently is transferred to the second active column of pixels (574AC).

Abstract: Provided is a method of performing a maskless lithography process. The method includes providing a proximity correction pattern. The method includes generating a deformed pattern based on the proximity correction pattern. The method includes performing a first convolution process to the proximity correction pattern to generate a first proximity correction pattern contour. The method includes processing the first proximity correction pattern contour to generate a second proximity correction pattern contour. The method includes performing a second convolution process to the deformed pattern to generate a first deformed pattern contour. The method includes processing the first deformed pattern contour to generate a second deformed pattern contour. The method includes identifying mismatches between the second proximity correction pattern contour and the second deformed pattern contour. The method includes determining whether the deformed pattern is lithography-ready in response to the identifying.

Abstract: In the field of semiconductor device production, a method and system for fracturing or mask data preparation or optical proximity correction are disclosed, in which a target maximum dosage for a surface is input, and where a plurality of variable shaped beam (VSB) shots is determined that will form a pattern on the surface, where at least two of the shots partially overlap, and where the plurality of shots are determined so that the maximum dosage produced on the surface is less than the target dosage. A similar method is disclosed for manufacturing an integrated circuit.

Abstract: An optical-component fabricating method includes arranging a mask that has both an optical component pattern and an alignment mark pattern and a wafer that is developed through the mask at predetermined positions; exposing the optical component pattern and the alignment mark pattern onto the wafer; developing the alignment mark pattern that is exposed on the wafer; observing a position of the developed alignment mark pattern and moving the wafer in accordance with the position; repeating the exposing, the developing, and the moving a predetermined number of times; developing all the optical component patterns on the wafer; and etching the developed optical component patterns.

Abstract: There is proposed a charged particle beam apparatus including: a plurality of noise removal filters that remove noise of an electrical signal; a measurement unit that measures the contrast-to-noise ratio after applying one of the noise removal filters; and a determination unit that determines a magnitude relationship between the contrast-to-noise ratio measured by the measurement unit and a threshold value set in advance.

Abstract: A method for decomposing design shapes in a design level into a plurality of target design levels is provided. Design shapes including first-type edges and second-type edges having different directions is provided for a design level. Inner vertices are identified and paired up. Vertices are classified into first-type vertices and second-type vertices. First mask level shapes are generated so as to touch the first-type vertices, and second mask level shapes are generated so as to tough the second-type vertices. Cut mask level shapes are generated to touch each first-type edges that are not over a second-type edge and to touch each second-type edges that are not over a first-type edge. Suitable edges are sized outward to ensure overlap among the various shapes. The design shapes are thus decomposed into first mask level shapes, the second mask level shapes, and the cut mask level shapes.

Abstract: A system and method for providing a cell layout for multiple patterning technology is provided. An area to be patterned is divided into alternating sites corresponding to the various masks. During a layout process, sites located along a boundary of a cell are limited to having patterns in the mask associated with the boundary site. When placed, the individual cells are arranged such that the adjoining cells alternate the sites allocated to the various masks. In this manner, the designer knows when designing each individual cell that the mask pattern for one cell will be too close to the mask pattern for an adjoining cell.