Abstract: Provided is a method for producing a probe capable of keeping sure electric conduction between the probe and a conductive pad. The method comprises the steps of: applying photo resists onto the front and rear faces of a conductive plate-form material which is to make a probe; masking one face of the plate-form material with a first mask, and masking the other face of the plate-form material with a second mask; subjecting the photo resists to exposure to light and development, and step of using the photo resists remaining in the exposure and development step as mask materials to etch the plate-form material.

Abstract: An interactive information device for use as a touch panel, touch screen, digitizer panel, or pen-input device, and a method for making such a device includes a first, transparent, electrically conductive layer supported by the rigid substrate, a flexible, transparent substrate at least partially aligned with the rigid substrate and having a second, transparent, electrically conductive layer on a surface thereof, the second conductive layer being spaced from the first conductive layer. A plurality of transparent insulating spacer members/dots are positioned on one or both of the conductive layers to allow the conductive layers to engage when the flexible substrate is pressed. The spacer members/dots comprise polymeric material including at least some inorganic material, and more preferably, comprise organic-inorganic nanocomposites having an index of refraction optically matched to the transparent, electrically conductive layer on which they are positioned.

Abstract: A method includes removing at least a piece of a deposition chamber liner from a deposition chamber by passing it through a passageway to the deposition chamber through which semiconductor substrates pass into and out of the chamber for deposition processing. A replacement for the removed deposition chamber liner piece is provided into the chamber by passing the replacement through said passageway. A liner apparatus includes a plurality of pieces which when assembled within a selected semiconductor substrate deposition processor chamber are configured to restrict at least a majority portion of all internal wall surfaces which define said semiconductor substrate deposition processor chamber from exposure to deposition material within the chamber. At least some of the pieces are sized for passing completely through a substrate passageway to the chamber through which semiconductor substrates pass into and out of the chamber for deposition processing.

Abstract: The present invention is a surface-mounted device of light-emitting diodes (SMD LED) whose component typically has a plane on the surface. Through the calculation of Snell's Law, most of light fails to be emitted directly from the component because of the difference in the refractive index of the epoxy resin and the atmosphere (the refractive index of the light in the atmosphere is 1, the refractive index of the epoxy resin is around 1.5). It takes several times of refraction and a waste of brightness to allow the light that fails to be emitted directly a chance to be emitted, while leaving some light that might never be emitted. Therefore, the brightness reduces. The surface-mounted devices of light-emitting diodes with small lens for the present invention attach several small lens or diffraction lens on the plane surface of the SMD LED. The lens that enlarges the critical angle increases the direct light-emitting opportunity from the light-emitting chip, which in turn increases the brightness of LED.

Abstract: A microelectronic package including a microelectronic die disposed within an opening in a microelectronic packaging core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic die. Build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulant material, and the microelectronic package core to form the microelectronic package.

Abstract: A semiconductor component (50), in particular a solar cell, which has at least one semiconductor base material (40) consisting of a mono or a polycrystalline structure. The semiconductor base material (40) consists at least in part of pyrite with the chemical composition FeS2 and which is cleaned for the purpose of achieving a defined degree of purity. Maximum benefit is drawn from the semiconductor base material (40) when it is produced from at least one layer of pyrite (51), at least one layer of boron (52) and at least one layer of phosphorous (53). An optimum type is derived from this semiconductor component when it is used as a solar cell.

Abstract: A fabrication method for forming a semiconductor device having a MIM (Metal-Insulator-Metal) capacitor is provided. A lower electrode is formed on a substrate. The lower electrode is subjected to a pre-annealing. The pre-annealing includes a thermal annealing in a hydrogen atmosphere, a nitrogen atmosphere or a mixed atmosphere of hydrogen and nitrogen. A capacitor dielectric layer is formed on the lower electrode. An upper electrode is formed on the capacitor dielectric layer. According to the present invention, the characteristic of a MIM capacitor can be enhanced by the pre-annealing without any substantial change in the materiality of the lower electrode.

Abstract: A process for manufacturing a semiconductor device includes the following steps applied to a semiconductor substrate having, on its main surface, a plurality of separation oxide films, formed in stripes parallel to each other, and gate oxide films formed in the regions placed between separation oxide films, wherein pieces of a polysilicon layer are formed so as to extend from areas above gate oxide films to areas above portions of separation oxide films on both sides of the gate oxide films and wherein a first resist is formed so as to cover the top surfaces of polysilicon layer: the injection step of injecting an impurity into polysilicon layer above separation oxide films; and the thermal diffusion step of carrying out a heat processing so that the injected impurity diffuses to the regions above gate oxide films within polysilicon layer.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device capable of reducing a short channel effect are provided.

Abstract: A semiconductor device improved to suppress a leakage current of a transistor is provided. A gate electrode is disposed on a semiconductor substrate. A pair of p type source/drain layers are provided on the surface of the semiconductor substrate, on both sides of the gate electrode in the gate length direction Y. An n type gate width determining layer is provided on the surface of the semiconductor substrate to sandwich the source/drain layers in the width direction X of the gate electrode, which determines a gate width of the gate electrode. The source/drain layers and the gate width determining layer are isolated by PN junction.

Abstract: A transistor is protected when a high voltage is applied to a drain, without involvement of an increase in the capacitance of a neighborhood of the drain. A semiconductor device has a gate electrode formed on a silicon semiconductor substrate by way of a gate oxide film, and a pair of N+-type diffusion layers formed on a surface region of the silicon semiconductor substrate on either side of the gate electrode. An N-type diffusion layer is formed in a predetermined area on the N+-type diffusion layer on the drain so as to protrude toward a position lower than the bottom of the N+-type diffusion layer.

Abstract: Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a spirally patterned conductor layer which terminates in a microelectronic structure within the center of the spirally patterned conductor layer. The spirally patterned conductor layer forms a planar spiral inductor, and the microelectronic structure formed within the center of the spirally patterned conductor layer further comprises a series of electrically interconnected sub-patterns. The method contemplates a microelectronic fabrication fabricated in accord with the method. The microelectronic fabrication is fabricated with optimal performance while occupying minimal microelectronic substrate area.

Abstract: In a substrate processing apparatus including a processing chamber for forming a processing room, a susceptor for supporting a substrate to be processed and a susceptor rotating unit for rotating the susceptor, the susceptor rotating unit includes a permanent magnet coupled with the susceptor and an electromagnet coupled with the processing chamber, wherein there is a spacing between the permanent magnet and the electromagnet. In the substrate processing apparatus, the inner part of the processing chamber is isolated from the atmosphere of the susceptor by the spacing between the permanent magnet and the electromagnet; and the susceptor is directly rotated by rotating the permanent magnet under a magnetic field formed by the electromagnet.

Abstract: A tape form substrate has a plurality of semiconductor elements arrayed in a central portion in the longitudinal direction, and first and second patterns extend laterally from the central portion of the substrate; each of the patterns comprises a plurality of wires having bonding portions with the semiconductor elements, external terminal portions connected to the bonding portions, and lead-out portions extending from the external terminal portions to the outside; and the wires are formed in a plurality of groups, with the ends of the lead-out portions of each group of wires disposed in a fixed pattern.

Abstract: External connection terminals (25) are disposed on side surfaces, a back surface, or both the side surfaces and the back surface of a semiconductor element, especially an optical element (20) such as an image sensor, a solid state imaging device, etc. The external connection terminals (25) are connected electrically to an integrated circuit (21) of the optical element (20) via wirings (23). The wirings (23) are connected electrically to electrical measuring electrodes (23T) in the course of wafer process, but the electrical measuring electrodes (23T) are disconnected from the wirings (23) after the electrical measurement has been completed. The electrical measuring electrodes (23T) are formed on dicing lines and then removed at the same time when dicing process is executed. The external connection terminals (25) are connected to the wirings (23) from which the electrical measuring electrodes (23T) are disconnected.

Abstract: A method for electrically contacting a rear side of a semiconductor substrate when processing the semiconductor substrate includes the step of placing the semiconductor substrate with a substrate rear side on a substrate holder such that an electrically conductive contact layer formed of a semiconductor material is disposed between the semiconductor substrate and the substrate holder.

Abstract: A process for producing a substrate 1 having a base-metal plating layer, which includes an immersion step for immersing the substrate 1 in a plating solution contained in a plating tank 33, to thereby form a base-metal plating layer; a washing step for removing the substrate 1 from the plating tank 33, transferring the substrate 1 to a washing tank, and washing the substrate 1; and a cooling step for applying a cooling liquid to the substrate 1 during at least a portion of the period during which the substrate is transferred to a position where the washing step is carried out after completing the immersion step, to thereby cool the substrate 1. An apparatus for carrying out the above process is also disclosed.

Abstract: In an integrated circuit configuration, above a first conductive structure which is embedded in a first insulating layer there are arranged a first barrier layer and a second insulating layer, in which a contact hole is provided which reaches down to the first conductive structure. Above the first barrier layer, the side walls of the contact hole are provided with spacers which act as a diffusion barrier and which reach down to the surface of the first barrier layer. A second conductive structure is arranged in the contact hole. The second conductive structure is conductively connected to the first conductive structure. During the production of the contact hole, the spacers prevent deposition of material from the first conductive structure on the surface of the second insulating layer.

Abstract: A method of fabricating a back surface point contact silicon solar cell having p-doped regions and n-doped regions on the same side by forming a passivating layer on a surface of the cell having opened windows at the p-doped regions and the n-doped regions, by depositing and patterning a first metal layer on the passivating layer in such a way that the first metal layer comes into contact with the p-doped regions and the n-doped regions, by depositing a first insulator layer of inorganic material on the first metal layer, by etching and patterning the first insulator layer in such a way that the insulator layer has opened windows at, at least one of the p-doped regions and the n-doped regions, by depositing a second insulator layer of organic material on the first insulator layer, by etching and patterning the second insulator layer in such a way that the insulator layer has opened windows at the one of the p-doped regions and the n-doped regions, by curing the second insulator layer by heating at a predeterm

Abstract: A multi-probe ring assembly including integral fine probe tips, conductive lines with terminal connection for testing semiconductor devices and a method of construction of the multi-probe ring assembly is described. The method of construction described utilizes the step of etching pits into silicon wafers to produce molds for forming the probe points. Semiconductor machining processes are used to complete the probe ring assembly.

Abstract: A metal oxide ceramic layer is formed from an amorphous film. The metal oxide ceramic layer comprises, for example, a Bi-based oxide ceramic, The amorphous Bi-based metal oxide layer is annealed to transformed it into a ferroelectric layer. A lower thermal budget is needed to transform the amorphous Bi-based metal oxide ceramic into the ferroelectric phase.

Abstract: A method and structure are disclosed which involve the re-wafering of previously processed and tested IC chips. The chips are encapsulated in supporting non-conductive material in a neo-wafer, so that they may be further processed preparatory to dicing layer units from the neo-wafer, which layer units are ready for stacking in a three-dimensional electronic package. Although the layer areas are the same, different stacked layers may contain different sized IC chips, and a single layer may encapsulate a plurality of chips. Precision of location of the separate IC chips in the neo-wafer is insured by use of photo-patterning means to locate openings in the neo-wafer into which extend conductive bumps on the chips. The neo-wafer is preferably formed with separate cavities in which the chips are located before they are covered with the encapsulating material.

Abstract: A method for removing a diffusion barrier layer on pad regions and diminishing the effect of plasma ions induced when removing a photoresist layer by a plasma asher. A two stage rapid thermal processing step is applied to the partially-removed diffusion barrier layer before a metal layer is formed. The first stage lasts a longer period of time at a lower temperature, for example, in the range of between 50 and 60 seconds at a temperature of about 600.degree. C. The second stage lasts a shorter period of time at a higher temperature, for example, in the range of between 20 and 30 seconds at a temperature of about 750.degree. C.