Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.

Abstract: A heat dissipation adhesive film, a semiconductor device including the same, and a method of fabricating the semiconductor device, the heat dissipation adhesive film being placeable between a protective layer encasing a semiconductor element therein and a heat dissipation metal layer on the protective layer to bond the protective layer to the heat dissipation metal layer, wherein an adhesive strength between the heat dissipation adhesive film and the protective layer and an adhesive strength between the heat dissipation adhesive film and the heat dissipation metal layer are each about 3 kgf/25 mm2 or greater.

Abstract: Providing a method for manufacturing a package capable of achieving reliable anodic bonding between the bonding material and a base board wafer even when the bonding material having a large resistance value is used. Providing a method for manufacturing a package by anodically bonding a bonding material, which is fixed in advance to an inner surface of a lid board wafer made of an insulator, to an inner surface of a base board wafer made of an insulator, the method including an anodic bonding step where an auxiliary bonding material serving as an anode is disposed on an outer surface of the lid board wafer, a cathode is disposed on an outer surface of the base board wafer, and a voltage is applied between the auxiliary bonding material and the cathode, wherein the auxiliary bonding material is made of a material that causes an anodic bonding reaction between the auxiliary bonding material and the lid board wafer in the anodic bonding step.

Abstract: Packaged microelectronic devices and methods of manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a stand-off layer over a plurality of microelectronic dies on a semiconductor workpiece, and removing selected portions of the stand-off layer to form a plurality of stand-offs with the individual stand-offs positioned on a backside of a corresponding die. The method further includes cutting the semiconductor workpiece to singulate the dies, and attaching the stand-off on a first singulated die to a second die.

Abstract: A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

Abstract: A chip package includes a substrate, a pad positioned on the substrate, a base board, at least one adhesive layer and at least one chip. The base board is positioned on the pad. At least one mounting hole is defined through the base board. The at least one adhesive layer is received in the at least one mounting hole. The at least one chip is received in the at least one mounting hole and adhere to the pad via the at least one adhesive layer.

Abstract: A method for fabrication of a lid for a microelectronic device is described, wherein the microelectronic device comprises of a die and a laminate. A gel is formed having a coefficient of thermal expansion (CTE) within a threshold percentage value of either a CTE of the die or a CTE of the laminate of the microelectronics device. A metal piece is inserted into the gel to form a lid.

Abstract: An insulating adhesive film is formed by laminating a first insulating adhesive layer which contains a filler in an insulating adhesive composition and a second insulating adhesive layer which contains no filler in an insulating adhesive composition. H/2<Tf<H?Tf+Tn is satisfied, wherein H is the height of the bump of the IC chip, Tf is the thickness of the first insulating adhesive layer, and the Tn is the thickness of the second insulating adhesive layer. The side of the substrate on which an electrode is formed and the side of an IC chip on which a bump is formed are connected via the insulating adhesion film arranged such that the first insulating adhesive layer and the electrode-forming side of the electronic component are opposed to thereby connect the electrode of the substrate and the bump of the IC chip.

Abstract: A semiconductor chip (1) is flip-chip mounted on a circuit board (4) with an underfill resin (6) interposed between the semiconductor chip (1) and the circuit board (4) and a container covering the semiconductor chip (1) is bonded on the circuit board (4). At this point, the semiconductor chip (1) positioned with the underfill resin (6) interposed between the circuit board (4) and the semiconductor chip (1) is pressed and heated by a pressure-bonding tool (8); meanwhile, the surface of the underfill resin (6) protruding around the semiconductor chip (1) is pressed by the pressure-bonding tool (8) through a film (13) on which a surface unevenness is formed in a periodically repeating pattern, so that a surface unevenness (16a) is formed. The inner surface of the container covering the semiconductor chip (1) is bonded to the surface unevenness (16a) on the surface of the underfill resin.

Abstract: The film for back surface of flip-chip semiconductor according to the present invention is a film for back surface of flip-chip semiconductor to be formed on a back surface of a semiconductor element having been flip-chip connected onto an adherend, wherein a tensile storage elastic modulus at 23° C. after thermal curing is 10 GPa or more and not more than 50 GPa. According to the film for back surface of flip-chip semiconductor of the present invention, since it is formed on the back surface of a semiconductor element having been flip-chip connected onto an adherend, it fulfills a function to protect the semiconductor element. In addition, since the film for back surface of flip-chip semiconductor according to the present invention has a tensile storage elastic modulus at 23° C. after thermal curing of 10 GPa or more, a warp of the semiconductor element generated at the time of flip-chip connection of a semiconductor element onto an adherend can be effectively suppressed or prevented.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for surface treatment of an integrated circuit (IC) substrate. In one embodiment, an apparatus includes an integrated circuit substrate, an interconnect structure disposed on the integrated circuit substrate, the interconnect structure being configured to route electrical signals to or from the integrated circuit substrate and comprising a metal surface, and a protective layer disposed on the metal surface of the interconnect structure, the protective layer comprising a first functional group bonded with the metal surface and a second functional group bonded with the first functional group, wherein the second functional group is hydrophobic to inhibit contamination of the metal surface by hydrophilic materials and further inhibits oxidation of the metal surface. Other embodiments may be described and/or claimed.

Abstract: A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes the steps of providing a semiconductor chip having an active surface and a non-active surface opposing to the active surface, roughening a peripheral portion of the non-active surface so as to divide the non-active surface into the peripheral portion formed with a roughened structure and a non-roughened central portion, mounting the semiconductor chip on a chip carrier via a plurality of solder bumps formed on the active surface, forming an encapsulant on the chip carrier to encapsulate the semiconductor chip. The roughened structure formed on the peripheral portion of the non-active surface of the semiconductor chip can reinforce the bonding between the semiconductor chip and the encapsulant, and the non-roughened central portion of the non-active surface of the semiconductor chip can maintain the structural strength of the semiconductor chip.

Abstract: A system for bonding a die to a high power dielectric carrier such as a ceramic dielectric core with double-sided conductive layers is described. In the system, the upper conductive layer has a first area whose surface has a first wettability. A second area that at least partially surrounds the first area has a surface with a second wettability that is greater than the first wettability. During bonding, an adhesive material bonding a chip to the substrate spreads among the first area by a downward force placed on the chip. Due to the difference in wettability, the adhesive material then spreads among the second area by a wetting force generated by the greater second wettability of the second area surface causing the chip to be drawn down until reaching a predetermined position. The predetermined position can be determined by substrate protrusions or substrate cavities.

Abstract: There is reduced the difference in inductance between bonding wires to be coupled to two semiconductor chips stacked one over another. A semiconductor device includes external terminals, lower and upper semiconductor chips, and first and second bonding wires. The lower semiconductor chip has first bonding pads, and the upper semiconductor chip has second bonding pads. The first bonding wire couples the first bonding pad of the lower semiconductor chip and the external terminal, and the second bonding wire couples the second bonding pad of the upper semiconductor chip and the external terminal. The diameter of the second bonding wire is larger than the diameter of the first bonding wire.

Abstract: To eliminate electric discharge when an element formation layer including a semiconductor element is peeled from a substrate used for manufacturing the semiconductor element, a substrate over which an element formation layer and a peeling layer are formed and a film are made to go through a gap between pressurization rollers. The film is attached to the element formation layer between the pressurization rollers, bent along a curved surface of the pressurization roller on a side of the pressurization rollers, and collected. Peeling is generated between the element formation layer and the peeling layer and the element formation layer is transferred to the film. Liquid is sequentially supplied by a nozzle to a gap between the element formation layer and the peeling layer, which is generated by peeling, so that electric charge generated on surfaces of the element formation layer and the peeling layer is diffused by the liquid.

Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.

Abstract: Disclosed herein is a method of manufacturing a printed circuit board, comprising: preparing a first carrier including a first pattern formed on one side thereof; preparing a second carrier including a first solder resist layer and a second pattern sequentially formed on one side thereof; pressing the first carrier and the second carrier such that the first pattern is embedded in one side of an insulation layer and the second pattern is embedded in the other side of the insulation layer and then removing the first carrier and the second carrier to fabricate two substrates; attaching the two substrates to each other using an adhesion layer such that the first solder resist layers face each other; and forming a via for connecting the first pattern with the second pattern in the insulation layer, forming a second solder resist on the insulation layer provided with the first pattern, and then removing the adhesion layer.

Abstract: A method comprises forming semiconductor flip chip interconnects having electrical connecting pads and electrically conductive posts terminating in distal ends operatively associated with the pads. We solder bump the distal ends by injection molding, mask the posts on the pads with a mask having a plurality of through hole reservoirs and align the reservoirs in the mask to be substantially concentric with the distal ends. Injecting liquid solder into the reservoirs and allowing it to cool provides solidified solder on the distal ends, which after mask removal produces a solder bumped substrate which we position on a wafer to leave a gap between the wafer and the substrate. The wafer has electrically conductive sites on the surface for soldering to the posts. Abutting the sites and the solder bumped posts followed by heating joins the wafer and substrate. The gap is optionally filled with a material comprising an underfill.

Abstract: Through-silicon-via (TSV) based 3D integrated circuit (3D IC) stacks are aligned, bonded and electrically interconnected using a transparent alignment material in the TSVs until the wafers are bonded. Embodiments include providing a first wafer having a first device layer and at least one first TSV filled with a conductive material, providing a second wafer having a second device layer, forming at least one second TSV in the second wafer, filling each second TSV with an alignment material, thinning the second wafer until the transparent material extends all the way through the wafer, aligning the first and second wafers, bonding the first and second wafers, removing the alignment material from the second wafer, and filling each second TSV in the second wafer with a conductive material.

Abstract: A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a coverlay layer on the substrate and the electrically conductive pattern, forming a partially cured, tacky adhesive layer on the coverlay layer, and forming openings in the coverlay layer and the partially cured, tacky adhesive layer aligned with the electrically conductive pattern. The method includes positioning an IC on the partially cured, tacky adhesive layer and thereafter curing the partially cured tacky adhesive layer to thereby simultaneously mechanically secure and electrically interconnect the IC to the substrate, the IC having bond pads on a surface thereof.

Abstract: Embodiments of the present invention provide a novel process integration for air gap formation at the sidewalls for a Through Silicon Via (TSV) structure. The sidewall air gap formation scheme for the TSV structure of disclosed embodiments reduces parasitic capacitance and depletion regions in between the substrate silicon and TSV conductor, and serves to also reduce mechanical stress in silicon substrate surrounding the TSV conductor.

Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. A step is performed to selectively etch through the semiconductor active layer and the sacrificial layer in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. A step can be performed to selectively etch through the capping layer and the first portion of the semiconductor active layer to thereby expose the sacrificial layer.

Abstract: Semiconductor devices are described that include a semiconductor device having multiple, stacked die on a substrate (e.g., a semiconductor wafer). In one or more implementations, wafer-level package devices that employ example techniques in accordance with the present disclosure include an ultra-thin semiconductor wafer with metallization and vias formed in the wafer and an oxide layer on the surface of the wafer, an integrated circuit chip placed on the semiconductor wafer, an underfill layer between the integrated circuit chip and the semiconductor wafer, a buffer material formed on the semiconductor wafer, the underfill layer, and at least one side of the integrated circuit chip, an adhesive layer placed on the buffer layer and the integrated circuit chip, and a stiffener layer placed on the adhesive layer. The semiconductor device may then be segmented into individual semiconductor chip packages.

Abstract: A method for assembling a heat generating element and a heat dissipating element includes: preparing a pressure sensitive element including a pressure sensitive layer and first and second release films connected to the pressure sensitive layer; separating the second release film from the pressure sensitive layer and then adhering a heat dissipating element to the pressure sensitive layer; forcing the first release film; separating the first release film from the pressure sensitive layer, and then adhering a heat generating element to the pressure sensitive layer; and fixedly attaching the heat generating element onto the pressure sensitive layer. A pressure sensitive element and a power supplying unit are also disclosed.

Abstract: A light emitting device includes a substrate, at least one electrode, a first contact layer, a second contact layer, a light emitting structure layer, and an electrode layer. The electrode is disposed through the substrate. The first contact layer is disposed on a top surface of the substrate and electrically connected to the electrode. The second contact layer is disposed on a bottom surface of the substrate and electrically connected to the electrode. The light emitting structure layer is disposed above the substrate at a distance from the substrate and electrically connected to the first contact layer. The light emitting structure layer includes a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer. The electrode layer is disposed on the light emitting structure layer.

Abstract: An adhesive resin composition of the present invention includes an expandable sticky polymer having a structure derived from a Meldrum's acid derivative, or a Meldrum's acid derivative represented by the following general formula (1) and an adhesive resin.

Abstract: The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad.

Abstract: An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Abstract: This disclosure relates generally to a semiconductor device and method of making the semiconductor device by pressing an electrical contact of a chip into a bonding layer on a carrier. The bonding layer is cured and coupled, at least in part, to the electrical contact. A molding layer is applied in contact with the chip and a first major surface of the bonding layer. Distribution circuitry is coupled to the electrical contact.

Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings.

Abstract: Embodiments described herein relate to manufacturing a device. The method includes etching at least one recess pattern in an internal surface of a lead frame, the at least one recess pattern including a perimeter recess that defines a perimeter of a mounting area. The method also includes attaching a component to the internal surface of the lead frame such that a single terminal of the component is attached in the mounting area and the single terminal covers the perimeter recess, wherein the perimeter recess has a size and shape such that the recess is proximate a perimeter of the single terminal.

Abstract: The present invention provides a temporary carrier bonding and detaching process. A first surface of a semiconductor wafer is mounted on a first carrier by a first adhesive layer, and a first isolation coating disposed between the first adhesive layer and the first carrier. Then, a second carrier is mounted on the second surface of the semiconductor wafer. The first carrier is detached. Then, the first surface of the semiconductor wafer is mounted on a film frame. The second carrier is detached. The method of the present invention utilizes the second carrier to support and protect the semiconductor wafer, after which the first carrier is detached. Therefore, the semiconductor wafer will not be damaged or broken, thereby improving the yield rate of the semiconductor process. Furthermore, the simplicity of the detaching method for the first carrier allows for improvement in efficiency of the semiconductor process.

Abstract: A method of making a cavity substrate. The method includes: preparing a supporting board including a stiffener, a bump/flange sacrificial carrier, an adhesive and an electrical pad, wherein the adhesive bonds the stiffener to the sacrificial carrier; forming a careless build-up circuitry on the supporting board in contact with the bump and the stiffener; and removing the bump to form a cavity and expose the electrical pad from a closed end of the cavity; wherein the cavity is laterally covered and surrounded by the adhesive. A semiconductor device can be mounted on the cavity substrate and electrically connected to the electrical pad. The careless buildup circuitry provide signal routing for the semiconductor device while the built-in stiffener can provide adequate mechanical support for the careless build-up circuitry and the semiconductor device.

Abstract: In one embodiment, a method of forming a semiconductor package comprises providing a first die having contact regions on a top surface but not on an opposite bottom surface. A dielectric liner layer is deposited under the bottom surface of the first die. The first die is attached with the deposited dielectric liner layer to a die paddle of a substrate. A bond layer is disposed between the substrate and the dielectric liner layer.

Abstract: A method for connecting a semiconductor chip to a metal layer of a carrier substrate is disclosed. A semiconductor chip is provided which has a first side, a second side opposite the first side, a glass substrate bonded to the second side of the semiconductor chip and including at least one opening leaving an area of the second side of the semiconductor chip uncovered by the glass substrate, and a metallization region arranged in the opening of the glass substrate and electrically contacting the second side of the semiconductor chip. The semiconductor chip with the bonded glass substrate is brought onto a metal layer of a carrier substrate. A firm mechanical and electrical connection is formed between the metal layer of the carrier substrate and the metallization region.

Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region.

Abstract: Various methods of attaching a lid to an integrated circuit substrate are provided. In one aspect, a method of attaching a lid to a substrate that has an integrated circuit positioned thereon is provided. An adhesive is applied to the substrate and an indium film is applied to the integrated circuit. The lid is positioned on the adhesive. The adhesive is partially hardened and the indium film is reflowed. The adhesive is cured.

Abstract: An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.

Abstract: Semiconductor devices are described that include a semiconductor device having multiple, stacked die on a substrate (e.g., a semiconductor wafer). In one or more implementations, wafer-level package devices that employ example techniques in accordance with the present disclosure include an ultra-thin semiconductor wafer with metallization and vias formed in the wafer and an oxide layer on the surface of the wafer, an integrated circuit chip placed on the semiconductor wafer, an underfill layer between the integrated circuit chip and the semiconductor wafer, a buffer material formed on the semiconductor wafer, the underfill layer, and at least one side of the integrated circuit chip, an adhesive layer placed on the buffer layer and the integrated circuit chip, and a stiffener layer placed on the adhesive layer. The semiconductor device may then be segmented into individual semiconductor chip packages.

Abstract: An IC package that is suitable for surface mounting arrangements includes a heat spreader device that is coupled to a bottom portion of the package below the IC die. Coupling the heat spreader device to the bottom portion of the package reduces or eliminates the possibility that placement of the heat spreader device will result in the molding compound bleeding on top of the heat spreader device, and delamination at the footings of the heat spreader device that can cause the package to delaminate, or “popcorn”.

Abstract: A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.

Abstract: Flexible structures and method of providing a flexible structure are disclosed. In some embodiments, a method of providing a flexible structure includes: providing a flex substrate having a device bonded to a first side of the flex substrate; and attaching a rigid layer to a second side of the flex substrate opposite the first side using an adhesive layer.

Abstract: When forming a conductive film by a method comprising sputtering after grinding the back surface of a semiconductor substrate, in order to avoid discharge from a part of an adhesive flown out at the outer periphery of the substrate, wherein the adhesive is used to fix the substrate to a support during grinding, at least the substrate end or the adhesive is removed after grinding the semiconductor substrate and before forming the conductive film, so that a gap between the substrate end and the adhesive may have a predetermined size.

Abstract: Various aspects of the present invention provide a transfer method for peeling off an MIM structure (comprising lower electrode/dielectric layer/upper electrodes) film formed on a supporting substrate and then transferring onto a transfer substrate with sufficiently uniform and low damage. Various aspects of the present invention also provide a thin film element provided with one or more thin film components which are transferred onto a substrate by using said method.

Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.

Abstract: In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body. The semiconductor package includes a post within the first insulating body and adjacent to a side of the first semiconductor chip.

Abstract: A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

Abstract: Various embodiments are directed to a semiconductor package and a method for manufacturing the same. A semiconductor package includes the following: a substrate having a plurality of connection pads; a semiconductor chip provided with a plurality of bonding pads on a first surface thereof and attached onto the substrate in a face-down position so that the bonding pads are positioned right above the corresponding connection pads; and thermoplastic conductive members introduced between the substrate and the semiconductor chip such that the bonding pad and the corresponding connection pad may be electrically connected.

Abstract: Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.

Abstract: A method of making a stackable semiconductor assembly that includes a semiconductor device, a heat spreader, an adhesive, a plated through-hole, first build-up circuitry and second build-up circuitry is disclosed. The heat spreader includes a bump and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the first build-up circuitry and thermally connected to the bump. The bump extends into an opening in the adhesive and the flange extends laterally from the bump at the cavity entrance. The first build-up circuitry and the second build-up circuitry extend beyond the semiconductor device in opposite vertical directions. The plated through-hole extends through the adhesive and provides signal routing between the first build-up circuitry and the second build-up circuitry. The heat spreader provides heat dissipation for the semiconductor device.