Abstract: A semiconductor device includes a semiconductor device includes an interposer having a first side and a second side opposite to the first side, wherein the interposer comprises a redistribution layer (RDL), and the RDL comprises a first passivation layer on the first side and a second passivation layer on the second side; at least one active chip mounted on the first passivation layer on the first side through a plurality of first bumps penetrating through the first passivation layer; a molding compound disposed on the first side, the molding compound covering the at least one active chip and a top surface of the first passivation layer; and a plurality of solder bumps mounted on the first passivation layer on the second side.

Abstract: A first semiconductor component and a second semiconductor component are attached together via an adhesion layer so that the first semiconductor component and the second semiconductor component are electrically connected with each other via a through electrode. The through electrode is formed to fill a through hole formed in the second semiconductor component and a through hole formed in a portion the adhesion layer. The through hole formed in the portion the adhesion layer is positioned between the through hole formed in the second semiconductor component and a second connection surface of a first semiconductor component through electrode.

Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a belt supporting module including a first portion that is provided around a first axis, a second portion that is provided around a second axis different from the first axis, a third portion connecting the first and second portions, and a fourth portion connecting the first and second portions and positioned below the third portion. The apparatus further includes a belt provided on the belt supporting module, and configured to rotate around the first axis in a first direction and rotate around the second axis in a second direction reverse to the first direction. The apparatus further includes a wafer supporting module provided on the belt and configured to support a wafer. The apparatus further includes raw material feeding heads provided above the belt and configured to feed a raw material of a film to be formed on the wafer.

Abstract: A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

Abstract: An ultrasonic transducer element chip includes a substrate, a plurality of ultrasonic transducer elements, a wiring part and an additional wiring part. The substrate defines a plurality of openings arranged in an array pattern. Each of the ultrasonic transducer elements is provided in each of the openings. The wiring part is connected to the ultrasonic transducer elements. The additional wiring part is disposed in a peripheral region between an outline of the array pattern of the openings and an outer edge of the substrate in a plan view as viewed along a thickness direction of the substrate. The additional wiring part is electrically insulated from the wiring part. The additional wiring part is longer than a shortest distance between the outline of the array pattern and the outer edge of the substrate in the plan view.

Abstract: The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape.

Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

Abstract: In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

Abstract: A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to expose a portion of the stud and then forming a conductive layer inside the trench and in electrical contact with the stud.

Abstract: A semiconductor memory device includes a first substrate on which a cell region is defined. In the cell region, memory cells are stacked. A second substrate is located above the first substrate, and a peripheral region is defined on the second substrate. One or more conductive lines are located in the peripheral region. The one or more lines extend through the second substrate and couple to the cell region.

Abstract: Provided is a method for producing an electronic component, which is capable of forming a cured adhesive layer easily with high accuracy. The method for producing a curable film electronic component according to the present invention includes an application step in which an adhesive is applied onto a first electronic component body using an ink jet device to form an adhesive layer, a first light irradiation step in which an adhesive layer is irradiated with light from a first light irradiation part, an attachment step in which a second electronic component body is disposed on the adhesive layer irradiated with light and attached, and a step in which the adhesive layer is cured by heating, thereby giving an electronic component, the ink jet device includes an ink tank to store the adhesive, a discharge part, and a circulation flow path part, and in the application step, the adhesive is applied while being circulated in the ink jet device.

Abstract: In the present invention, a half-value width of a rocking curve, an average roughness of a surface, and an average grain diameter are all specified at one time with respect to a Pt layer that constitutes a lower electrode for a piezoelectric element, thereby stably film-forming the Pt layer having excellent characteristics, and stably forming, on the Pt layer, a piezoelectric thin film having excellent characteristics.

Abstract: A method for producing at least one photosensitive infrared detector by assembling a first electronic component including plural photodiodes sensitive to infrared radiation and a second electronic component including at least one electronic circuit for reading the plurality of photodiodes, an infrared detector, and an assembly for producing such a detector, the method including: production, on each one of the first and second components, of a connection face formed at least partially by a silicon oxide (SiO2)-based layer; bonding the first component and the second component by the connection faces thereof, thus performing the direct bonding of the two components. The method can simplify hybridization of heterogeneous components for producing an infrared detector.

Abstract: A method of manufacturing a semiconductor device, includes: providing a first adhesive layer on a support member; providing a film on the first adhesive layer; arranging a semiconductor element on the film; providing a resin layer on the film on which the semiconductor element is arranged, and forming a substrate including the semiconductor element and the resin layer on the film; and separating the film and the substrate from the first adhesive layer.

Abstract: A surface-mount package structure for reducing the ingress of moisture and gases thereto is disclosed. The surface-mount structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to a substrate structure, with a dielectric material positioned between the dielectric layer and the substrate structure to fill in gaps in the surface-mount structure.

Abstract: A device includes a bottom package component that includes a bottom die, and a dam over a top surface of the bottom die. The dam has a plurality of sides forming a partial ring, with an air gap surrounded by the plurality of side portions. The air gap overlaps the bottom die. A top package component is bonded to the bottom package component, wherein the air gap separates a bottom surface of the top package component from the bottom die.

Abstract: Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface material layer containing a support structure on the first semiconductor chip. The heat spreader is positioned proximate the thermal interface material layer. The thermal interface material layer is reflowed to establish thermal contact with both the first semiconductor chip and the heat spreader.

Abstract: The disclosed technology relates to pillar-type microbumps formed on a semiconductor component, such as an integrated circuit chip or an interposer substrate, and a method of forming the pillar-type microbumps. In one aspect, a method of forming the pillar-type microbump on a semiconductor component includes providing the semiconductor component, where the semiconductor component has an upper metallization layer, and the metallization layer has a contact area. The method additionally includes forming a passivation layer over the metallization layer. The method additionally includes forming a plurality of openings through the passivation layer such that the contact area is exposed at a bottom of the openings. The method further includes forming the microbump over the contact area, where the microbump forms an electrical connection with the contact area through the openings.

Abstract: A cavity package is disclosed comprising a metal leadframe, a metal ring connected to the metal leadframe, a plastic body molded to the metal leadframe forming a substrate cavity including an exposed die attach pad of the leadframe for affixing a semiconductor device, exposed lead fingers of the leadframe for wire bonding to the semiconductor device and an external circuit, and an exposed top surface of the metal ring, and a metal cap for closing and encapsulating the substrate cavity. The metal ring is integrated into the pre-molded cavity leadframe for providing an electrical ground path from the metal cap to the die attach pad and permitting attachment of the metal cap to the pre-molded leadframe using solder reflow.

Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.

Abstract: A method of manufacturing a semiconductor device, includes: placing a semiconductor element on an adhesive layer that is placed on a support body having a first through hole; placing a part in an area that includes a portion corresponding to the first through-hole, the portion being on the adhesive layer placed on the support body; forming a substrate on the adhesive layer by forming a resin layer on the adhesive layer, on which the semiconductor element and the part have been placed, the substrate including the semiconductor element, the part, and the resin layer; and detaching the substrate from the adhesive layer by pressing the part through the first through-hole.

Abstract: Contact bumps between a contact pad and a substrate can include recesses and protrusions that can mate with the material of the substrate. The irregular mating surfaces between the contact bumps and the contact pads can enhance the bonding strength of the contacts, for example, against shear and tension forces, especially for flexible systems such as smart cards.

Abstract: Providing a lighting device wherein provisions are made to be able to provide a sufficiently high dielectric strength while retaining the required heat-sink property even when a module substrate with a plurality of LED elements mounted thereon is reduced in size. A lighting device includes a module substrate on an upper surface of which are mounted a plurality of LED elements, a heat-sink member, having a raised portion, for dissipating heat generated by the plurality of LED elements, and an insulating sheet formed with an opening and interposed between a portion of the lower surface of the module substrate and the heat-sink member, and wherein the raised portion is formed so as to be located via the opening in close proximity to the lower surface of a region where the plurality of LED elements are mounted on the module substrate.

Abstract: A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding.

Abstract: A semiconductor structure for forming FinFETs is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the FinFETs on the substrate, and a plurality of even fins of the FinFETs on the substrate between the odd fins of the FinFETs. The odd fins of the FinFETs are defined from the substrate. The even fins of the FinFETs are different from the odd fins of the FinFETs in at least one of the width and the material, and may be further different from the odd fins of the FinFETs in the height.

Abstract: Methods and systems are disclosed for address mapping between die-to-die-port (DTDP) host devices and DTDP expansion devices for combined system-in-package (SiP) solutions. Interconnect circuitry having a plurality of ports is configured to provide communication from the host device to the expansion device so that the expansion device appears to be resident on the host device. Configurable address mapping is used to re-configure the host memory map to include expansion memory map details in a seamless fashion. Further, direct circuit interconnection blocks (e.g., using copper pillar (CuP) connectors) can be used to improve connectivity and performance.

Abstract: Methods and systems are disclosed for interconnecting die-to-die-port (DTDP) host devices and DTDP expansion devices for combined system-in-package (SiP) solutions. Interconnect circuitry having a plurality of ports is configured to provide communication from the host device to the expansion device so that the expansion device appears to be resident on the host device. Further, direct circuit interconnection blocks (e.g., using copper pillar (CuP) connectors) can be used to improve connectivity and performance. In addition, level shift circuitry can be utilized within expansion devices to allow for standardized interconnect signals and supply voltages to be provided by DTDP host devices to DTDP expansion devices.

Abstract: A method of defining poly-silicon growth direction includes Step 1, forming a buffer layer on a substrate; Step 2, forming a regular graphene array; Step 3, forming an amorphous silicon thin film on the buffer layer, which the regular graphene array has formed thereon; and Step 4, transferring the amorphous silicon thin film into poly-silicon with an excimer laser anneal process. The growth direction of the poly-silicon as being formed can be controlled according to the present method of defining poly-silicon growth direction. Accordingly, the grain size of the poly-silicon can be raised.

Abstract: The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.

Abstract: A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.

Abstract: A method and device for emitting electromagnetic radiation using semipolar or nonpolar gallium containing substrates is described where the backside of the substrate includes multiple scribes that reduce stray light leaking.

Abstract: A portable hand-held device is provided having a network interface for sharing images between the device and a network, an image display for displaying the shared images, an orientation sensor for sensing an orientation of the device, and a processor for processing the displayed images based on the sensed device orientation and outputting the processed images to the image display.

Abstract: A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes a first surface and a second surface. The through interposer vias extend from the first surface to the second surface of the interposer. A first die is mounted on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with coefficient of thermal expansion (CTE) similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer.

Abstract: A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.

Abstract: A semiconductor substrate (1) is provided with a structure (3) on an upper side (2), and an additional substrate (4) provided for handling the semiconductor substrate is likewise structured on an upper side (5). The structuring of the additional substrate takes place in at least partial correspondence with the structure of the semiconductor substrate. The structured upper sides of the semiconductor substrate and the additional substrate are positioned such that they face one another and are permanently connected to one another. Subsequently, the semiconductor substrate is thinned from the rear side (6), and the additional substrate is removed at least to such a degree that the structure of the semiconductor substrate is exposed to the extent required for the further use.

Abstract: An embodiment of a method is proposed for indexing electronic devices. The embodiment includes the steps of forming a plurality of first chips in a first wafer, forming a plurality of second chips in a second wafer, forming the electronic devices by coupling each first chip with a corresponding second chip, and forming an index on each electronic device; the index is indicative of a position of the corresponding first chip in the first wafer. In an embodiment, the step of forming an index includes forming a first portion of the index on the first chip, and forming a second portion of the index on the second chip.

Abstract: Embodiments of the present disclosure include methods of forming a semiconductor device. An embodiment is a method for forming a semiconductor device, the method including applying a substrate to a carrier with an adhesive layer between the carrier and the substrate, curing a portion of the adhesive layer, the cured portion surrounding an uncured portion of the adhesive layer, removing the carrier from adhesive layer, removing the uncured portion of the adhesive layer, and removing the cured portion of the adhesive layer.

Abstract: A semiconductor device includes a wiring substrate, a semiconductor chip whose connection terminal is connected to the wiring substrate, an underfill resin formed from a clearance between the wiring substrate and the semiconductor chip to a periphery area of the semiconductor chip, wherein the underfill resin in the periphery area is formed at a same height as an upper surface of the semiconductor chip, an auxiliary member fixed on the semiconductor chip by an adhesive layer, and including a protruding portion which protrudes to an outside from the semiconductor chip, and the protruding portion arranged at least on the underfill resin via the adhesive layer, and a sealing resin sealing the underfill resin and at least side faces of the auxiliary member, wherein respective coefficients of thermal expansion of the auxiliary member and the adhesive layer are larger than a coefficient of thermal expansion of the semiconductor chip.

Abstract: A portable hand-held device is provided having a network interface for sharing images between the device and a network, an image display for displaying the shared images, an orientation sensor for sensing an orientation of the device, and a processor for processing the displayed images based on the sensed device orientation and outputting the processed images to the image display.

Abstract: Methods and systems for adhering microfeature workpieces to support members are disclosed. A method in accordance with one embodiment of the invention includes disposing a first adhesive on a surface of a microfeature workpiece, and disposing a second adhesive on a surface of a support member. The method can further include adhesively attaching the microfeature workpiece to the support member by contacting the first adhesive with the second adhesive while the second adhesive is only partially cured. In further particular embodiments, the first and second adhesives can have different compositions, and the second adhesive can be fully cured after the microfeature workpiece and support member are adhesively attached.

Abstract: A method of manufacturing an integrated circuit (IC) package is provided. The method includes stacking an interposer substrate and a device structure, the interposer substrate having a first plurality of contact members formed on a first surface of the interposer substrate and the device structure having a second plurality of contact members that are exposed at a surface of the device structure, and laminating the interposer substrate and the device structure such that the first plurality of contact members are physically and electrically coupled to the second plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the second plurality of contact members.

Abstract: Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal.

Abstract: A portable hand-held device is provided having a network interface for sharing images between the device and a network, an image display for displaying the shared images, an orientation sensor for sensing an orientation of the device, and a processor for processing the displayed images based on the sensed device orientation and outputting the processed images to the image display.

Abstract: A method of manufacturing a semiconductor chip includes forming a masking member including an opening on a wiring substrate including a chip mounting region so as to align the opening with the chip mounting region, forming an uncured sealing resin on at least the chip mounting region of the wiring substrate, wherein a support film is formed on the uncured sealing resin, removing the support film from the uncured sealing resin, removing the masking member from the wiring substrate so that the uncured sealing resin remains on the chip mounting region, and flip-chip mounting a semiconductor chip onto the chip mounting region with the uncured sealing resin arranged in between. The uncured sealing resin has a higher temperature when removing the masking member than when removing the support film.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a conductive pad in a first substrate, forming an interconnecting structure over the conductive pad and the first substrate, the interconnecting structure comprising a plurality of metal layers disposed in a plurality of dielectric layers, bonding a die to a first side of the interconnecting structure, and etching the first substrate from a second side of the interconnecting structure, the etching exposing a portion of the conductive pad.

Abstract: A method of manufacturing a semiconductor element includes forming a first bonding layer containing a metal, which forms a eutectic crystal with Au, on a first substrate to provide a first laminated body. The method also includes forming an element structure layer having a semiconductor layer on a second substrate. The method also includes forming a second bonding layer on the element structure layer to provide a second laminated body. The second bonding layer has a metal underlayer containing a metal, which forms a eutectic crystal with Au. The second bonding layer also has a surface layer that contains Au. The method also includes performing heating pressure-bonding on the first and second laminated bodies with the first and second bonding layers facing each other. The heating temperature of the second substrate in the heating pressure-bonding is higher than the heating temperature of the first substrate.

Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.

Abstract: Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.

Abstract: In one embodiment, a semiconductor component, such as a wavelength converter wafer, is described wherein the wavelength converter is bonded to an adjacent inorganic component with a cured bonding layer comprising polysilazane polymer. The wavelength converter may be a multilayer semiconductor wavelength converter or an inorganic matrix comprising embedded phosphor particles. In another embodiment, the semiconductor component is a pump LED component bonded to an adjacent component with a cured bonding layer comprising polysilazane polymer. The adjacent component may the described wavelength converter(s) or another component comprised of inorganic material(s) such as a lens or a prism. Also described are methods of making semiconductor components such as wavelength converters and LED's.

Abstract: The present invention discloses a three-dimensional vertically interconnected structure and a fabricating method therefor. The structure comprises at least two layers of chips which are stacked in sequence or stacked together face to face. An adhesive material is used for adhesion between adjacent layers of the chips while each layer of the chips contains a substrate layer and a dielectric layer from bottom to top. A front surface of the chip has a first concave, which is filled with metal to form a first electrical conductive ring that connects to microelectronic devices inside the chip via a redistribution layer. A first through layers of chips hole with a first micro electrical conductive pole inside, penetrates the stacked chips. The structure in the present invention enhances the electric interconnection and the bonding between adjacent layers of chips while the instant fabricating method simplifies the process and increases the yield.