Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.

Abstract: The present disclosure provides a die assembly. The die assembly includes a first die, a second die and a third die stacked together. The first die includes a plurality of first metal lines facing a plurality of second metal lines of the second die, and a second substrate beneath the second metal lines faces a plurality of third metal lines of the third die. The die assembly further includes at least one first plug, a first redistribution layer and a second redistribution layer. The first plug penetrates through the second substrate to connect to at least one of the second metal lines. A first redistribution layer physically connects at least one of the first metal lines to at least one of the second metal lines, and a second redistribution layer physically connects at least one of the third metal lines to the first plug.

Abstract: A semiconductor chip includes a single-crystal substrate and a metal electrode on the bottom surface of the substrate. The metal electrode has a region in which a first metal is exposed and a region in which a second metal is exposed, the second metal having a standard electrode potential different from that of the first metal.

Abstract: A method for fabricating a radio-frequency device involves providing a semiconductor wafer including a transistor device, applying a form of sacrificial material on the semiconductor wafer, applying an interface material over the form of sacrificial material, and removing at least a portion of the form of sacrificial material to form a cavity at least partially covered by the interface material.

Abstract: A method for fabricating a semiconductor die involves providing a semiconductor substrate, forming a plurality of active devices and a plurality of passive devices over the semiconductor substrate, forming one or more electrical connections to the plurality of active devices and the plurality of passive devices, forming one or more dielectric layers over at least a portion of the electrical connections, applying an interface material over at least a portion of the one or more dielectric layers, removing portions of the interface material to form a plurality of trenches, and covering at least a portion of the interface material and the plurality of trenches with a substrate layer to form a plurality of radio-frequency isolation cavities.

Abstract: A semiconductor chip includes a single-crystal substrate and a metal electrode on the bottom surface of the substrate. The metal electrode has a region in which a first metal is exposed and a region in which a second metal is exposed, the second metal having a standard electrode potential different from that of the first metal.

Abstract: A silicon etching method of etching a silicon substrate to form silicon trenches having different width dimensions includes: S1, providing a silicon substrate; S2, depositing a mask layer on the silicon substrate; S3, corroding the mask layer to form windows having different width dimensions, wherein a mask layer having a certain thickness is reserved at least at a bottom portion of a window having a non-minimum width dimension, such that all the silicon trenches have the same depth after step S4; and S4, corroding the mask layer at the bottom portion of the window and the silicon substrate to form the silicon trenches. The mask layer having a certain thickness is reserved at the bottom portion of the window having the non-minimum width dimension, a relatively large window is protected, and a relatively small window is etched first, so that the finally obtained silicon trenches have the same depth.

Abstract: A method including introducing a dopant into a region of a substrate, etching a deep trench in the substrate through the region, gettering impurities introduced during etching of the deep trench using a pentavalent ion formed from a reaction between an element of the substrate and the dopant, wherein the charge of the pentavalent ion attracts the impurities, and filling the deep trench with a conductive material.

Abstract: A system for manipulating dislocations on semiconductor devices, includes a moveable laser configured to generate a laser beam locally on a surface portion of the semiconductor body having a plurality of dislocations, the moveable laser being characterized as having a scan speed, the moveable laser manipulates the plurality of dislocations on the surface portion of the semiconductor body by adjusting the temperature and the scan speed of the laser beam.

Abstract: A method for manipulating dislocations from a semiconductor device includes directing a light-emitting beam locally onto a surface portion of a semiconductor body that includes active regions of the semiconductor device and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam. Manipulating the plurality of dislocations includes directly scanning the plurality of dislocations with the light-emitting beam to manipulate a location of each of the plurality of dislocations on the surface portion of the semiconductor body by adjusting a temperature of the surface portion of the semiconductor body corresponding to the plurality of dislocations and adjusting a scan speed of the a light-emitting beam.

Abstract: A method of fabricating a polycrystalline silicon layer includes: forming an amorphous silicon layer on a substrate; crystallizing the amorphous silicon layer into a polycrystalline silicon layer using a crystallization-inducing metal; forming a metal layer pattern or metal silicide layer pattern in contact with an upper or lower region of the polycrystalline silicon layer corresponding to a region excluding a channel region in the polycrystalline silicon layer; and annealing the substrate to getter the crystallization-inducing metal existing in the channel region of the polycrystalline silicon layer to the region in the polycrystalline silicon layer having the metal layer pattern or metal silicide layer pattern. Accordingly, the crystallization-inducing metal existing in the channel region of the polycrystalline silicon layer can be effectively removed, and thus a thin film transistor having an improved leakage current characteristic and an OLED display device including the same can be fabricated.

Abstract: A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.

Abstract: The present application relates to a multiple component which is to be subsequently individualized by forming components containing active structures, in addition to a corresponding component which can be used in microsystem technology systems. The multiple component and/or component comprises a flat substrate and also a flat cap structure which are bound to each other such that they surround at least one first and one second cavity per component, which are sealed against each other and towards the outside. The first of the two cavities is provided with getter material and due to the getter material has a different internal pressure and/or a different gas composition than the second cavity. The present application also relates to a method for producing the type of component and/or components for which gas mixtures of various types of gas have a different absorption ratio in relation to the getter material.

Abstract: The semiconductor device includes a silicon substrate having a channel region, a gate electrode formed over the channel region, buried semiconductor regions formed in a surface of the silicon substrate on both sides of the gate electrode, for applying to the surface of the silicon substrate a first stress in a first direction parallel to the surface of the silicon substrate, and stressor films formed on the silicon substrate between the channel region and the buried semiconductor regions in contact with the silicon substrate, for applying to the silicon substrate a second stress in a second direction which is opposite to the first direction.

Abstract: A method for protecting, against laser attacks, an integrated circuit chip formed inside and on top of a semiconductor substrate and including in the upper portion of the substrate an active portion in which are formed components, this method including the steps of: forming in the substrate a gettering area extending under the active portion, the upper limit of the area being at a depth ranging between 5 and 50 ?m from the upper surface of the substrate; and introducing diffusing metal impurities into the substrate.

Abstract: Silicon wafers wherein slip dislocations and warpages during device production are suppressed, contain BMDs with an octahedral shape, and of BMDs at a depth greater than 50 ?m from the surface of the wafer, the density of BMDs with diagonal size of 10 nm to 50 nm is ?1×1012/cm3, and the density of BSFs is ?1×108/cm3. The present silicon wafers preferably have an interstitial oxygen concentration of 4×1017 atoms/cm3 to 6×1017 atoms/cm3, and a density of BMDs with diagonal size of ?200 nm of not more than 1×107/cm3.

Abstract: A method of processing a semiconductor wafer includes preheating the wafer to a preheating temperature that is less than a peak temperature, heating the wafer from the preheating temperature to the peak temperature at a first ramp rate that averages about 100° C. per second or more, and, immediately after heating the wafer from the preheating temperature to the peak temperature, cooling the wafer at a second ramp rate that averages about ?70° C. per second or more from the peak temperature to the preheating temperature, wherein the peak temperature is about 1,100° C. or more.

Abstract: A device and a device manufacturing process. First, a gettering layer is formed on the bottom surface of a silicon substrate. Gates having a MOS structure are then formed on the principal surface of the silicon substrate, and the gettering layer is removed. According to this manufacturing method, the formation of the gates having a MOS structure is performed such that the gettering layer getters dissolved oxygen present in the silicon substrate. This reduces the concentration of dissolved oxygen in the silicon substrate, resulting in improved device characteristics.

Abstract: A method of producing an epitaxial substrate for a solid-state imaging device, comprising: forming a gettering sink by injecting laser beam to a semiconductor substrate through one surface thereof, condensing the laser beam to an arbitrarily selected portion of the semiconductor substrate, thereby causing multi-photon absorption process to occur in the portion, and forming a gettering sink having a modified crystal structure; and epitaxially growing at least two epitaxial layers on the semiconductor substrate in which the gettering sink is formed.

Abstract: A semiconductor device includes a p-type semiconductor layer and an n-type semiconductor layer that are joined by sandwiching a depletion layer with a thickness that allows transmission of a plurality of electrons and holes by direct-tunneling.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a first semiconductor layer formed over the first insulation layer. At least one gettering region is formed in at least one of the first insulating layer and the first semiconductor layer. The gettering region includes a plurality of gettering sites, and at least one gettering site includes one of a precipitate, a dispersoid, an interface with the dispersoid, a stacking fault and a dislocation.

Abstract: A semiconductor device includes a p-type semiconductor layer and an n-type semiconductor layer that are joined by sandwiching a depletion layer with a thickness that allows transmission of a plurality of electrons and holes by direct-tunneling.

Abstract: A method for removing impurities from at least one semiconductor device layer during manufacturing of a semiconductor device is disclosed. The semiconductor device layer has a compound semiconductor material and/or germanium. Each heating process performed during the manufacturing of the semiconductor device after provision of the semiconductor device layer has a low thermal budget determined by temperatures equal to or lower than about 900° C. and time periods equal to or lower than about 5 minutes. In one aspect, the method includes providing a germanium gettering layer with a higher solubility for the impurities than the semiconductor device layer. The germanium gettering layer is provided at least partly in direct or indirect contact with the at least one semiconductor device layer, such that impurities can diffuse from the at least one semiconductor device layer to the germanium gettering layer.

Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Abstract: Method for producing nanostructures comprising: a step of providing a substrate (100) having a buried barrier layer (2) and above said barrier layer (2) a crystalline film (5) provided with a network of crystalline defects and/or stress fields (12) in a crystalline zone (13), one or several steps of attacking the substrate (100), of which a preferential attack either of the crystalline defects and/or the stress fields, or the crystalline zone (13) between the crystalline defects and/or the stress fields, said attack steps enabling the barrier layer (2) to be laid bared locally and protrusions (7) to be formed on a nanometric scale, separated from each other by hollows (7.1) having a base located in the barrier layer, the protrusions leading to nanostructures (7, 8).

Abstract: A flat panel display device, more particularly, an Organic Light Emitting Diode (OLED) display device having uniform electrical characteristics and a method of fabricating the same include: a thin film transistor of which a semiconductor layer including a source, a drain, and a channel region formed in a super grain silicon (SGS) crystallization growth region; a capacitor formed in an SGS crystallization seed region; and an OLED electrically connected to the thin film transistor. Further, a length of the channel region of the silicon layer is parallel with the growth direction in the SGS growth region to improve the electrical properties thereof.

Abstract: A method for generating patterned strained regions in a semiconductor device is provided. The method includes directing a light-emitting beam locally onto a surface portion of a semiconductor body; and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam, the light-emitting beam being characterized as having a scan speed, so as to produce the patterned strained regions.

Abstract: A method for forming gettering sites and gettering impurities in a substrate layer includes producing a first masking layer over the substrate layer and patterning the masking layer to define openings at locations where trenches will be formed in the substrate layer at a later time. Ions are then implanted into the substrate layer to produce gettering sites. The gettering sites are disposed at a depth in the substrate layer such that the sites are removed when the trenches are formed. The first masking layer is removed and impurities driven to the gettering sites by thermally processing the substrate layer. A second masking layer is then produced over the substrate layer and patterned to define openings at locations where the trenches will be formed. The substrate layer is etched to produce the trenches. The gettering sites and gettered impurities are removed when the trenches are etched into the substrate layer.

Abstract: A thin film transistor includes a substrate, a semiconductor layer provided on the substrate and crystallized by using a metal catalyst, a gate electrode insulated from and disposed on the semiconductor layer, and a getter layer disposed between the semiconductor layer and the gate electrode and formed with a metal oxide having a diffusion coefficient that is less than that of the metal catalyst in the semiconductor layer.

Abstract: By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in highly scaled P-channel transistors.

Abstract: A method for manufacturing a light emitting device, includes: forming a first multilayer body including a first substrate, a first semiconductor layer provided on the first substrate and having a light emitting layer, and a first metal layer provided on the first semiconductor layer; forming a second multilayer body including a second substrate having a thermal expansion coefficient different from a thermal expansion coefficient of the first substrate, and a second metal layer provided on the second substrate; a first bonding step configured to heat the first metal layer and the second metal layer being in contact with each other; removing the first substrate after the first bonding step; and a second bonding step configured to perform, after the removing, heating at a temperature higher than a temperature of the first bonding step.

Abstract: Method of manufacturing image sensors having a plurality of gettering regions. In the method, a gate electrode may be formed on a semiconductor substrate. A source/drain region may be formed in the semiconductor substrate to be overlapped with the gate electrode. A gettering region may be formed in the semiconductor substrate to be adjacent to the source/drain region.

Abstract: Gate electrodes are formed on a substrate. A gate insulation film is formed so as to cover the gate electrodes. A semiconductor layer is formed in regions on the gate insulation film in a region which overlap with at least the gate electrodes. Plasma treatment is applied to the semiconductor layer using a gas which contains a dopant thus increasing impurity concentration of a surface layer of the semiconductor layer. A conductive film is formed on the surface layer of the semiconductor layer to which the plasma treatment is applied. A source electrode and a drain electrode are formed by etching the conductive film.

Abstract: A method includes providing a substrate including a non-insulative, silicon-including region for silicidation, the substrate including one or more contaminants at a top surface thereof. A getter layer is deposited over the non-insulative, silicon-including region, the getter layer reacting with at least one of the one or more contaminants in the non-insulative, silicon-including region at approximately room temperature. The getter layer is removed, and siliciding of the non-insulative, silicon-including region is performed.

Abstract: An object of an embodiment of the present invention to be disclosed is to prevent oxygen from being taken in a single crystal semiconductor layer in laser irradiation even when crystallinity of the single crystal semiconductor layer is repaired by irradiation with a laser beam; and to make substantially equal or reduce an oxygen concentration in the semiconductor layer after the laser irradiation comparing before the laser irradiation. A single crystal semiconductor layer which is provided over a base substrate by bonding is irradiated with a laser beam, whereby the crystallinity of the single crystal semiconductor layer is repaired. The laser irradiation is performed under a reducing atmosphere or an inert atmosphere.

Abstract: A method of improving the intrinsic gettering ability of a wafer is described. A first annealing step is performed to the wafer at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. A second annealing step is performed to the wafer, at a second temperature higher than the first temperature, in the atmosphere.

Abstract: It is shown in the invention a method for manufacturing a semiconductor wafer structure with an active layer for impurity removal, which method comprises phases of depositing a first layer on a first wafer surface for providing an active layer, an optional phase of preparation for said first layer for next phase, growing thermal oxide layer on a second wafer, bonding said first and second wafers into a stack, annealing the stack for a crystalline formation in said thermal oxide layer as a second layer, and thinning said first wafer to a pre-determined thickness. The invention concerns also a wafer manufactured according to the method, chip that utilizes such a wafer structure and an electronic device utilizing such a chip.

Abstract: A semiconductor device includes a first conductive type SiC semiconductor substrate; a second conductive type well formed on the SiC semiconductor substrate; a first impurity diffusion layer formed by introducing a first conductive type impurity so as to be partly overlapped with the well in a region surrounding the well; a second impurity diffusion layer formed by introducing the first conductive type impurity in a region spaced apart for a predetermined distance from the impurity diffusion layer in the well; and a gate electrode opposed to a channel region between the first and the second impurity diffusion layers with gate insulating film sandwiched therebetween.

Abstract: Gate electrodes are formed on a substrate. A gate insulation film is formed so as to cover the gate electrodes. A semiconductor layer is formed in regions on the gate insulation film in a region which overlap with at least the gate electrodes. Plasma treatment is applied to the semiconductor layer using a gas which contains a dopant thus increasing impurity concentration of a surface layer of the semiconductor layer. A conductive film is formed on the surface layer of the semiconductor layer to which the plasma treatment is applied. A source electrode and a drain electrode are formed by etching the conductive film.

Abstract: The specification teaches a system for manufacturing microelectronic, microoptoelectronic or micromechanical devices (microdevices) in which a contaminant absorption layer improves the life and operation of the microdevice. In an embodiment, a system for manufacturing the devices includes efficiently integrating a getter material in multiple microdevices.

Abstract: In an example embodiment of the method of manufacturing an epitaxial semiconductor substrate, a gettering layer is grown over a semiconductor substrate. An epitaxial layer may then be formed over the gettering layer, and a semiconductor device may be formed on the epitaxial layer.

Abstract: First, a base structure provided with the main parts of a memory cell is prepared, and a lower electrode comprising a polycrystalline silicon film is thereafter formed on the base structure. Next, the surface of the lower electrode is thermally nitrided at a predetermined temperature to form a silicon nitride film. In the thermal nitridation of the lower electrode, the temperature is increased to a predetermined nitriding temperature, after which the temperature is reduced at a rate that is more gradual than usual. Aluminum oxide (Al2O3) or another metal oxide dielectric film is thereafter formed as the capacitive insulating film on the lower electrode, and an upper electrode is formed on the capacitive insulating film.

Abstract: A semiconductor die package. Embodiments of the package can include a substrate with solid conductive pins disposed throughout. A semiconductor die can be attached to a surface of the substrate. Electrical connection to the semiconductor die can be provided by the solid conductive pins.

Abstract: A semiconductor package includes a substrate having a first surface portion in a cavity. The first surface portion includes an artificially formed grass structure. The package includes a getter film formed over the grass structure.

Abstract: A method of recycling monitor wafers. The method includes: (a) providing a semiconductor wafer which includes a dopant layer extending from a top surface of the wafer into the wafer a distance less than a thickness of the wafer, the dopant layer containing dopant species; after (a), (b) attaching an adhesive tape to a bottom surface of the wafer; after (b), (c) removing the dopant layer; and after (c), (d) removing the adhesive tape.

Abstract: A method for manufacturing an SOI substrate, including the steps of implanting hydrogen ions from a main surface of a single-crystal silicon substrate having an interstitial oxygen concentration which is equal to or below 1×1018 cm?3; performing an activation treatment with respect to the main surface of at least one of a transparent insulative substrate and the silicon substrate; bonding the main surface of the transparent insulative substrate to the main surface of the silicon substrate at a room temperature; performing a heat treatment with respect to the bonded substrate at a temperature falling within the range of 350° C. to 550° C. and having a cooling rate after the heat treatment that is equal to or below 5° C./minute; and mechanically delaminating a silicon thin film from the silicon substrate to form a silicon film on the main surface of the transparent insulative substrate.

Abstract: The specification teaches a system for manufacturing microelectronic, microoptoelectronic or micromechanical devices (microdevices) in which a contaminant absorption layer improves the life and operation of the microdevice. In an embodiment, a system for manufacturing the devices includes efficiently integrating a getter material in multiple microdevices.

Abstract: A method of forming a semiconductor device includes forming a high dielectric constant material over a semiconductor substrate, forming a conductive material over the high dielectric constant material, and performing an anneal in a non-oxidizing ambient using ultraviolet radiation to remove defects in the high dielectric constant material. Examples of a non-oxidizing ambient include for example nitrogen, deuterium, a deuterated forming gas (N2/D2), helium, argon or a combination of any two or more of these. Additional anneals using ultraviolet radiation may be performed. These additional anneals may occur in non-oxidizing or oxidizing ambients.

Abstract: A method of forming an integrated circuit, the method including forming at least one patterned gate stack on a substrate including a substrate surface; forming an amorphous substrate region in the substrate by implanting a first material in the substrate; and implanting a getter material to form a getter region within the amorphous substrate region; forming doped implant regions extending from the substrate surface in to the substrate by implanting a second material; and thermally recrystallizing the amorphous substrate region.

Abstract: A thin film transistor array substrate and a method for manufacturing the same is disclosed, in which it is possible to prevent mobile ions contained in a substrate from penetrating into a semiconductor layer by the gettering effect or neutralization in case soda lime glass is used for the substrate. The method includes forming a buffer layer on a substrate; doping impurity ions in the buffer layer; and forming a pixel electrode and a thin film transistor including a semiconductor layer on the buffer layer.