Abstract: A chip module assembly includes a CO2 getter exposed through a gas-permeable membrane to a chip cavity of a chip module. One or more chips is/are enclosed within the cavity. The CO2 getter comprises a liquid composition including 1,8-diaza-bicyclo-[5,4,0]-undec-7-ene (DBU) in a solvent that includes an alcohol, preferably, 1-hexanol. In one embodiment, a sheet of gas-permeable membrane is heat-welded to form a pillow-shaped bag in which the liquid composition is sealed. The pillow-shaped bag containing the liquid composition is preferably disposed in a recess of a heat sink and exposed to the cavity through a passage between the recess and the cavity. The CO2 getter can remove a relatively large amount of carbon dioxide from the cavity, and thus effectively prevents solder joint corrosion. For example, based on the formula weights and densities of the DBU and 1-hexanol, 200 g of the liquid composition can remove over 34 g of carbon dioxide.

Abstract: To provide a back-illuminated solid-state imaging device able to suppress a crystal defect caused by a metal contamination in a process and to suppress a dark current to improve quantum efficiency, a camera including the same and a method of producing the same, having the steps of forming a structure including a substrate, a first conductive type epitaxial layer and a first conductive type impurity layer, the first conductive type epitaxial layer being formed on the substrate to have a first impurity concentration, and the first conductive type impurity layer being formed in a boundary region to have a second impurity concentration higher than the first impurity concentration of the epitaxial layer; forming a second conductive type region storing a charge generated by a photoelectric conversion in the epitaxial layer; forming an interconnection layer on the epitaxial layer; and removing the substrate.

Abstract: A method includes: forming a transistor gate over a first substrate and at least one first dummy structure within the first substrate; forming an interlayer dielectric (ILD) layer over the gate transistor, the ILD layer including at least one contact structure formed therein and making electrical contact with the transistor gate and at least one first conductive structure formed therethrough at least partially over a surface of the dummy structure; forming a passivation layer over the ILD layer, the passivation layer comprising at least one first pad structure formed therein and making electrical contact with the conductive structure; bonding the first substrate with a second substrate; removing at least a portion of the first dummy structure, thereby forming a first opening; and forming a conductive material within the first opening for formation of a second conductive structure, the second conductive structure being electrically coupled to the first conductive structure.

Abstract: A limited access space inspection system comprising: an imaging device for imaging a region in the limited access space, a mounting for mounting the imaging device to scan about the limited access space and a scanning control unit, associated with the imaging device, for controlling the imaging device to scan about the limited access space. The device is particularly useful for improving by automation, security checks customs checks and safety checks involving such awkward to access spaces.

Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

Abstract: One aspect of this disclosure relates to a method for creating a gettering site in a semiconductor wafer. In various embodiments, a predetermined arrangement of a plurality of holes is formed in the semiconductor wafer through a surface of the wafer. The wafer is annealed such that the wafer undergoes a surface transformation to transform the arrangement of the plurality of holes into a predetermined arrangement of at least one empty space of a predetermined size within the wafer to form the gettering site. One aspect relates to a semiconductor wafer. In various embodiments, the wafer includes at least one device region, and at least one gettering region located proximate to the at least one device region. The gettering region includes a precisely-determined arrangement of a plurality of precisely-formed voids that are formed within the wafer using a surface transformation process. Other aspects and embodiments are provided herein.

Abstract: A comprehensive vehicle anti-theft and alarm system that immediately notifies a vehicle owner when a vehicle is being tampered with. Notification is accomplished via wireless signal to the owners' cell phone, personal digital assistant (PDA), laptop or desktop computer, or other electronic device, or to the police. The signal can be used to provide an audible, inaudible (e.g., vibratory), or visual alert, depending upon the mode the owner has chosen. In addition, the system transmits a photograph or image of the person tampering with the vehicle. The transmitted image(s) may be periodically refreshed. In alternate embodiments of the system, realtime streaming video may be transmitted. The anti-theft system typically includes a GPS receiver that tracks the movements of the vehicle in the event it is actually stolen. Finally, the system includes a communications link that allows the owner to speak directly to the unauthorized occupant of the vehicle.

Abstract: A method of fabricating a p-type thin film transistor (TFT) includes: performing a first annealing process on a substrate to diffuse a metal catalyst through a capping layer into a surface of an amorphous silicon layer, and to crystallize the amorphous silicon layer to a polycrystalline silicon layer due to the diffused metal catalyst; removing the capping layer; patterning the polycrystalline silicon layer to form a semiconductor layer; forming a gate insulating layer and a gate electrode on the substrate; implanting p-type impurity ions into the semiconductor layer; and implanting a gettering material into the semiconductor layer and performing a second annealing process to remove the metal catalyst. Herein, the p-type impurity ions are implanted at a dose of 6×1013/cm2 to 5×1015/cm2, and the gettering material is implanted at a dose of 1×1011/cm2 to 3×1015/cm2.

Abstract: Ultra-low leakage current backside-illuminated semiconductor photodiode arrays are fabricated using a method of formation of a transparent, conducting bias electrode layer that avoids high-temperature processing of the substrate after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or impurities introduced during elevated temperature processing subsequent to gettering can be kept extremely low. An optically transparent, conductive bias electrode layer, serving as both an optical window and an ohmic backside equipotential contact surface for the photodiodes, is fabricated by etching through the polysilicon gettering layer and a portion of the thickness of heavily-doped crystalline silicon layer formed within, and near the back of, the substrate during the gettering process.

Abstract: A method of fabricating a via and a trench is disclosed. A disclosed method comprises: forming a via hole and a trench in a interlayer dielectric layer on a semiconductor substrate where a predetermined device is formed; depositing a thin Hf layer on the substrate; performing a thermal treatment of the substrate to getter oxygen and forming a barrier layer; and filling copper into the via hole and the trench.

Abstract: A high-density impurity diff-used layer of an identical conduction type to the semiconductor substrate on which the impurity is doped higher in density than the semiconductor substrate around the diffuse resistance region is provided, one side of the electrodes is formed extending to the high-density impurity diffused layer and the diffused resistance region and the high-density impurity diff-used layer are connected in a semiconductor strain gauge that is formed on the surface of the semiconductor substrate of a fixed conduction type and is provided with the diffused resistance region of opposite conduction type to the semiconductor substrate and is provided with electrodes on both ends of the diffused resistance region.

Abstract: There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. An amorphous semiconductor thin film is irradiated with ultraviolet light or infrared light, to obtain a crystalline semiconductor thin film (102). Then, the crystalline semiconductor thin film (102) is subjected to a heat treatment at a temperature of 900 to 1200° C. in a reducing atmosphere. The surface of the crystalline semiconductor thin film is extremely flattened through this step, defects in crystal grains and crystal grain boundaries disappear, and the single crystal semiconductor thin film or substantially single crystal semiconductor thin film is obtained.

Abstract: A method for making a semiconductor device is described. That method includes forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a gate electrode to be formed on the dielectric layer, and then a gate electrode is formed on the dielectric layer.

Abstract: The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has at least a surface layer of high resistivity, the layer having an interstitial oxygen content which renders it incapable of forming thermal donors in an amount sufficient to affect resistivity upon being subjected to a conventional semiconductor device manufacturing process. The present invention further directed to a silicon on insulator structure derived from such a wafer.

Abstract: On a silicon layer of an SOI wafer is defined a semiconductor device-forming region to form semiconductor devices thereon and an insulating region to electrically insulate the semiconductor device-forming region. Then, a mask layer is formed of nitride by means of photolithography so as to cover the semiconductor device-forming region. Then, an impurities-removing layer is formed by means of well known technique so as to cover the mask layer and embed the gaps between the adjacent masks of the mask layer. The impurities of the silicon layer of the SOI wafer are absorbed and removed by the distorted layer, the grain boundaries and the lattice defects of the impurities-removing layer.

Abstract: A process for removing a contaminant selected from among copper, nickel, and a combination thereof from a silicon wafer having a surface and an interior. The process comprises cooling the silicon wafer in a controlled atmosphere from a temperature at or above an oxidation initiation temperature and initiating a flow of an oxygen-containing atmosphere at said oxidation initiation temperature to create an oxidizing ambient around the silicon wafer surface to form an oxide layer on the silicon wafer surface and a strain layer at an interface between the oxide layer and the silicon wafer interior. The cooling of the wafer is also controlled to permit diffusion of atoms of the contaminant from the silicon wafer interior to the strain layer. Then the silicon wafer is then cleaned to remove the oxide layer and the strain layer, thereby removing said contaminant having diffused to the strain layer.

Abstract: A method of manufacturing a semiconductor device on a silicon-on-insulator wafer including a silicon active layer having at least two die pads formed thereon, the at least two die pads separated by at least one scribe lane, including the steps of forming at least one cavity through the silicon active layer in the at least one scribe lane; forming at least one gettering plug in each said cavity, each said gettering plug comprising doped fill material containing a plurality of gettering sites; and subjecting the wafer to conditions to getter at least one impurity into the plurality of gettering sites.

Abstract: One aspect of this disclosure relates to a method for creating a gettering site in a semiconductor wafer. In various embodiments, a predetermined arrangement of a plurality of holes is formed in the semiconductor wafer through a surface of the wafer. The wafer is annealed such that the wafer undergoes a surface transformation to transform the arrangement of the plurality of holes into a predetermined arrangement of at least one empty space of a predetermined size within the wafer to form the gettering site. One aspect relates to a semiconductor wafer. In various embodiments, the wafer includes at least one device region, and at least one gettering region located proximate to the at least one device region. The gettering region includes a precisely-determined arrangement of a plurality of precisely-formed voids that are formed within the wafer using a surface transformation process. Other aspects and embodiments are provided herein.

Abstract: The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has at least a surface layer of high resistivity, the layer having an interstitial oxygen content which renders it incapable of forming thermal donors in an amount sufficient to affect resistivity upon being subjected to a conventional semiconductor device manufacturing process. The present invention further directed to a silicon on insulator structure derived from such a wafer.

Abstract: An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconductor region; and a second conductive type first diffusion layer constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which a germanium concentration is continuously increased from a drain region side to a source region side, and an impurity concentration immediately below the gate electrode in the first conductive type semiconductor region being continuously increased from the source region side to the drain region side in accordance with the germanium concentration in the gate electrode.

Abstract: An N?-type silicon substrate (1) has a bottom surface and an upper surface which are opposed to each other. In the bottom surface of the N?-type silicon substrate (1), a P-type impurity diffusion layer (3) of high concentration is entirely formed by diffusing a P-type impurity. In the upper surface of the N?-type silicon substrate (1), a P-type isolation region (2) is partially formed by diffusing a P-type impurity. The P-type isolation region (2) has a bottom surface reaching an upper surface of the P-type impurity diffusion layer (3). As viewed from the upper surface side of the N?-type silicon substrate (1), the P-type isolation region (2) is formed, surrounding an N? region (1a) which is part of the N?-type silicon substrate (1). The N? region (1a) surrounded by the P-type isolation region (2) is defined as an element formation region of the N?-type silicon substrate (1).

Abstract: A liquid crystal display device is provided wherein an adhesive force between a seal and a lower plate is improved upon bonding of an upper plate to the lower plate. In high aperture liquid crystal display panels, organic protective films are used to reduce dielectric constants. However, the seal, used when bonding the upper and lower plates of the liquid crystal panel, generally do not adhere well to organic materials. In this invention, holes are generated in the organic protective film so that the seal bonds with inorganic materials such as the lower glass plate or the gate insulating film.

Abstract: A driver circuit integration type (monolithic type) active matrix display device having high performance is formed by using thin film transistors (TFT). While a nickel element is added t an amorphous silicon film 203, a head treatment is carried out to thereby crystallize the amorphous silicon film. Further, by carrying out a heat treatment in an oxidizing atmosphere containing a halogen element, a thermal oxidation film 209 is formed. At this time, cyrstallinity is improved and gettering of the nickel element proceeds. TFTs are formed by using the thus obtained crystalline silicon film, and various circuits are constituted by using the TFTs, so that a data driver circuit capable of driving the active matrix circuit having the dot number of fifty thousands to three millions can be obtained.

Abstract: A semiconductor device is manufactured by a method in which the number of heat treatments at a high temperature (600° C. or higher) is reduced to thereby achieve a process at a low temperature (600° C. or lower), and a simplified process and improvement in throughput are realized. An impurity region to which a rare gas element (also called a rare gas) is added is formed on a semiconductor film of a crystalline structure by using a mask. Gettering is performed in such a manner that a metallic element contained in the semiconductor film is caused to segregate in the impurity region by heat treatment. The impurity region is thereafter used as a source or drain region.

Abstract: In the fabrication of gate oxides in IC process, a suitable cleaning/etching process is required to remove the native oxides and reduce surface microroughness in addition to standard RCA cleaning. For ultrathin oxide thickness (<10 nm), it is an important issue to have a native-oxide-free and H-passivated silicon (Si) surface to ensure high breakdown field, high charge-to-breakdown, and low leakage current. According to these concepts, we propose an invention with a simple two-step hydrogen fluoride (HF) etching process to improve the electrical properties of liquid-phase deposited fluorinated silicon oxides (LPD-SiOF), including effective removal of native oxides, lowering of interface trap density (˜1010 eV−1 cm−2), reduction of surface microroughness (Ra=0.1 nm), and raising of breakdown field (˜9.7 MV/cm). Furthermore, rapid thermal annealing (RTA) is also used to further improve the oxide quality.

Abstract: In order to obtain a method of evaluating a crystal defect which allows crystal defects generated in a thin film SOI layer or a thin film surface layer to be evaluated using an in-line test, an SOI layer 3 has silicide regions 8 formed in the evaluation region consequently upon generation of crystal defects generated in the SOI layer 3. The silicide regions 8 are regions silicided as a result of the crystal defects having gettered metals which are contained in a transition layer 10 and diffuse into the SOI layer 3 upon a heat treatment. A laser beam is irradiated to the evaluation region via the transition layer 10 and the silicon oxide film 6. By monitoring a current flowing between first and second probes using an ampere meter while scanning the evaluation region with a laser beam, it is possible to evaluate the crystal defects in the evaluation region.

Abstract: After a catalyst element is introduced into an amorphous silicon film, the amorphous silicon film is converted into a crystalline silicon film by a heat treatment and laser irradiation. After a resist mask is formed on the crystalline silicon film, boron and phosphorus are selectively introduced into the crystalline silicon film to form a gettering region therein. Then, a heat treatment is performed at 500°-650° C., whereby the catalyst element in a gettering subject region is gettered to the gettering region. As a result, a crystalline semiconductor film is obtained in which the catalyst element concentration is reduced. The crystalline semiconductor film is patterned into a semiconductor layer of a semiconductor device.

Abstract: Ultra-low leakage current backside-illuminated semiconductor photodiode arrays are fabricated using a method of formation of a transparent, conducting bias electrode layer that avoids high-temperature processing of the substrate after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or impurities introduced during elevated temperature processing subsequent to gettering can be kept extremely low. An optically transparent, conductive bias electrode layer, serving as both an optical window and an ohmic backside equipotential contact surface for the photodiodes, is fabricated by etching through the polysilicon gettering layer and a portion of the thickness of heavily-doped crystalline silicon layer formed within, and near the back of, the substrate during the gettering process.

Abstract: The present invention relates to a method of manufacturing a silicon-on-insulator substrate, comprising the steps of (1) providing a silicon-on-insulator semiconductor wafer having at least one surface of a silicon film; (2) implanting an inert atom into the at least one surface to form a damaged surface layer including a gettering site on the silicon film and to leave an undamaged region of the silicon film; (3) subjecting the wafer to conditions to getter at least one impurity from the silicon film into the gettering site; and (4) removing the damaged surface layer.

Abstract: There is disclosed a method of fabricating TFTs using a silicon film crystallized with the aid of nickel. The nickel is removed from the crystallized silicon film. The method starts with maintaining nickel in contact with the surface of an amorphous silicon film. Then, a heat treatment is performed to form a crystalline silicon film. At this time, nickel promotes the crystallization greatly, and nickel diffuses into the film. A mask is formed. A silicon film heavily doped with phosphorus is formed. Thereafter, a heat treatment is performed to move the nickel from the crystalline silicon film into the phosphorus-rich silicon film. This reduces the concentration of nickel in the crystalline silicon film.

Abstract: The number of defects (HF defects) in the SOI layer of an SOI substrate is reduced. In an annealing method of annealing an SOI substrate in a reducing atmosphere at a temperature equal to or less than the melting point of a semiconductor, annealing is executed in a state wherein a flow of a reducing atmospheric gas parallel to the surface of the SOI substrate is generated near this surface.

Abstract: A substrate inspection device for carrying out visual inspection of a front surface and a rear surface of a wafer W is provided with an arm 21 for holding the wafer W on pad mounting sections 21b through suction. The arm 21 is moved by an arm driving mechanism between a substrate conveying position and a substrate inspection position. The arm 21 is a flat plate partially cut away and having a bracelet-shape, while the pad mounting sections 21b are arranged at specified intervals on the surface of the arm 21. Clip members 24 are arranged at specified intervals on the arm 21 so as to prevent the wafer W dropping off from the arm 21. If the arm 21 is moved to the substrate inspection position, the clip members 24 move to a substrate dropping position. If the vacuum suction of the pad mounting sections 21b is impaired, the wafer W would drop off, but instead they come into contact with the clip members 24 and dropping is prevented.

Abstract: A method of forming a self-aligned gettering region within an SOI substrate is provided. Specifically, the inventive method includes the steps of forming a disposable spacer on each vertical sidewall of a patterned gate stack region, the patterned gate stack region being formed on a top Si-containing layer of an SOI substrate; implanting gettering species into the top Si-containing layer not protected by the disposable spacer and patterned gate stack region; and removing the disposable spacer and annealing the implanted gettering species so as to convert said species into a gettering region.

Abstract: A semiconductor device comprising organic semiconductor material (14) has one or more barrier layers (16) disposed at least partially thereabout to protect the organic semiconductor material (14) from environment-driven changes that typically lead to inoperability of a corresponding device. If desired, the barrier layer can be comprised of partially permeable material that allows some substances therethrough to thereby effect disabling of the encapsulated organic semiconductor device after a substantially predetermined period of time. Getterers (141) may also be used to protect, at least for a period of time, such organic semiconductor material.

Abstract: White defects caused by a dark-current of a solid-state imaging device is reduced by effectively bringing out gettering capability of a buried getter sink layer. A buried getter sink layer is formed by introducing to the semiconductor substrate a substance of a second element which is a congener of a first element composing a semiconductor substrate, a crystal growth layer is formed by crystal growing a substance of the first element on a surface of the semiconductor substrate, and a solid-state imaging element is formed inside and on the crystal growth layer at a lower temperature than that in the case of forming an extrinsic getter sink layer by introducing a substance of a third element of a different group from the first element on a back surface of the semiconductor substrate.

Abstract: A method is designed to manufacture a silicon epitaxial wafer exhibiting sufficient gettering capability from the initial stage of the device process. Specifically, the method is to manufacture the silicon wafer with a nitrogen concentration of at least 1×1012 atoms/cm3 and an oxygen concentration of 10˜18×1017 atoms/cm3 by annealing at a temperature of 800˜1,100° C. after epitaxial growth treatment, satisfying the following equation (a), t≧33−((T−800)/100)  (a) wherein T(° C.) is temperature, and t(hr) is time, thereby manufacturing a high yield semiconductor device.

Abstract: An electronic device that is sealed under vacuum includes a substrate, a transistor formed on the substrate, and a dielectric layer covering at least a portion of the transistor. The electronic device further includes a layer of non-evaporable getter material disposed on a portion of the dielectric layer; and a vacuum device disposed on a portion of the substrate. Electrical power pulses activate the non-evaporable getter material.

Abstract: Within a method for fabricating a microelectronic fabrication comprising a topographic microelectronic structure formed over a substrate, there is implanted, while employing a first ion implant method and while masking a portion of the substrate adjacent the topographic microelectronic structure but not masking the topographic microelectronic structure, the topographic microelectronic structure to form an ion implanted topographic microelectronic structure without implanting the substrate. There is also implanted, while employing a second ion implant method, the portion of the substrate adjacent the topographic microelectronic substrate to form therein an ion implant structure. The method is particularly useful for fabricating source/drain regions with shallow junctions within field effect transistor (FET) devices.

Abstract: A semiconductor wafer manufacturing process is disclosed wherein a double side polished wafer having oxygen induced stacking faults to provide extrinsic gettering on the back surface of the wafer. The process includes polishing the back surface of the wafer, and depositing a thin polysilicon film on the polished back surface. The wafer is then subjected to a thermal oxidation step, wherein the polysilicon film is consumed by the thermal oxidation step. The oxide layer is then stripped from the back surface, leaving oxygen induced stacking faults on the back surface of the wafer. The front surface of the wafer is then polished, thereby producing a double side polished wafer containing extrinsic gettering sites on the polished back surface.

Abstract: Disclosed is a simplified technique of introducing a metal element capable of promoting the crystallization of silicon into an amorphous silicon film to be crystallized, and of removing the metal element from the film. An amorphous silicon film 102 is formed on a substrate, a mask 103 is formed thereon, and a nickel-containing PSG film is further formed thereover. This is heated at 560° C. to thereby make nickel diffused in the direction 106, and the film is crystallized. Next, this is further heated at 850° C. to thereby make phosphorus diffused into the region 107, in which nickel is gettered by the thus-diffused phosphorus. Thus, the crystallization of silicon is promoted by the metal element nickel, and the nickel is then removed from the crystallized silicon film.

Abstract: A method of manufacturing a semiconductor memory device comprising: a step of forming a storage node in which a conductive layer 7 to be the storage node is formed in the vicinity of single crystalline silicon 3 formed on an insulator 2, a gettering step for conducting heat treatment to the single crystalline silicon 3 after the step of forming the storage node and gettering contaminants contained in the single crystalline silicon 3 by the conductive layer 7 connected to the single crystalline silicon, and a step of forming a gate oxide film 8a on the single crystalline silicon 3 after the step of gettering is provided to thereby obtain a sufficient gettering effect even though the width of an element and/or the thickness of the element is reduced in accordance with microminiaturization of the element.

Abstract: There is disclosed a method of fabricating TFTs using a silicon film crystallized with the aid of nickel. The nickel is removed from the crystallized silicon film. The method starts with maintaining nickel in contact with the surface of an amorphous silicon film. Then, a heat treatment is performed to form a crystalline silicon film. At this time, nickel promotes the crystallization greatly, and nickel diffuses into the film. A mask is formed. A silicon film heavily doped with phosphorus is formed. Thereafter, a heat treatment is performed to move the nickel from the crystalline silicon film into the phosphorus-rich silicon film. This reduces the concentration of nickel in the crystalline silicon film.

Abstract: A method for producing a thin-film transistor by using a crystalline silicon film that has been formed by using nickel as a metal element for accelerating crystallization of silicon. In forming source and drain regions, phosphorus as an element for gettering nickel is introduced therein by ion implantation. Nickel gettering is effected by annealing. For example, in the case of producing a P-channel thin-film transistor, both phosphorus and boron are used. Boron determines a conductivity type, and phosphorus is used as a gettering material.

Abstract: A method for forming thin film transistor with reduced metal impurities. The method at least includes the following steps. First of all, an insulation substrate is provided, and an insulating gettering layer is deposited on the substrate, and an amorphous silicon layer is deposited on the insulating gettering layer, wherein the amorphous silicon layer defines an active area. Then, a channel region is formed by using metal induced laterally crystallization process, and sequentially a dielectric layer and a polysilicon layer are deposited on the channel region, wherein the dielectric layer and the polysilicon layer are gate electrode. Finally, implanting numerous ions into amorphous silicon layer by using the gate electrode as a mask to form source and drain regions.

Abstract: A semiconductor device has source and drain regions, a gate insulating film, a gate electrode, and a channel region. The channel region includes a region where carriers move between the source and drain regions. An impurity concentration of the channel region is higher at an end portion of a surface depletion layer than at an interface between the semiconductor layer and the gate insulating film. The impurity concentration varies along a direction in which the gate electrode, the gate insulating film and the channel region are successively provided, and it increases substantially linearly near the end portion of the surface depletion layer.

Abstract: The present invention relates to a simplified method of fabricating a thin film transistor (TFT), including the steps of preparing a first conductive type TFT including a first semiconductor layer and a first gate electrode and a second conductive type TFT including a second semiconductor layer and a second gate electrode on a substrate; doping the first and second semiconductor layers with a first conductive type impurity using the first and second gate electrodes as a mask; forming a doping mask covering the first conductive type TFT; counter-doping the second semiconductor layer with a second conductive type impurity using the doping mask and the second gate electrode as masks; and forming a CMOS TFT by electrically connecting the first conductive type TFT to the second conductive type TFT.

Abstract: At least a part of the surface of a crystalline silicon semiconductor substrate is rendered porous to convert at least a part of the crystalline silicon semiconductor substrate to a porous silicon layer. A catalytic metal layer is formed on the porous silicon layer. An amorphous silicon thin film is formed on the catalytic metal layer. The amorphous silicon thin film is heated to monocrystallize the amorphous silicon thin film, thereby converting the amorphous silicon thin film to a crystalline silicon thin film. The crystalline silicon semiconductor substrate, provided with the crystalline silicon thin film, is joined to a support substrate so that the crystalline silicon thin film faces the support substrate. The crystalline silicon semiconductor substrate, together with the porous silicon layer, which is the crystalline silicon semiconductor substrate in its portion converted to a porous layer, is separated and removed from the crystalline silicon thin film joined to the support substrate.

Abstract: After a catalyst element is introduced into an amorphous silicon film, the amorphous silicon film is converted into a crystalline silicon film by a heat treatment and laser irradiation. After a resist mask is formed on the crystalline silicon film, boron and phosphorus are selectively introduced into the crystalline silicon film to form a gettering region therein. Then, a heat treatment is performed at 500°-650° C., whereby the catalyst element in a gettering subject region is gettered to the gettering region. As a result, a crystalline semiconductor film is obtained in which the catalyst element concentration is reduced. The crystalline semiconductor film is patterned into a semiconductor layer of a semiconductor device.

Abstract: The present invention relates to the formation of multiple gettering structures within a semiconductive substrate by ion implantation through recesses in the semiconductive substrate. A preferred embodiment of the present invention includes forming the recesses by using a reactive anisotropic etching medium, followed by implanting a gettering material. The gettering material is implanted by changing the gettering material for the reactive anisotropic etching medium. An advantage of the method of the present invention is that gettering structures are formed without the cost of an extra masking procedure and without the expense of MeV implantation equipment and procedures. As a result, metallic contaminants will not move as freely through the semiconductive substrate in the region of an active area proximal to the gettering structures.

Abstract: To provide a method of removing a catalyst element from a crystalline silicon film obtained by solid phase growth using the catalyst element promoting crystallization, phosphorus is implanted selectively to the crystalline silicon film having the catalyst element whereby a portion of the silicon film implanted with phosphorus is made amorphous, and when a thermal annealing treatment is performed and the silicon film is heated, the catalyst element is moved to an amorphous portion implanted with phosphorus having large gettering capacity by which the concentration of the catalyst element in the silicon film is lowered and a semiconductor device is fabricated by using the silicon film.