Abstract: A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.

Abstract: A method for manufacturing a thin film transistor is disclosed. Afterforming a channel region on a surface of a substrate, an insulating layer is deposited on the surface of the substrate to cover the channel region. The insulating layer is pataterned such that a portion of the channel region is exposed. Then, a silicon layer and a metal layer are sequentially deposited on the insulating layer. The silicon and metal layers are etched to define source, drain and gate electrode sections. After doping positive ions on a portion corresponding to a MOS circuit portion, an intermediate insulating layer is deposited on the metal layer while covering the source, drain and gate electrode sections. The intermediate insulating layer is patterned to form a plurality of contact holes. An electrode material is deposited on the intermediate insulating layer and patterned to define a pixel electrode section and a wire section.

Abstract: In a charge transfer device and a driving method therefor, electrons are injected through an insulating film into floating gate 108 or electrons are extracted through the insulating film from the floating gate 108, whereby the potential of the floating gate is converged to a fixed voltage.

Abstract: An integrated circuit device structure comprises a semiconductor plateau containing an active region subjacent its front side, an electrode structure at the front side of the plateau, and an insulating layer surrounding the semiconductor plateau. A front side bus at the front side of the insulating layer is connected to the electrode structure. The front side bus extends over an elongate aperture in the insulating layer and is connected through the aperture to a back side bus over substantially the entire length of the front side bus.

Abstract: Method for fabricating a solid state image sensor, which can improve a charge transfer efficiency of an end terminal, including the steps of (1) providing a first conduction type substrate having a second conduction type well and a BCCD formed therein for an end terminal, (2) continuously increasing impurity concentrations in a region of the substrate in which a floating diffusion region is to be formed and in a portion of an area of other substrate in which the regions are are to be formed for improving a horizontal charge transfer efficiency, and (3) forming transfer gates, an output gate, and reset gate on the substrate, and the floating diffusion region and a reset drain region in the BCCD, respectively.

Abstract: A method for driving a solid-state imaging device such as a CCD (Charge Coupled Device) which facilitates control of a blooming suppressing voltage and can reduce a voltage required for shuttering. The solid-state imaging device to be driven typically comprises a first one-conductive type region, a second one-conductive type region having a one-conductive type impurity concentration lower than that of the first one-conductive type region and provided on the first one-conductive type region in contact with the first one-conductive type region, an opposite-conductive type region in contact with the second one-conductive type region, and a one-conductive type layer forming a p-n junction together with the opposite-conductive type region and constituting a photodiode portion together with the opposite-conductive type region.

Abstract: A charge coupled device is disclosed including: a well formed in a substrate, the well having a conductivity opposite to that of the substrate; a first conductivity type of BCCD region formed on the well; a first lightly doped impurity region formed in a predetermined portion of the first conductivity type of BCCD region; a heavily doped impurity region formed in a predetermined portion of the BCCD region, the heavily doped impurity region having a predetermined distance from the first lightly doped impurity region; a second lightly doped impurity region formed between the first lightly doped impurity region and heavily doped impurity region; a first polysilicon gate formed over a portion of the BCCD region, placed between the first lightly doped impurity region and heavily doped impurity region; and a second polysilicon gate formed over the first lightly doped impurity region. The realization of high speed CCD and simplification of the circuit configuration can be obtained by using one-phase clocking.

Abstract: A first silicon oxide film, silicon nitride film, and polycrystalline silicon film are formed on the entire surface of a semiconductor substrate. Then, the polycrystalline silicon film is etched to form a first transfer electrode and then, the surface of the first transfer electrode isothermally oxidized to form a second silicon oxide film. Thereafter, a polycrystalline silicon film and a third silicon oxide film are formed on the entire surface and patterned to form a second transfer electrode. A fourth silicon oxide film is formed on the entire surface, and is etched back. Thereafter, the side wall surfaces of the third silicon oxide film and the second transfer electrode are covered with a fourth silicon oxide film. Thereafter, a light shielding film is selectively formed on them.

Abstract: A charge-coupled device includes a first P-type well formed in an N-type semiconductor substrate, a second P-type well formed repeatedly the first P-type well region, a charge-transfer region (BCCD) formed within the second P-type well region, an N-type photodiode region (PDN) formed in the upper portion of the first P-type well so as to be isolated from the charge-transfer region, a first high concentration P-type photodiode region (first PDP.sup.+ region) formed in the upper surface of the N-type photodiode region excluding the charge-transfer region and serving as a charge-isolating layer, first and second poly-gates formed repeatedly on the charge-transfer region, and a second high concentration self aligned P-type photodiode region (second PDP.sup.+ region) formed in the surface of the first high concentration P-type photodiode region. The charge-isolating region is thin to extend the potential pocket of each light-conversion PDN region.

Abstract: A solid-state image pick-up device having a structure in which the amount of transferred charges is not reduced in a vertical CCD portion even if a pixel portion is made finer, and a method for manufacturing the solid-state image pick-up device are provided. A first p-type well and a second p-type well are formed on an N (100) silicon substrate. A vertical CCD n.sup.+ layer is formed in the second p-type well 3. Then, impurity ions are implanted into a surface layer of the N (100) silicon substrate including an upper layer portion of the vertical CCD n.sup.+ layer to form a p.sup.- layer. An isolating portion for isolating photodiode portions from the vertical CCD n.sup.+ layer and a read control portion for controlling the read of charges from the photodiode n layer are simultaneously formed on a portion adjacent to the vertical CCD n.sup.+ layer.

Abstract: A semiconductor silicon wafer (10) useful as a calibration standard for measurement of a thickness (18) of a microdefect-free layer (16) is formed by depositing an epitaxial layer onto a substrate (12) having an interstitial oxygen concentration suitable for precipitating oxide. Large, uniform oxide microdefects (14) are formed in the substrate by maintaining the semiconductor silicon wafer at between 600.degree. C. and 900.degree. C. to nucleate oxide precipitates that are then grown at between 800.degree. C. and 1,200.degree. C. Because the epitaxial layer contains no oxide precipitate nuclei to form microdefects, the epitaxial layer remains a microdefect-free layer and has a relatively sharp, easily detectable boundary with the substrate. The epitaxial layer can be polished to a reduced thickness, if desired.

Abstract: In a charge coupled device (CCD) comprising a semiconductor substrate having a channel layer therein and a gate insulator thereon, a plurality first electrodes arranged in charge transfer direction on the gate insulator with inter-electrode spaces defined by opposite sidewalls of the first electrodes, an interlayer insulators covering the outer surfaces including the sidewalls of the first electrodes, a plurality of second electrodes formed at the inter-electrodes spaces, and a potential barrier region formed in the channel layer under the inter-electrode spaces, each of the sidewalls are tapered to diverge the inter-electrode space upwardly from the gate insulator so that each of the first electrodes has a thin portion at the tapered sidewall. In boron injection to form the potential barrier region using the first electrodes as a mask.

Abstract: In a charge transfer device including single-layer charge transfer electrodes including a p-type polycrystalline silicon layer and an n-type polycrystalline silicon layer, the sizes of the charge accumulation and potential barrier regions can be set to desired values and the height of potential barrier is produced with a desired reproducibility.A polycrystalline silicon layer is fabricated on a surface of a semiconductor substrate. With a photoresist layer 106 as a mask, ions of phosphorus are implanted thereinto so as to form a silicon oxide layer by liquid phase growth. Boron ions are then injected thereinto. The junction region between the n-type and p-type polycrystalline silicon layers is etched for the separation of the charge transfer electrodes.

Abstract: A product and process for making backside inned semiconductor image sensing devices employing neutral ion beams to reduce substrate volumes so that the image sensor can be illuminated from the backside, or side opposite etched circuitry. A neutral ion beam is contained in a vacuum chamber that has a fixture for holding a semiconductor image sensor, a control mechanism for controlling the neutral ion beam via the raster mechanism, and a map of the semiconductor image sensor. The image sensor is placed on the fixture within the vacuum chamber and the neutral ion beam removes a predetermined amount of substrate from the backside of the sensor. The result is an image sensor than can be backside thinned at the molecular level.

Abstract: A bidirectional horizontal charge transfer device and method includes a charge transfer area formed within a substrate, a plurality of first, second, third and fourth poly gates formed over the charge transfer area, an insulating layer formed between the first, second, third and fourth poly gates, a first clock signal applied to the first and second poly gates, a second clock signal applied to the third and fourth poly gates, and a biasing circuit for selectively applying a bias signal to the first and second clock signals so as to selectively change a charge transfer direction.

Abstract: A methodology for producing an edge aligned implant beneath an electrode with reduced lateral spread, comprising the steps of: providing a dielectric layer on a substrate; forming an etch-stop layer on the dielectric layer; forming a sacrificial material layer on the etch-stop layer; patterning the sacrificial layer with openings to expose the etch-stop layer and which openings corresponding to gate electrode positions; implanting dopant atoms through the opening into the substrate in regions adjacent to at least one edge of the opening in the sacrificial layer; depositing electrode material into the openings and onto the sacrificial layer; forming an electrode layer, either by itself of with another layer deposited or grown over it to allow alteration to provide an etch rate differential. The material that etches relatively slowly becomes or protects the gate electrode region. The alteration is done by a process such as diffusion or irradiation.

Abstract: A method of making a fully self-aligned, planar, two phase charge coupled device comprises the steps of first forming upon a semiconductive substrate a uniform dielectric; then implanting ions of a second conductivity type into the substrate, then patterning closely spaced first conductive strips of a first conductive layer on the dielectric, then further implanting ions of the first or second conductivity type in the regions between said first conductive strips, then depositing uniformly a second conductive layer electrically isolated from the first conductive strips by an insulative region, then entirely removing by uniform planarization those portions of the second conductive layer disposed over regions of the first conductive strips so as to form coplanar, alternating first and thick electrically isolated conductive strips, then depositing a second insulative layer, then electrically connecting selected adjacent first and second conductive strips together to form first and second composite gate electrodes

Abstract: An improved method of manufacturing active matrix displays with ESD protection through final assembly and in process testing and repair capabilities. At least a first set of shorting bars is formed adjacent the row and column matrix. The shorting bars are respectively coupled to one another in series to allow testing of the matrix elements. A first shorting bar is coupled to the odd row lines, a second shorting bar is coupled to the even row lines, a third shorting bar is coupled to the odd column lines and a fourth shorting bar is coupled to the even column lines. The shorting bars can remain coupled to the matrix through final assembly to provide ESD protection and final assembly and testing capability.

Abstract: A fully self-aligned, charge coupled device (CCD) comprises a semiconductor substrate having implanted barrier and/or storage regions, an insulating dielectric layer disposed over the substrate, a first layer of closely spaced electrodes in self-alignment with at least one implant underneath the first electrodes, a second layer of closely spaced electrodes in self-alignment with the first electrodes and with at least one implant underneath the second electrodes also in self-alignment with the first electrodes.

Abstract: A resist layer with a pattern having openings on portions exposed to boundaries between any two adjacent transfer gate electrodes is formed on the surface of a polycrystal silicon layer used as a material for forming the transfer gate electrodes which polycrystal silicon layer has been formed on a gate insulating layer. The polycrystal silicon layer is then etched with the resist layer used as a mask and the surface of the polycrystal silicon layer is subsequently oxidized to form silicon oxide layers between any two adjacent transfer gate electrodes for insulating the adjacent transfer gate electrodes from each other. In this way, the number of manufacturing processes can be reduced by preventing a potential pocket, which gives rise to signal charge left untransferred beneath the space between any two adjacent transfer gate electrodes, from being developed while forming the transfer gate electrodes of the electric charge transferring device into a single-layer structure.