Abstract: An object of the present invention is to provide a small-sized active matrix type liquid crystal display device that may achieve large-sized display, high precision, high resolution and multi-gray scales. According to the present invention, gray scale display is performed by combining time ratio gray scale and voltage gray scale in a liquid crystal display device which performs display in OCB mode. In doing so, one frame is divided into subframes corresponding to the number of bit for the time ratio gray scale. Initialize voltage is applied onto the liquid crystal upon display of a subframe.

Abstract: An anti-diffusion layer, a preparation method thereof, a thin-film transistor (TFT), an array substrate and a display device are provided, involve the display device manufacturing field and can resolve problem that a high atmosphere temperature is need in process of preparing a tantalum dioxide anti-diffusion layer by PVD or CVD, which causes the gate electrode to volatilize and affect the performance of a display device. The method for preparing the anti-diffusion layer comprises: placing a conductive base (1) and a cathode (4) in a electrolytic solution (3), taking the conductive base (1) as an anode, and forming a tantalum dioxide anti-diffusion layer on the conductive base (1) after energizing.

Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.

Abstract: A transistor with stable electric characteristics is provided. A transistor with small variation in electrical characteristics is provided. A miniaturized transistor is provided. A transistor having low off-state current is provided. A transistor having high on-state current is provided. A semiconductor device including the transistor is provided. One embodiment of the present invention is a semiconductor device including an island-shaped stack including a base insulating film and an oxide semiconductor film over the base insulating film; a protective insulating film facing a side surface of the stack and not facing a top surface of the stack; a first conductive film and a second conductive film which are provided over and in contact with the stack to be apart from each other; an insulating film over the stack, the first conductive film, and the second conductive film; and a third conductive film over the insulating film.

Abstract: A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.

Abstract: An organic light emitting display apparatus including a thin film encapsulation layer of an improved structure. The organic light emitting display apparatus includes: a display unit formed on a substrate; metal wires formed on an outer portion of the display unit on the substrate; and a thin film encapsulation layer formed by alternately stacking at least one organic layer and at least one inorganic layer on the display unit for sealing the display unit, wherein the at least one organic layer is separated from the metal wires so as not to contact the metal wires. According to the above structure, since the organic layer that is close to the display unit is separated completely from the metal wires formed on an outer portion of the display unit, moisture infiltration to the display unit via the metal wires may be prevented.

Abstract: Solar cells having emitter regions composed of wide bandgap semiconductor material are described. In an example, a method includes forming, in a process tool having a controlled atmosphere, a thin dielectric layer on a surface of a semiconductor substrate of the solar cell. The semiconductor substrate has a bandgap. Without removing the semiconductor substrate from the controlled atmosphere of the process tool, a semiconductor layer is formed on the thin dielectric layer. The semiconductor layer has a bandgap at least approximately 0.2 electron Volts (eV) above the bandgap of the semiconductor substrate.

Abstract: The present invention provides a structure of a pixel, which includes an array substrate (10), a color filter substrate (20), and a liquid crystal layer (30) between the array substrate (10) and the color filter substrate (20). The array substrate (10) includes a first substrate (11), a data line (12) and a gate line (13) arranged on the first substrate (11), and a pixel unit (14). The pixel unit (14) includes a thin-film transistor (15) and a pixel electrode (16). The thin-film transistor (15) is electrically connected to the data line (12), the gate line (13), and the pixel electrode (16). The color filter substrate (20) includes a second substrate (21) and a common electrode (22) arranged on the second substrate (21). The common electrode (22) and the pixel electrode (16) have a first overlapping portion (23), which forms a first storage capacitor of the pixel unit (14).

Abstract: A thin film transistor includes a gate electrode on a substrate, a main active layer in electrical connection with the gate electrode and including an exposed channel portion, a source electrode in electrical connection with the main active layer, a drain electrode which is spaced apart from the source electrode and in electrical connection with the main active layer, and a sub active layer in electrical connection to the main active layer.

Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.

Abstract: A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.

Abstract: In a manufacturing process of a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation through heat treatment and oxygen doping treatment are performed. A transistor including an oxide semiconductor film subjected to dehydration or dehydrogenation through heat treatment and oxygen doping treatment can be a highly reliable transistor having stable electric characteristics in which the amount of change in threshold voltage of the transistor between before and after the bias-temperature stress (BT) test can be reduced.

Abstract: A thin film transistor is provided. A thin film transistor according to an exemplary embodiment of the present invention includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a semiconductor layer disposed on the substrate and including at least a portion overlapping the gate electrode; a gate insulating layer disposed between the gate line and the semiconductor layer; and a source electrode and a drain electrode disposed on the substrate and facing each other over a channel region of the semiconductor layer. The gate insulating layer includes a first region and a second region, the first region corresponds to the channel region of the semiconductor layer, the first region is made of a first material, the second region is made of a second material, and the first material and the second material have different atomic number ratios of carbon and silicon.

Abstract: A thin film transistor array substrate including a gate line and a data line formed on a substrate, the gate and data lines crossing each other; a gate insulation film formed between the gate and data lines; a gate electrode formed at an intersection of the gate and data lines; an active layer formed on the gate insulation film to overlap the gate electrode; an etch stop layer formed on the active layer to define a channel region of the active layer; and a source electrode and a drain electrode formed on the active layer to partially overlap the active layer. The etch stop layer is between the source and drain electrodes, and the source and drain electrodes are spaced apart from the etch stop layer.

Abstract: A physical structure and a method for forming a electronic devices on a substrate comprising: providing a substrate; forming a plurality of layers on the substrate, the layers comprising at least two layers of conducting material and a layer of insulating material therebetween; depositing photoresist material onto predetermined regions of the plurality of layers, the photoresist material varying in thickness; utilizing gray scale illumination on the photoresist material; removing a portion of the layers using physical etching to expose predetermined portions of the conducting layers. Optionally, the photoresist may be utilized on a plurality of discrete electronic devices concurrently, such that the gray scale illumination is conducted on a plurality of discrete electronic devices concurrently. Similarly, the physical etching may be conducted on the discrete electronic devices concurrently; removing different thicknesses of material concurrently. Also claimed is a product made by the claimed method.

Abstract: A manufacturing method of a wire including: forming a lower layer on a substrate; forming a middle layer on the lower layer; forming an upper layer on the middle layer; forming, exposing, and developing a photoresist layer on the upper layer to form a photoresist pattern; and etching the upper layer, the middle layer, and the lower layer by using the photoresist pattern as a mask to form a wire such that the upper layer covers an end of the middle layer.

Abstract: An object is to provide a semiconductor device having good electrical characteristics. A gate insulating layer having a hydrogen concentration less than 6×1020 atoms/cm3 and a fluorine concentration greater than or equal to 1×1020 atoms/cm3 is used as a gate insulating layer in contact with an oxide semiconductor layer forming a channel region, so that the amount of hydrogen released from the gate insulating layer can be reduced and diffusion of hydrogen into the oxide semiconductor layer can be prevented. Further, hydrogen present in the oxide semiconductor layer can be eliminated with the use of fluorine; thus, the hydrogen content in the oxide semiconductor layer can be reduced. Consequently, the semiconductor device having good electrical characteristics can be provided.

Abstract: An array substrate, a manufacturing method thereof and a display device are provided, and the array substrate comprises: a substrate (1); a plurality of data lines (16), formed on the substrate and extending in a first direction; a plurality of gate lines (15), formed on the substrate (1), crossing the plurality of data lines (15), and extending in a second direction perpendicular to the first direction; a plurality of pixel regions, defined by the plurality of gate lines (15) and the plurality of data lines (15) crossing each other and arranged in a matrix form, wherein each of the pixel regions is provided with a thin film transistor and a pixel electrode (12), wherein, the thin film transistor comprises: a gate electrode (2), connected with one of the plurality of gate lines (15); a gate insulating layer (3), provided above the gate line (15) and the gate electrode (2); an active layer (5), formed on the gate insulating layer (3) and disposed corresponding to the gate electrode (2); a drain electrode (8) a

Abstract: A method for manufacturing an SOI substrate with favorable adherence without high-temperature heat treatment being performed in bonding, and a semiconductor device using the SOI substrate and a manufacturing method thereof are proposed. An SOI substrate and a semiconductor device can be manufactured by forming a single-crystalline silicon substrate with a thickness of 50 ?m or less in which a brittle layer is formed; forming a supporting substrate having an insulating layer over a surface; activating at least one of the surfaces of the single-crystalline silicon substrate and the insulating layer by exposure to a plasma atmosphere or an ion atmosphere; and bonding the single-crystalline silicon substrate and the supporting substrate with the insulating layer interposed therebetween.

Abstract: Solar cells having emitter regions composed of wide bandgap semiconductor material are described. In an example, a method includes forming, in a process tool having a controlled atmosphere, a thin dielectric layer on a surface of a semiconductor substrate of the solar cell. The semiconductor substrate has a bandgap. Without removing the semiconductor substrate from the controlled atmosphere of the process tool, a semiconductor layer is formed on the thin dielectric layer. The semiconductor layer has a bandgap at least approximately 0.2 electron Volts (eV) above the bandgap of the semiconductor substrate.

Abstract: An organic light-emitting display device is disclosed. The organic light-emitting display device may include a substrate, an organic light-emitting portion provided on the substrate, a first inorganic film that seals and covers the organic light-emitting portion, and a second inorganic film provided on the first inorganic film and including a low temperature viscosity transition (LVT) inorganic material. A coefficient of thermal expansion (CTE) of the first inorganic film may be smaller than a CTE of the second inorganic film.

Abstract: Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses, wherein the source and drain contacts extend above the channel layer.

Abstract: The present invention relates to a method of fabricating a display device using a maskless exposure apparatus, and the display device, and more particularly, to a method of fabricating a display device by using a maskless exposure apparatus, which is capable of preventing a stain from being viewed, and the display device.

Abstract: An array substrate including: a gate barrier layer on a substrate; a gate line on the gate barrier layer, the gate line having a gate open portion exposing the gate barrier layer in a gate electrode region; a gate insulating layer on the gate line; an active layer on the gate insulating layer over the gate barrier layer in the gate electrode region; and source and drain electrodes spaced apart from each other on the active layer.

Abstract: A display substrate, method of manufacturing the same, and a display device including the same are disclosed. In one aspect, a display substrate includes a first gate electrode formed on a base substrate, a scan line electrically connected to the first gate electrode, a gate insulation layer, an etch stop layer and a passivation layer formed on the base substrate to at least partially overlap the first gate electrode and the scan line, and a data line formed on the passivation layer to at least partially overlap the scan line.

Abstract: Provided is a transistor which has favorable transistor characteristics and includes an oxide semiconductor, and a highly reliable semiconductor device which includes the transistor including the oxide semiconductor. In the semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode are stacked in this order, a sidewall insulating film is formed along side surfaces and a top surface of the gate electrode, and the oxide semiconductor film is subjected to etching treatment so as to have a cross shape having different lengths in the channel length direction or to have a larger length than a source electrode and a drain electrode in the channel width direction. Further, the source electrode and the drain electrode are formed in contact with the oxide semiconductor film.

Abstract: In connection with various example embodiments, an organic electronic device is provided with an organic material that is susceptible to decreased mobility due to the trapping of electron charge carriers in response to exposure to air. The organic material is doped with an n-type dopant that, when combined with the organic material, effects air stability for the doped organic material (e.g., exhibits a mobility that facilitates stable operation in air, such as may be similar to operation in inert environments). Other embodiments are directed to organic electronic devices n-doped and exhibiting such air stability.

Abstract: A display device includes a laminated wiring formed of a low-resistance conductive film, and a low-reflection film mainly containing Al and functioning as an antireflective film which are sequentially arranged on a transparent substrate, a wiring terminal part provided at an end part of the laminated wiring and has the same laminated structure as that of the laminated wiring, and an insulating film for covering the laminated wiring and the wiring terminal part, in which the insulating film side serves as a display surface side, the wiring terminal part has a first opening part penetrating the insulating film and the low-reflection film and reaching the low-resistance conductive film, and an outer peripheral portion of the first opening part has a laminated structure of the low-resistance conductive film, the low-reflection film, and the insulating film, in at least one part.

Abstract: A method of fabricating a thin film transistor array substrate is disclosed.

Abstract: According to embodiments of the invention, a TFT array substrate, a manufacturing method of the TFT array substrate and a display device are provided. The method comprises: depositing a metal film on a substrate, and forming a gate electrode and a gate line; forming a gate insulating layer and a passivation layer on the substrate; depositing a transparent conductive layer, a first source/drain metal layer and a first ohmic contact layer, and forming a drain electrode, a pixel electrode, a data line, and a first ohmic contact layer pattern provided on the drain electrode; and depositing a semiconductor layer, a second ohmic contact layer and a second source/drain metal layer, and forming a source electrode, a second ohmic contact layer pattern provided below the source electrode, and a semiconductor channel between the source electrode and the drain electrode.

Abstract: A liquid crystal display device having a color filter on TFT (COT) structure for high picture quality, high performance display and a method of fabricating the same are provided to reduce the luminance difference between a pixel portion and an outer portion by laminating color pigments in black matrix regions, forming a light blocking pattern to use as a black matrix, and configuring the light blocking pattern to have three layers to achieve black luminance.

Abstract: The organic insulating film has an opening through which the drain electrode is partially exposed. The opening has a side wall extending from above the drain electrode. The pixel electrode has a contact portion that is in contact with the drain electrode in the opening of the organic insulating film, a wiring portion that extends directly on the side wall of the organic insulating film from the contact portion, and a body portion that is linked to the wiring portion and is located on the organic insulating film. The interlayer insulating film covers the pixel electrode. The interlayer insulating film covers the source electrode and directly covers the semiconductor film between the source-electrode side surface and the drain-electrode side surface. The common electrode has fringes opposed to the pixel electrode via the interlayer insulating film.

Abstract: A display substrate includes a gate line disposed on a base substrate and extending in a direction. A data line crosses the gate line. A thin film transistor comprises a gate electrode, a semiconductor pattern, a source electrode, and a drain electrode. The thin film transistor is connected to the gate line and the data line. A pixel electrode is connected to the thin film transistor. A light blocking pattern overlaps the semiconductor pattern. The light blocking pattern includes a haze-processed material of substantially the same material as the pixel electrode.

Abstract: A thin film transistor substrate is equipped with: an insulating substrate (10a); a gate electrode (2) constituted by a stack of a first barrier metal layer (3) formed of titanium and disposed over the insulating substrate (10a), a first copper layer (4) disposed over the first barrier metal layer (3), and a second barrier metal layer (5) formed of titanium and disposed over the first copper layer (4); a gate insulating layer (7) disposed covering the gate electrode (2); and a semiconductor layer (8) disposed over the gate insulating layer (7), and having a channel region (C) disposed overlapping the gate electrode (2).

Abstract: A micro device transfer head array and method of forming a micro device transfer array from an SOI substrate are described. In an embodiment, the micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include a silicon interconnect and an array of silicon electrodes electrically connected with the silicon interconnect. Each silicon electrode includes a mesa structure protruding above the silicon interconnect. A dielectric layer covers a top surface of each mesa structure.

Abstract: A thin-film semiconductor device having two thin-film transistors, wherein each of the two thin-film transistors includes: a gate electrode; a gate insulating film; a semiconductor layer; a channel protection layer; an intrinsic semiconductor layer; a contact layer in contact with a portion of sides of the channel region; a source electrode on the contact layer; and a drain electrode opposite to the source electrode on the contact layer, wherein the contact layer of one of the two thin-film transistors has a conductivity type different from a conductivity type of the contact layer of the other of the two thin-film transistors.

Abstract: A thin film transistor includes a semiconductor layer disposed on a base substrate and including an oxide semiconductor material, a source electrode and a drain electrode, which respectively extend from opposing ends of the semiconductor layer, a plurality of low carrier concentration areas respectively disposed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer, a gate insulating layer disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating layer.

Abstract: A source electrode (5) and a drain electrode (6) are film-formed, and a semiconductor layer (7) is formed in a substantially stripe shape substantially parallel to the X axis direction (channel-length direction) using a coating method. Then, a protection layer (8) is formed in a substantially stripe shape substantially parallel to the Y axis direction (channel width direction) orthogonal to the semiconductor layer (7). Then, a semiconductor layer (7) portion not covered with the protection layer (8) is removed using an organic solvent or an inorganic solvent or a mixed solution of the organic solvent and the inorganic solvent. Consequently, the semiconductor layer (7) and the protection layer (8) are formed with improved alignment accuracy, and electrical isolation between transistor elements (50) can be achieved with a simplified process.

Abstract: A method of manufacturing a thin film transistor substrate (1) includes at least the steps of: forming a gate electrode (15) on an insulating substrate (10) by using a first photomask; forming a channel protective film (21) on an oxide semiconductor layer (13) so as to cover a channel region (C) by using a second photomask; forming a source electrode (19) on the oxide semiconductor layer (13) by using a third photomask; and forming a planarizing film (18) on an interlayer insulating film (17) by using a fourth photomask.

Abstract: A thin film transistor array panel includes a substrate, a gate line extending in a first direction on the substrate, a data line extending in a second direction on the substrate and intersecting the gate line, a thin film transistor connected to the gate line and the data line, an insulating layer on the gate line, the data line, and the thin film transistor, a first auxiliary line on the insulating layer and connected to the gate line, a second auxiliary line on the insulating layer and connected to the data line, and a pixel electrode connected to the thin film transistor.

Abstract: A photoresist composition may include a novolac resin, a diazide-based photosensitive compound, a surfactant represented by Chemical Formula 1 below, and a solvent. R1 and R2 may denote a hydrogen atom or an alkyl group, x may be 10-50, and y may be 10-50.

Abstract: Provided are a display device and a manufacturing method thereof capable of preventing a short defect between electrodes. The display device includes a substrate, a common electrode formed on the substrate, a pixel electrode formed on the common electrode to be spaced apart from the common electrode with a microcavity therebetween, a roof layer formed on the pixel electrode, a liquid crystal layer filing the microcavity, and an encapsulation layer formed on the roof layer to seal the microcavity.

Abstract: A manufacturing method of an array substrate includes following steps. A first photolithography process is performed to form a gate electrode on a substrate. A gate insulating layer is formed to cover the substrate and the gate electrode. A second photolithography process is performed to form a patterned semiconductor layer and a patterned etching stop layer. A semiconductor layer and an etching stop layer are successively formed on the gate insulating layer, and a second patterned photoresist is formed on the etching stop layer. The etching stop layer uncovered by the second patterned photoresist is removed. The semiconductor layer uncovered by the second patterned photoresist is removed for forming the patterned semiconductor on the gate insulating layer. A patterned etching stop layer is formed on the patterned semiconductor layer by etching the second patterned photoresist and the etching stop layer.

Abstract: Embodiments of the present invention provide an array substrate, a manufacturing method thereof and a display device. The manufacturing method of an array substrate, comprising: forming a gate electrode on a base substrate by a first patterning process, and then depositing a gate insulating layer on the base substrate on which the gate electrode is formed; forming source and drain electrodes on the base substrate obtained after the above step, by a second patterning process; forming an active layer formed of a graphene layer, and a protective layer disposed on the active layer, on the base substrate obtained after the above steps, by a third patterning process; and forming a planarizing layer on the base substrate, obtained after the above steps, by a fourth patterning process, in which the planarizing layer is provided with a through hole through which the source or drain electrode is exposed.

Abstract: An embodiment of the invention provides a manufacturing method of a thin film transistor substrate including: sequentially forming a gate electrode, a gate insulating layer covering the gate electrode, an active material layer, and a photo-sensitive material layer on a first substrate; performing a photolithography process by using a half tone mask to form a photo-sensitive protective layer which is above the gate electrode and has a first recess and a second recess; etching the active material layer by using the photo-sensitive protective layer as a mask to form an active layer; removing a portion of the photo-sensitive protective layer at bottoms of the first recess and the second recess to expose a first portion and a second portion of the active layer respectively; forming a first electrode connecting to the first portion; and forming a second electrode connecting to the second portion.

Abstract: A liquid crystal display may include a first substrate, a second substrate facing the first substrate, a liquid crystal layer comprising liquid crystal molecules that are interposed between the first substrate and the second substrate, a first electrode disposed on the first substrate, an insulating layer disposed on the first electrode, a second electrode disposed on the insulating layer, a third electrode disposed on the second substrate, and an alignment layer disposed on any one of the second electrode and the third electrode. The second electrode comprises a fine slit structure, and at least one of the liquid crystal layer and the alignment layer comprises a sub-alignment substance.

Abstract: Disclosed are an LCD device and a method of manufacturing the same, which reduce a capacitance deviation between pixels without any change in a viewing angle and a high transmittance. The LCD device includes a plurality of gate lines formed in a first direction on a substrate, a plurality of data lines formed in a second direction to intersect the plurality of gate lines, a thin film transistor (TFT) formed in each of a plurality of pixel areas defined by the plurality of gate lines and the plurality of data lines, a pixel electrode formed in a tetragonal shape in each of the plurality of pixel areas, and a common electrode formed on the pixel electrode, and configured to include a plurality of finger patterns. Each of the plurality of pixel areas is formed in a tetragonal shape.

Abstract: A TFT array substrate is provided. The TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line that crosses the gate line and defines a pixel region; a drain electrode facing the source electrode with a channel between; a semiconductor layer forming the channel in between the source electrode and the drain electrode; a pixel electrode in the pixel region and contacting the drain electrode; a channel passivation layer formed on the semiconductor layer; a gate pad with a gate pad lower electrode that extends from the gate line; and a data pad having a data pad lower electrode separated from the data line.

Abstract: A thin film transistor (TFT) array substrate, an organic light-emitting display apparatus, and a manufacturing method thereof are disclosed. One inventive aspect includes a first gate line formed on a substrate and a second gate line formed on the first gate line. A third gate line is formed on the second gate line and covers a top surface of the second gate line and the side portions of the first and second gate lines.

Abstract: In the transistor including an oxide semiconductor film, a gate insulating film of the transistor including an oxide semiconductor film has a stacked-layer structure of the hydrogen capture film and the hydrogen permeable film. At this time, the hydrogen permeable film is formed on a side which is in contact with the oxide semiconductor film, and the hydrogen capture film is formed on a side which is in contact with a gate electrode. After that, hydrogen released from the oxide semiconductor film is transferred to the hydrogen capture film through the hydrogen permeable film by the heat treatment.