Abstract: A pixel structure includes a substrate, a gate line, a data line, a semiconductor pattern, a non-metal source electrode pattern, a non-metal drain electrode pattern, and a pixel electrode. The gate line and the data line are disposed on the substrate. The semiconductor pattern is disposed on the gate line, and the semiconductor pattern overlaps two corresponding edges of the gate line along a vertical projective direction. The non-metal source electrode pattern and the non-metal drain electrode pattern are disposed on the semiconductor pattern. The non-metal source electrode pattern and the non-metal drain electrode pattern are respectively disposed on two corresponding edges of the gate line. The non-metal source electrode pattern is partially disposed between the data line and the gate line. The pixel electrode is electrically connected to the non-metal drain electrode pattern.

Abstract: A display substrate includes a switching transistor electrically connected to a gate line and a data line, the data line extending in a first direction substantially perpendicular to the gate line extending in a second direction, the switching transistor including a switching active pattern comprising amorphous silicon, a driving transistor electrically connected to a driving voltage line and the switching transistor, the driving voltage line extended in the first direction, the driving transistor including a driving active pattern comprising a metal oxide; and a light-emitting element electrically connected to the driving transistor.

Abstract: A liquid crystal display in which an organic passivation layer is partially removed and a method of fabricating the same are provided. The liquid crystal display comprises: an active area and a pad area. The pad area comprising: a first pad area where first pads connected to the data lines and bonded to output terminals of a drive IC are formed; a second pad area where second pads bonded to an input terminals of the drive IC are bonded; and a third pad area where third pads bonded to output terminals of the FPC are formed.

Abstract: Provided is a thin film transistor on fiber and a method of manufacturing the same. The thin film transistor includes a fiber; a first electrode, a second electrode and a gate electrode formed on fiber; a channel formed between the first and second electrodes; an encapsulant encapsulating the fiber, the first, second, and gate electrodes, and an upper surface of the channel; and a gate insulating layer formed in a portion of the inner area of the encapsulant.

Abstract: Disclosed herein is a display device including: a thin film transistor; and a wiring layer; wherein the thin film transistor includes a semiconductor layer, a gate electrode disposed so as to be opposed to the semiconductor layer, the gate electrode being different in thickness from the wiring layer, and a gate insulating film between the semiconductor layer and the gate electrode.

Abstract: A thin film transistor, includes: a gate electrode; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; an etch stopper disposed on a channel of the semiconductor; a source electrode disposed on the semiconductor; and a drain electrode disposed on the semiconductor. At least one of the source electrode and the drain electrode does not overlap with the etch stopper. At least one dimension of the etch stopper and the channel of the semiconductor are substantially the same.

Abstract: A highly reliable semiconductor device in which a transistor including an oxide semiconductor film has stable electric characteristics is manufactured. In the semiconductor device which includes an inverted-staggered transistor having a bottom-gate structure and being provided over a substrate having an insulating surface, at least a first gate insulating film and a second gate insulating film are provided between a gate electrode layer and an oxide semiconductor film, and heat treatment is performed at a temperature of 450° C. or higher, preferably 650° C. or higher, and then the oxide semiconductor film is formed. By the heat treatment at a temperature of 450° C. or higher before the formation of the oxide semiconductor film, diffusion of hydrogen elements into the oxide semiconductor film, which causes degradation or variations in electric characteristics of the transistor, can be reduced, so that the transistor can have stable electric characteristics.

Abstract: A thin film transistor substrate includes a substrate, a gate electrode disposed on the substrate, a gate insulation layer disposed on the gate electrode, an oxide semiconductor pattern disposed on the gate insulation layer, where the oxide semiconductor pattern includes a first area whose carrier concentration is in a range of about 1017 per cubic centimeter to about 1019 per cubic centimeter and a second area whose carrier concentration is less than the carrier concentration of the first area, an etch stopper disposed on the oxide semiconductor pattern, where the etch stopper covers the first area and the second area of the oxide semiconductor pattern, a signal electrode partially overlapping the etch stopper and the second area, and a passivation layer which covers the etch stopper and the signal electrode.

Abstract: A transistor in a display device is expected to have higher withstand voltage, and it is an object to improve the reliability of a transistor which is driven by high voltage or large current. A semiconductor device includes a transistor in which buffer layers are provided between a semiconductor layer forming a channel formation region and source and drain electrode layers. The buffer layers are provided between the semiconductor layer forming a channel formation region and the source and drain electrode layers in order to particularly relieve an electric field in the vicinity of a drain edge and improve the withstand voltage of the transistor.

Abstract: A transistor includes a substrate, an electrically conductive material layer, and an electrically insulating material layer. At least a portion of one or more of the substrate, the electrically conductive material layer, and the electrically insulating material layer define a reentrant profile.

Abstract: Provided a display device including a thin film transistor. The thin film transistor includes a gate electrode, a gate insulating layer which covers the gate electrode, an oxide semiconductor film above the gate insulating layer, a source electrode and a drain electrode which are respectively provided in contact with a first region and a second region, which are provided in the upper surface of the oxide semiconductor film, and a channel protective film which is provided in contact with a third region between the first region and the second region. In plan view, a region of the oxide semiconductor film, which overlaps with the gate electrode, is smaller than the third region, and a portion of the oxide semiconductor film except for a portion which overlaps with the gate electrode has a resistance lower than the portion.

Abstract: According to an aspect of the present invention, there is provided a thin-film transistor (TFT) sensor, including a bottom gate electrode on a substrate, an insulation layer on the bottom gate electrode, an active layer in a donut shape on the insulation layer, the active layer including a channel through which a current generated by a charged body flows, an etch stop layer on the active layer, the etch stop layer including a first contact hole and a second contact hole, and a source electrode and a drain electrode burying the first and second contact holes, the source and drain electrodes being disposed on the etch stop layer so as to face each other.

Abstract: A method of manufacturing an array substrate for an FFS mode LCD device includes forming a gate line and a gate electrode on a substrate, forming a pixel electrode in the pixel region, forming a gate insulating layer on the gate line, the gate electrode and the pixel electrode, forming a data line, a source electrode, a drain electrode, and a semiconductor layer on the gate insulating layer, forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer including a drain contact hole and a pixel contact hole, and forming a connection pattern and a common electrode on the passivation layer, wherein the common electrode includes bar-shaped first openings in the pixel region, and the connection pattern contacts the drain electrode and the pixel electrode through the drain contact hole and the pixel contact hole, respectively.

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle ?1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle ?2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Abstract: A fabrication method of a pixel structure and a pixel structure are provided. A first patterned metal layer including scan lines and a gate is formed on a substrate. A first insulation layer, a semiconductor layer, an etching stop pattern and a metal layer are formed sequentially on the first patterned metal layer. The metal layer and the semiconductor layer are patterned to form a second patterned metal layer and a patterned semiconductor layer. The second patterned metal layer includes data lines, a source and a drain. The patterned semiconductor layer includes a first semiconductor pattern completely overlapping the second patterned metal layer and a second semiconductor pattern without overlapping the second patterned metal layer, wherein the second semiconductor pattern includes a channel pattern and a marginal pattern. The channel pattern is between the source and the drain and the marginal pattern surrounds the first semiconductor pattern.

Abstract: An object is to provide a highly reliable semiconductor device including a thin film transistor having stable electric characteristics. In addition, another object is to manufacture a highly reliable semiconductor device at low cost with high productivity. In a method for manufacturing a semiconductor device including a thin film transistor including an oxide semiconductor layer as a channel formation region, the oxide semiconductor layer is heated under a nitrogen atmosphere to lower its resistance, thereby forming a low-resistance oxide semiconductor layer. Further, resistance of a region of the low-resistance oxide semiconductor layer, which is overlapped with a gate electrode layer, is selectively increased, thereby forming a high-resistance oxide semiconductor layer. Resistance of the oxide semiconductor layer is increased by forming a silicon oxide film in contact with the oxide semiconductor layer by a sputtering method.

Abstract: Embodiments of the invention provide an array substrate and a fabrication method thereof, and a liquid crystal display device. The array substrate comprises: a gate line, a data line, and a pixel unit formed by the gate line and the data line intersecting with each other. A first thin-film transistor and a pixel electrode are formed in the pixel unit, and the pixel electrode has slits. The pixel unit further comprises a second thin-film transistor, a first common electrode and a second common electrode, and the second thin-film transistor is configured to turn on and transmit a signal of the first common electrode to the second common electrode when a data line signal is at a high level.

Abstract: A thin film transistor substrate is provided. The thin film transistor substrate includes a display area including a plurality of pixels, wherein the pixels are connected to gate lines and data lines, a gate driver connected to the gate lines, a plurality of data pads connected to the data lines, a plurality of dummy pattern parts formed of a same layer as the gate lines, and a non-display area in which the gate driver, data pads, and dummy pattern parts are disposed, and the dummy pattern parts are disposed in an area within the non-display area where the gate driver is not disposed, and one of the dummy pattern parts is disposed overlapping with the data pads.

Abstract: A thin film transistor (TFT) array panel and a manufacturing method thereof are disclosed. A contact hole may be formed to expose a pad disposed on a substrate of the TFT array panel. A first layer of a connecting member is formed with the same layer as a first field generating electrode and is disposed in the contact hole. A second passivation layer is disposed in the TFT array panel, but is removed at a region where the contact hole is formed and portions of the second passivation layer that cover the first layer of the connecting member. A second layer of the connecting member is formed on the first layer of the connecting member.

Abstract: A semiconductor device including an oxide semiconductor with stable electric characteristics and high reliability is provided. An island-shaped oxide semiconductor layer is formed by using a resist mask, the resist mask is removed, oxygen is introduced (added) to the oxide semiconductor layer, and heat treatment is performed. The removal of the resist mask, introduction of the oxygen, and heat treatment are performed successively without exposure to the air. Through the oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor layer, whereby the oxide semiconductor layer is highly purified. Chlorine may be introduced to an insulating layer over which the oxide semiconductor layer is formed before formation of the oxide semiconductor layer.

Abstract: The present invention relates to a photoresist composition for digital exposure and a method of fabricating a thin film transistor substrate. The photoresist composition for digital exposure includes a binder resin including a novolak resin and a compound represented by the chemical formula (1), a photosensitizer including a diazide-based compound, and a solvent: wherein R1-R9 each include a hydrogen atom, an alkyl group, or a benzyl group, a is an integer from 0 to 10, b is an integer from 0 to 100, and c is an integer from 0 to 10.

Abstract: A touch display screen, a method for manufacturing a display electrode of the touch display screen, a display electrode and an electronic device are described. In the touch display screen, the electrode in the first direction and the electrode in the second direction are connected to the touch detecting unit, and the touch detecting unit and the display control unit operate in a time-sharing manner. Thus, a part of the display electrode can be multiplexed, and it is unnecessary to provide an additional touch-sensitive layer to detect the touch on the touch display screen, so the structure of the touch display screen is simplified; because the touch-sensitive layer is omitted, the touch display screen has better transmittance; and because the touch detecting unit and the display control unit operate in a time-sharing manner, the detection on the touch and the control on the display will not affect mutually.

Abstract: A thin film transistor, a display device including the same, and a method of manufacturing the display device, the thin film transistor including a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor layer on the gate insulating layer; and source/drain electrodes electrically connected with the semiconductor layer, wherein the gate electrode has a thickness of about 500 ? to about 1500 ? and the gate insulating layer has a thickness of about 1600 ? to about 2500 ?.

Abstract: Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

Abstract: Self-aligned carbon nanostructure field effect transistor structures are provided, which are formed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer.

Abstract: Self-aligned carbon nanostructure field effect transistor structures are provided, which are foamed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer.

Abstract: A method of fabricating a fringe field switching (FFS)-liquid crystal display (LCD) device may have the following advantage. An inferior connection between the drain electrode and the pixel electrode may be prevented by preventing formation of a copper compound on the drain electrode, by performing a back channel etching after patterning a pixel electrode, and by performing a wet strip rather than a dry strip. This may result in a direct contact between copper and ITO, thereby reducing the number of mask processes.

Abstract: An object is to obtain a semiconductor device with improved characteristics by reducing contact resistance of a semiconductor film with electrodes or wirings, and improving coverage of the semiconductor film and the electrodes or wirings. The present invention relates to a semiconductor device including a gate electrode over a substrate, a gate insulating film over the gate electrode, a first source or drain electrode over the gate insulating film, an island-shaped semiconductor film over the first source or drain electrode, and a second source or drain electrode over the island-shaped semiconductor film and the first source or drain electrode. Further, the second source or drain electrode is in contact with the first source or drain electrode, and the island-shaped semiconductor film is sandwiched between the first source or drain electrode and the second source or drain electrode. Moreover, the present invention relates to a manufacturing method of the semiconductor device.

Abstract: A thin-film transistor substrate includes a gate line, and a gate electrode connected to the gate line, on a base substrate; an insulating layer on the gate electrode, the insulating layer including a first part and a second part, the first part having a hydrophobic property and the second part having a hydrophilic property; a data line extended in a different direction from the gate line, and a source electrode connected to the data line and on the second part of the insulating layer; a drain electrode on the second part of the insulating layer, the drain electrode spaced apart from the source electrode; a semi-conductor pattern overlapping the source electrode, the drain electrode and a gap between the spaced apart source and drain electrodes, where the semi-conductor pattern exposes the first part of the insulating layer; and a pixel electrode in contact with the drain electrode.

Abstract: A method of making a transistor includes etching a first side of a gate, the gate including an oxide layer formed over a substrate and a conductive material formed over the oxide layer, the etching removing a first portion of the conductive material, implanting an impurity region into the substrate such that the impurity region is self-aligned, and etching a second side of the gate to remove a second portion of the conductive material.

Abstract: In a method for producing a display panel, a base substrate having an upper surface on which an electrode is located is prepared. A first layer having a first opening overlapping with the electrode in plan-view is formed on the base substrate. A second layer having a second opening overlapping with the first opening in plan-view is formed on the first layer. The second opening has a smaller area than the first opening in plan-view. A wiring layer is formed in the first opening and the second opening, in contact with the electrode. The second layer includes a portion located on an upper surface of the first layer and a portion located in the first opening. The portion of the second layer located in the first opening covers an internal side surface of the first layer located around the first opening.

Abstract: A thin-film transistor device manufacturing method forms a plurality of gate electrodes above a substrate. A silicon nitride layer is formed on the plurality of gate electrodes. A silicon oxide layer is formed on the silicon nitride layer. An amorphous silicon layer is formed on the silicon oxide layer. The amorphous silicon layer is crystallized using predetermined laser light to produce a crystalline silicon layer. A source electrode and a drain electrode are formed on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes. A film thickness of the silicon oxide layer, a film thickness of the silicon nitride layer, and a film thickness of the amorphous silicon layer satisfy predetermined conditional expressions.

Abstract: A method for manufacturing a semiconductor device comprises the steps of forming a seed over the insulating film by introducing hydrogen and a deposition gas into a first treatment chamber under a first condition and forming a microcrystalline semiconductor film over the seed by introducing hydrogen and the deposition gas into a second treatment chamber under a second condition: a second flow rate of the deposition gas is periodically changed between a first value and a second value; and a second pressure in the second treatment chamber is higher than or equal to 1.0×102 Torr and lower than or equal to 1.0×103 Torr.

Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.

Abstract: A thin film transistor for increasing the conductivity of a channel region and suppressing the leakage current of a back channel region, and a display device including the thin film transistor, are discussed. According to an embodiment, the thin film transistor includes a gate electrode arranged on a substrate, a source electrode and a drain electrode spaced from each other on the substrate, a gate insulating film to insulate the gate electrode from the source electrode and the drain electrode, and a semiconductor layer insulated from the gate electrode through the gate insulating film, the semiconductor layer including a channel region and a back channel region, the semiconductor layer made of (In2O3)x(Ga2O3)y(ZnO)z(0?x?5, 0?y?5, 0?z?5), wherein X or Z is greater than Y in the channel region of the semiconductor layer, and Y is greater than X and Z in the back channel region of the semiconductor layer.

Abstract: A highly reliable semiconductor device that includes a transistor including an oxide semiconductor is provided. In a manufacturing process of a semiconductor device that includes a bottom-gate transistor including an oxide semiconductor, an insulating film which is in contact with an oxide semiconductor film is subjected to dehydration or dehydrogenation treatment by heat treatment and oxygen doping treatment in this order. The insulating film which is in contact with the oxide semiconductor film refers to a gate insulating film provided under the oxide semiconductor film and an insulating film which is provided over the oxide semiconductor film and functions as a protective insulating film. The gate insulating film and/or the insulating film are/is subjected to dehydration or dehydrogenation treatment by heat treatment and oxygen doping treatment in this order.

Abstract: On each of wiring conversion parts connected to a first conductive film and a second conductive film each functioning as a wiring, a first transparent conductive film does not cover an end surface of the second conductive film in proximity to a corner of the first transparent conductive film, and has a portion covering the end surface of the second conductive film on a portion other than the proximity of the corners. A second transparent conductive film as an upper layer of the first transparent conductive film is connected to the first conductive film and the second conductive film, so that the first conductive film and the second conductive film are electrically connected.

Abstract: Disclosed is a method for fabricating an array substrate, comprising: forming a pattern layer comprising a gate and a gate connection on a substrate; sequentially forming an insulation layer film and an active layer film on the substrate, and forming a pattern of a gate insulation layer having a first via hole and a pattern of an active layer through a single patterning process, wherein the first via hole is located above the gate connection; sequentially forming a transparent conductive film and a metal film on the substrate, and forming a pattern layer comprising a first electrode and a pattern layer comprising a data line, a source, a drain and a TFT channel through a single patterning process.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the invention includes: a substrate, a gate line disposed on the substrate and including a gate electrode, a gate insulating layer disposed on the gate line, a semiconductor disposed on the gate insulating layer, a data line disposed on the semiconductor and including a source electrode, a drain electrode disposed on the semiconductor and opposite to the source electrode, a color filter disposed on the gate insulating layer, the data line and the drain electrode, an overcoat disposed on the color filter and including an inorganic material, a contact hole defined in the color filter and the overcoat, where the contact hole exposes the drain electrode, and a pixel electrode disposed on the overcoat and connected through the contact hole to the drain electrode, in which a plane shape of the contact hole in the overcoat and a plane shape of the contact hole in the color filter are substantially the same as each other.

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a semiconductor device comprises an insulation region over a substrate; a gate electrode layer over the insulation region comprising a gate middle line; a first contact structure over the insulation region adjacent to the gate electrode layer comprising a first middle line, wherein the first middle line and the gate middle line has a first distance; and a second contact structure over the insulation region on a side of the gate electrode layer opposite to the first contact structure comprising a second middle line, wherein the second middle line and the gate middle line has a second distance greater than the first distance.

Abstract: It is possible to manufacture a large-size, high-accuracy organic EL display using a plastic substrate and an organic EL display using a roll-shaped long plastic substrate. The organic EL display includes an organic EL device A having at least a lower electrode 300, an organic layer including at least a light emitting layer, and an upper electrode 305 and a thin film transistor B on a transparent plastic substrate 100, a source electrode or drain electrode of the thin film transistor B is connected to the lower electrode 300, the plastic substrate 100 has a gas barrier layer 101a, the thin film transistor B is formed on the gas barrier layer 101a, the thin film transistor B includes an active layer 203 containing a non-metallic element which a mixture of oxygen (O) and nitrogen (N) and has a ratio of N to O (N number density/O number density) from 0 to 2, and the organic EL device A is formed at least on the gas barrier layer 101a or one the thin film transistor B.

Abstract: An array substrate, a manufacturing method thereof and a display device are provided. As for the method of manufacturing the array substrate, the common electrode and the pixel electrode are formed by a single process simultaneously. Therefore, the problems of process complexity and the higher costs in the existing manufacturing process of array substrate can be solved.

Abstract: A thin film transistor array panel includes a substrate, an insulation layer, a first semiconductor, and a second semiconductor. The insulation layer is disposed on the substrate and includes a stepped portion. The first semiconductor is disposed on the insulation layer. The second semiconductor is disposed on the insulation layer and includes a semiconductor material different than the first semiconductor. The stepped portion is spaced apart from an edge of the first semiconductor.

Abstract: A ZnO-based semiconductor device includes an n type ZnO-based semiconductor layer, an aluminum oxide film formed on the n type ZnO-based semiconductor layer, and a palladium layer formed on the aluminum oxide film. With this configuration, the n type ZnO-based semiconductor layer and the palladium layer form a Schottky barrier structure.

Abstract: According to one aspect of the present invention, the provided is an array substrate. Specifically, the first conductive strip that is coupled to the first data shorting bar and the second conductive strip that is coupled to the second data shorting bar are formed on the array substrate. The width of the first conductive strip is greater than the width of the first data shorting bar. The width of the second conductive strip is greater than the width of the second data shorting bar. The first conductive strip is overlapped with the second conductive strip. Such a structure of the array substrate effectively increases the overlapped capacitance between the data metal layer and the gate metal layer.

Abstract: A metal oxide thin film transistor includes a metal oxide semiconductor channel with the metal oxide semiconductor having a conduction band with a first energy level. The transistor further includes a layer of passivation material covering at least a portion of the metal oxide semiconductor channel. The passivation material has a conduction band with a second energy level equal to, or less than 0.5 eV above the first energy level.

Abstract: A thin-film transistor includes: a gate electrode above a substrate; a gate insulating layer above the gate electrode; a semiconductor layer opposed to the gate electrode with the gate insulating layer therebetween; a protective layer above the semiconductor layer and comprising an organic material; and a source electrode and a drain electrode each of which has at least a portion located above the protective layer. The protective layer includes an altered layer which has at least a portion contacting the semiconductor layer, and which is generated by alteration of a surface layer of the protective layer in a region exposed from the source electrode and the drain electrode. A relational expression of Log10 Nt?0.0556?+16.86 is satisfied where Nt (cm?3) represents a defect density of the semiconductor layer and ? (°) represents a taper angle of an edge portion of the protective layer.

Abstract: A touch display comprising a first substrate formed with a common electrode; a second substrate formed with a gate line and a data line, wherein a first thin film transistor and a pixel electrode is provided in a pixel region defined by the gate line and the data line and the pixel region and the common electrode form a liquid crystal capacitor; a touch element provided in the pixel region in the second substrate and used to sense a touch voltage reflecting the change of the liquid crystal capacitance at a touch point; and a touch processing device connected with the touch element and used to obtaining a position coordinates of the touch point according to the touch voltage.

Abstract: A method for manufacturing a thin-film transistor, includes: preparing a substrate; forming a gate electrode above the substrate; forming a gate insulating layer above the gate electrode; forming a semiconductor film above the gate insulating layer; forming, above the semiconductor film, a protective layer comprising an organic material; forming a source electrode and a drain electrode above the protective layer; forming a semiconductor layer patterned, by performing dry etching on the semiconductor film; removing at least a portion of a region of an altered layer, the region contacting the semiconductor layer, the altered layer being a surface layer of the protective layer that is altered by the dry etching; and forming a passivation layer having a major component identical to a major component of the protective layer so as to contact the semiconductor layer in a region in which the altered layer has been removed.

Abstract: The present invention relates to a thin-film transistor in a liquid crystal display device and a method of fabricating the same, and the thin-film transistor may be configured by including a first gate electrode formed on an insulating substrate; a first gate insulation film formed on the insulating substrate including the first gate electrode; an active layer formed on the first gate insulation film; source/drain electrodes formed on the active layer and arranged at both sides of the first gate electrode; a second gate insulation film formed on the active layer and the first gate insulation film including the source/drain electrodes and provided with a contact hole for exposing part of the drain electrode; a second gate electrode overlapped with the first gate electrode on the second gate insulation film; and a pixel electrode electrically connected to the drain electrode through the contact hole.