Abstract: A thin film transistor (TFT) structure is implemented. This embodiment is much less sensitive than conventional TFTs to alignment errors and substrate distortion. In such a configuration, there is no need to define gate features, so the layout is simplified. Moreover, the gate layer may be patterned by several inexpensive printing or non-printing methods.

Abstract: A thin film transistor and a method of manufacturing the same, and a display device and a method of manufacturing the same are disclosed, in which the thin film transistor substrate comprises an active layer formed on a substrate; a gate electrode controlling electron transfer within the active layer; a source electrode connected with one end area of the active layer; a drain electrode connected with the other end area of the active layer; and a light-shielding layer formed under the active layer to shield light from entering the active layer.

Abstract: The present application discloses a method for manufacturing a semiconductor device. The method may comprise providing a fin in a semiconductor layer of a SOI substrate, and providing a stack of gate dielectric and gate conductor on only a first side of the fin. The gate conductor may extend laterally away from the first side of the fin in a gate extending direction. The method may comprise doping the fin at its other two opposing sides so as to provide a source region and a drain region. Each of the source and drain regions may have a portion extending laterally away from a second side, opposite to the first side, of the fin in a source/drain extending direction. The gate extending direction and the source/drain extending direction can be parallel to the main surface of the SOI substrate, while being opposite to each other. The method may comprise providing a channel region at a central portion of the fin.

Abstract: An exposure mask includes a first transmission portion, a second transmission portion, and a blocking portion. The first transmission portion is configured to, when illuminated with light, transmit the light at a first energy level. The first transmission portion is disposed in association with formation of a first contact hole in an underlying layer. The second transmission portion is configured to, when illuminated with the light, transmit the light at a second energy level. The second transmission portion is disposed in association with formation of a second contact hole in the underlying layer. The blocking portion is configured to block the light, and is disposed in association with a boundary region between a first region and a second region of the underlying layer. The second transmission portion is further configured to enable the second contact hole to be formed deeper into the underlying layer than the first contact hole.

Abstract: A thin film transistor substrate is equipped with: an insulating substrate (10a); a gate electrode (2) constituted by a stack of a first barrier metal layer (3) formed of titanium and disposed over the insulating substrate (10a), a first copper layer (4) disposed over the first barrier metal layer (3), and a second barrier metal layer (5) formed of titanium and disposed over the first copper layer (4); a gate insulating layer (7) disposed covering the gate electrode (2); and a semiconductor layer (8) disposed over the gate insulating layer (7), and having a channel region (C) disposed overlapping the gate electrode (2).

Abstract: Embodiments of the present invention provide an array substrate and a fabrication method thereof, and a display device, the array substrate comprises gate lines, data lines, and pixel units defined by the gate lines and the data lines crossing with each other, and each pixel unit comprises a first TFT, whose gate is electrically connected with the gate line, wherein each pixel unit further comprises an auxiliary turn-on structure for forming a turn-on voltage at a channel of the first TFT when the first TFT is switched into conduction. In the embodiments of the present invention, a dual-drive voltage for the first TFT is formed by the auxiliary turn-on structure together with the gate of the first TFT, so that when the turn-on voltage provided by the gate lines is relatively low, the channel of the first TFT can also be turned on, therefore lowering power consumption.

Abstract: A thin film transistor (TFT) and a method of manufacturing the same such that an ohmic contact can be formed between a semiconductor layer and a source electrode or between the semiconductor layer and a drain electrode, wherein the TFT can be applied to a plastic substrate. The TFT includes: a substrate; an active layer formed of ZnO, InZnO, ZnSnO, and/or ZnInGaO on the substrate and including a channel region, a source region, and a drain region; a gate electrode insulated from the active layer; and source and drain electrodes insulated from the gate electrode and electrically connected to the source region and the drain region, respectively, wherein the source region and the drain region of the active layer include hydrogen.

Abstract: An array substrate for a liquid crystal display includes a substrate and first and second subpixels which are positioned on the substrate and are defined by a crossing structure of one gate line, a first data line, a second data line, a first common line, and a second common line. The first subpixel includes a first semiconductor layer, a first source electrode, a first drain electrode, and a first pixel electrode connected to the first drain electrode. The second subpixel includes a second semiconductor layer, a second source electrode, a second drain electrode, and a second pixel electrode connected to the second drain electrode. The first and second subpixels share the one gate line with each other, and the first drain electrode and the second drain electrode are exposed through one contact hole.

Abstract: A dual-gate transistor including: a first insulating layer provided to cover a first conductive layer; a first semiconductor layer over the first insulating layer; second semiconductor layers over the first semiconductor layer, the second semiconductor layers are spaced from each other to expose the first semiconductor layer; impurity semiconductor layers over the second semiconductor layers; second conductive layers over the impurity semiconductor layers; second insulating layers over the second conductive layers; a third insulating layer to cover the first semiconductor layer, the second semiconductor layers, the impurity semiconductor layers, the second conductive layers, and the second insulating layers; and a third conductive layer at least over the third insulating layer, and in the dual-gate transistor including the first to third insulating layers with openings, the first insulating layer is substantially equal in thickness to the second insulating layer.

Abstract: A crystalline silicon thin film is formed by irradiating a silicon thin film with a laser beam. The laser beam is a continuous wave laser beam. An intensity distribution of the laser beam in a first region about a center of the intensity distribution is symmetric on an anterior side and a posterior side of the center. The intensity distribution in a second region about the center is asymmetric on the anterior side and the posterior side. The first region is from the maximum intensity of the laser beam at the center to an intensity half of the maximum intensity. The second region is at most equal to the half of the maximum intensity of the laser beam. In the second region, an integral intensity value on the posterior side is larger than on the anterior side.

Abstract: Provided is a method of manufacturing a display apparatus, including forming a drive circuit and a light-emitting portion on a substrate in which the forming the light-emitting portion includes forming a transparent anode electrode for applying a charge to an emission layer, forming a first coating layer and a second coating layer on the transparent anode electrode, removing the first coating layer by etching using the second coating layer as a mask, and forming a layer including the emission layer on a part of the transparent anode electrode from which the first coating layer is removed. A surface of the transparent anode electrode becomes as clean as a surface cleaned with ultraviolet irradiation.

Abstract: The present invention discloses a manufacturing method for a switch and an array substrate. The method comprises: firstly, forming sequentially a first metal layer, an insulating layer, a semiconductor layer, an ohmic contact layer, a second metal layer, a third metal layer and a photoresist layer on a base substrate; after patterning the photoresist layer, etching the third metal layer and the second metal layer to form the input electrode and the output electrode of the switch; using a stripper comprising at least 30% by weight of amine in order to remove the photoresist layer and the residual second metal layer; and finally, etching the ohmic contact layer. Through the above steps, the present invention can avoid the electrical abnormality of the switch and increase process yield of the array substrate.

Abstract: A method of manufacturing a thin film transistor array panel includes forming a semiconductor on a substrate, forming a gate insulating layer on the semiconductor, forming a sacrificial layer including an opening on the gate insulating layer, forming a copper layer on the sacrificial layer, the copper layer filling the opening, forming a gate wiring by polishing the copper layer by chemical mechanical polishing until the sacrificial layer is exposed, removing the sacrificial layer, forming a source region and a drain region by doping conductive impurities on the semiconductor by using the gate wiring as a mask, forming a first interlayer insulating layer covering the gate wiring, and forming a source electrode and a drain electrode connected to the source region and the drain region, respectively, on the first interlayer insulating layer.

Abstract: A display substrate includes a base substrate, a data line disposed on the base substrate, a gate line crossing the data line, a first insulation layer disposed on the base substrate, an active pattern disposed on the first insulation layer and comprising a channel comprising an oxide semiconductor, a source electrode connected to the channel, and a drain electrode connected to the channel, a second insulation layer disposed on the active pattern, and contacting to the source electrode and the drain electrode, a gate electrode disposed on the second insulation layer, and overlapping with the channel, a passivation layer disposed on the gate electrode and the second insulation layer, and a pixel electrode electrically connected to the drain electrode through a first contact hole formed through the passivation layer and the second insulation layer.

Abstract: A carbon nanotube field-effect transistor is disclosed. The carbon nanotube field-effect transistor includes a first carbon nanotube film, a first gate layer coupled to the first carbon nanotube film and a second carbon nanotube film coupled to the first gate layer opposite the first gate layer. The first gate layer is configured to influence an electric field within the first carbon nanotube film as well as to influence an electric field of the second carbon nanotube film. At least one of a source contact and a drain contact are coupled to the first and second carbon nanotube film and are separated from the first gate layer by an underlap region.

Abstract: The present invention provides an array substrate, which includes a plurality of pixel units, each pixel unit includes a thin film transistor, a pixel electrode, a common electrode and a passivation layer, the thin film transistor includes an active layer, a gate electrode, a source electrode and a drain electrode, the drain electrode and the pixel electrode are connected, the passivation layer is disposed on the active layer, the source electrode, the drain electrode and the pixel electrode, the common electrode is disposed above the pixel electrode with the passivation layer therebetween, a test electrode is disposed on the active layer and under the passivation layer, the test electrode is electrically insulated from the gate electrode, the source electrode and the drain electrode. Correspondingly, a method for fabricating and a method for testing the array substrate, and a display device including the array substrate are provided.

Abstract: An object is to reduce the manufacturing cost of a semiconductor device. An object is to improve the aperture ratio of a semiconductor device. An object is to make a display portion of a semiconductor device display a higher-definition image. An object is to provide a semiconductor device which can be operated at high speed. The semiconductor device includes a driver circuit portion and a display portion over one substrate. The driver circuit portion includes: a driver circuit TFT in which source and drain electrodes are formed using a metal and a channel layer is formed using an oxide semiconductor; and a driver circuit wiring formed using a metal. The display portion includes: a pixel TFT in which source and drain electrodes are formed using an oxide conductor and a semiconductor layer is formed using an oxide semiconductor; and a display wiring formed using an oxide conductor.

Abstract: A thin film transistor having a channel region including a nanoconductor layer. The nanoconductor layer can be a dispersed monolayer of nanotubes or nanowires formed of carbon. The thin film transistor generally includes a gate terminal insulated by a dielectric layer. The nanoconductor layer is placed on the dielectric layer and a layer of semiconductor material is developed over the nanoconductor layer to form the channel region of the thin film transistor. A drain terminal and a source terminal are then formed on the semiconductor layer. At low field effect levels, the operation of the thin film transistor is dominated by the semiconductor layer, which provides good leakage current performance. At high field effect levels, the charge transfer characteristics of the channel region are enhanced by the nanoconductor layer such that the effective mobility of the thin film transistor is enhanced.

Abstract: The present invention relates to methods for fabricating a thin film transistor substrate.

Abstract: An array substrate for a liquid crystal display (LCD) device includes a common line and gate lines. The array substrate includes a first, second, and third passivation layer and thin film transistors (TFTs). The second passivation layer includes first and second holes respectively corresponding to a drain electrode and the common line. A common electrode on the second passivation layer includes a first opening corresponding to the TFTs and a second opening in the second hole. A drain contact hole through the third and first passivation layers exposes the drain electrode. A first common contact hole through the third passivation layer exposes the common electrode in the second hole. A second common contact hole through the third and first passivation layers exposes the common line, and a pixel electrode includes a third opening and a connection pattern connecting the common electrode to the common line on the third passivation layer.

Abstract: A TFT array substrate includes: a pixel electrode, which is arranged in a pixel region formed in a matrix shape by a gate wiring and a source wiring on an insulating substrate; a switching element, which is disposed at an intersection of the gate wiring and the source wiring; a counter electrode, which is formed on the pixel electrode with interposing an insulating film; and a silicon film is formed on a lower layer so as to face the source wiring, wherein the source wiring and the pixel electrode are formed on the same layer by a transparent conductive material, and wherein the source wiring and the silicon film are formed so that end faces of the source wiring and the silicon film are overlapped and a width of the source wiring is identical to a width of the silicon film, in a plan view.

Abstract: A thin film transistor display panel includes a gate electrode on a substrate; a gate insulating layer on the substrate and the gate electrode; a planarization layer on the gate insulating layer and at opposing sides of the gate electrode, where the planarization layer exposes the gate insulating layer; a semiconductor layer on the gate insulating layer; and a source electrode and a drain electrode on the semiconductor layer and spaced apart from each other.

Abstract: A method for manufacturing fan-out lines on an array substrate is disclosed. The fan-out lines comprise an amorphous silicon layer, an ohmic contact layer and a source-drain electrode layer disposed on a gate insulating layer. The manufacturing processes can be conducted by forming a first layer of photoresist on the source-drain electrode layer and performing a half-exposure development process on the first layer of photoresist; etching the amorphous silicon layer, the ohmic contact layer and the source-drain electrode layer by an etching process; removing the first layer of photoresist; foiming a second layer of photoresist and performing full-exposure development process on the second layer of photoresist; and etching the amorphous silicon layer by etching process to form the fan-out lines.

Abstract: Embodiments of the present application provide an array substrate and a method for fabricating the same. The array substrate comprises: a base substrate, a plurality of thin film transistors formed on the base substrate; the array substrate also comprising: a buffer layer formed on the substrate between the substrate and the film transistors; wherein, the buffer layer is a metal oxide film layer. Embodiments of the present application also provide a display device having such array substrate.

Abstract: This disclosure provides systems, methods, and apparatus for flexible thin-film transistors. In one aspect, a device includes a polymer substrate, a gate electrode disposed on the polymer substrate, a dielectric layer disposed on the gate electrode and on exposed portions of the polymer substrate, a carbon nanotube network disposed on the dielectric layer, and a source electrode and a drain electrode disposed on the carbon nanotube network.

Abstract: A TFT substrate (100) is provided with TFTs disposed on a substrate (2), first insulating layers (24, 26) disposed above the TFTs, a lower layer transparent electrode (12) disposed above the first insulating layers (24, 26), a second insulating layer (28) covering the lower layer transparent electrode (12), and pixel electrodes (10) disposed on the second insulating layer (28), in which an auxiliary capacitance (Cs) is formed by means of the lower layer transparent electrode (12), the second insulating layer (28), and the pixel electrode (10). The TFT and the pixel electrode (10) are electrically connected via a contact hole (34) penetrating the first insulating layers (24, 26) and the second insulating layer (28). A connecting transparent electrode (14) is disposed within the contact hole (34).

Abstract: Organic polymeric multi-metallic alkoxide or aryloxide composites are used as dielectric materials in various devices with improved properties such as improved mobility. These composites comprise an organic polymer comprising metal coordination sites, and multi-metallic alkoxide or aryloxide molecules that are coordinated with the organic polymer, the multi-metallic alkoxide or aryloxide molecules being represented by: (M)n(OR)x wherein at least one M is a metal selected from Group 2 of the Periodic Table and at least one other M is a metal selected from any of Groups 3 to 12 and Rows 4 and 5 of the Periodic Table, n is an integer of at least 2, R represents the same or different alkyl or aryl groups, and x is an integer of at least 2.

Abstract: A method for manufacturing a thin-film transistor includes: preparing a substrate; forming a gate electrode above the substrate; forming a gate insulating layer above the gate electrode; forming a semiconductor film above the gate insulating layer; forming, above the semiconductor film, a protective layer comprising an organic material; forming a source electrode and a drain electrode which are opposed to each other and each of which has at least a portion located above the protective layer; forming a semiconductor layer patterned, by performing dry etching on the semiconductor film; and performing, in a hydrogen atmosphere, plasma treatment on an altered layer which (i) is a surface layer of the protective layer exposed from the source electrode and the drain electrode and altered by the dry etching, and (ii) has at least a portion contacting a surface of the semiconductor layer.

Abstract: A thin film transistor and method of manufacturing the same are disclosed. In one aspect, the thin film transistor includes a gate electrode positioned on a substrate It also includes a gate insulating layer positioned on the gate electrode and a semiconductor positioned on the gate insulating layer. It further includes a source electrode and a drain electrode positioned on the semiconductor, in which the semiconductor has a step at a boundary surface that is in contact with the gate insulating layer.

Abstract: A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes.

Abstract: A thin film transistor substrate including a thin film transistor having a drain electrode with an electrode portion, which overlaps with a semiconductor layer, and an extended portion, which extends from the electrode portion and has a portion overlapping with a storage electrode or storage electrode line. A passivation layer is arranged on the drain electrode, and it has a contact hole that partially exposes the extended portion of the drain electrode without exposing a step in the extended portion caused by the storage electrode or storage electrode line. A pixel electrode is arranged on the passivation layer and is electrically connected with the extended portion of the drain electrode through the contact hole.

Abstract: A method of fabricating an array substrate and a display device including the array substrate are discussed. According to an embodiment, the array substrate includes a gate electrode formed on a substrate; a gate insulating layer formed on the gate electrode; an oxide semiconductor layer and an etch prevention layer formed on the gate insulating layer, wherein ends of the oxide semiconductor layer and ends of the etch prevention layer are aligned with each other; source and drain electrodes formed on the etch prevention layer; a passivation layer including a contact hole formed on the source and drain electrodes and on the gate insulating layer; and a pixel electrode formed on the passivation layer and through the contact hole.

Abstract: In a thin film transistor which uses an oxide semiconductor, buffer layers containing indium, gallium, zinc, oxygen, and nitrogen are provided between the oxide semiconductor layer and the source and drain electrode layers.

Abstract: A manufacturing method of an arrayed substrate is disclosed, in which ion-doping is performed by using photoresist as a barrier layer instead of using a gate electrode, which process can reduces the short channel effect that is caused by diffusion of doped ions toward a channel region, and meanwhile decrease the coupling capacitance between the gate electrode and the source-drain electrodes, thereby improving the performance of the prepared TFT.

Abstract: A display panel device includes: a gate electrode above a substrate; a gate insulator above the gate electrode; a first source electrode and a first drain electrode above the gate insulator; a second source electrode and a second drain electrode above the first source electrode and the first drain electrode respectively; a first partition wall part having an opening in which the second source electrode and the second drain electrode are exposed; a semiconductor layer in the opening; an insulation layer above the semiconductor layer; a lower electrode above the insulation layer; and a contact hole in the insulation layer, for connecting the lower electrode and the second drain electrode or the second source electrode, wherein a film structure of each of the second source electrode and the second drain electrode is sparser than a film structure of each of the first source electrode and the first drain electrode.

Abstract: Embodiments of the present invention relate to an array substrate, a manufacturing method thereof and a display device. The manufacturing method of the array substrate comprises: preparing a base substrate; forming a gate electrode pattern on the base substrate; forming a gate insulating layer pattern on the base substrate with the gate electrode pattern formed thereon; and forming an active layer pattern, a pixel electrode pattern and source and drain patterns above the gate insulating layer pattern through a three-gray-tone mask process in one patterning process, wherein the gate electrode pattern, the active layer pattern, the source pattern and the drain pattern constitute a thin film transistor.

Abstract: The present invention discloses an active-matrix panel display device, a TFT and a method for forming the same The method includes that arranging a first insulating layer on a gate, stacking an oxide semiconductor layer and a buffer layer in order on the first insulating layer, arranging as source on the oxide semiconductor layer and a drain on the buffer layer, and plasma processing or heating in oxygen atmosphere the buffer layer which does not directly contact the source and the drain. Therefore, the present invention is capable of preventing the oxide semiconductor layer from damage in follow-up processes to assure stability of the TFT and display quality of the active-matrix panel display device.

Abstract: A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.

Abstract: A flat panel display device is disclosed. In one embodiment, the flat panel display device includes i) a semiconductor layer including a channel region and a groove, wherein the channel region electrically connects a source electrode and a drain electrode, and the groove is configured to separate the channel region from adjacent thin film transistors and ii) a stop layer formed below at least a portion of the semiconductor layer. According to one embodiment of the invention, a semiconductor layer can be easily patterned without using a dry or wet etching technique such as photolithography.

Abstract: Embodiments of the present invention provide a thin film transistor and its manufacturing method, an array substrate and a display device, to improve the electrical performance of the thin film transistor and improve the picture quality of images displayed by the display device. The thin film transistor includes: a substrate; a gate, a source, a drain and a semiconductor layer formed on the substrate; a first gate protection layer; a gate isolation layer; and a second gate protection layer. The first gate protection layer is at least partly located between the gate and the semiconductor layer, and is an insulating layer. The gate isolation layer is at least partly located between the first gate protection layer and the second gate protection layer, and is a conductive layer. The second gate protection layer is at least partly located between the gate isolation layer and the semiconductor layer, and is an insulating layer.

Abstract: To reduce parasitic capacitance between a gate electrode and a source electrode or drain electrode of a dual-gate transistor. A semiconductor device includes a first insulating layer covering a first conductive layer; a first semiconductor layer, second semiconductor layers, and an impurity semiconductor layer sequentially provided over the first insulating layer; a second conductive layer over and at least partially in contact with the impurity semiconductor layer; a second insulating layer over the second conductive layer; a third insulating layer covering the three semiconductor layers, the second conductive layer, and the second insulating layer; and a third conductive layer over the third insulating layer. The third conductive layer overlaps with a portion of the first semiconductor layer, which does not overlap with the second semiconductor layers, and further overlaps with part of the second conductive layer.

Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.

Abstract: The invention provides a graphene device structure and a method for manufacturing the same, the device structure comprising a graphene layer; a gate region in contact with the graphene layer; semiconductor doped regions formed in the two opposite sides of the gate region and in contact with the graphene layer, wherein the semiconductor doped regions are isolated from the gate region; a contact formed on the gate region and contacts formed on the semiconductor doped regions. The on-off ratio of the graphene device is increased through the semiconductor doped regions without increasing the band gap of the graphene material, i.e., without affecting the mobility of the material or the speed of the device, thereby increasing the applicability of the graphene material in CMOS devices.

Abstract: An object is to provide a manufacturing method of an oxide semiconductor film with high crystallinity. Another object is to provide a manufacturing method of a transistor with high field effect mobility. In a manufacturing method of an oxide semiconductor film, an oxide semiconductor film is formed over a substrate in an atmosphere in which oxygen is purposely not contained, and then the oxide semiconductor film is crystallized by a heat treatment in an atmosphere containing oxygen.

Abstract: One method disclosed herein includes forming a plurality of fin-formation trenches in a substrate that defines a plurality of fins, wherein at least one of the fins is a dummy fin, forming an insulating material that fills at least a portion of the trenches, forming a recess in a masking layer formed above the insulating material, forming a sidewall spacer on sidewalls of the recess so as to define a spacer opening, performing at least one first etching process on the masking layer through the spacer opening to define an opening in the masking layer that exposes a portion of the insulating material and the dummy fin, and performing at least one second etching process to remove at least a portion of the dummy fin and thereby define an opening in the insulating material.

Abstract: The present invention discloses a thin-film transistor (TFT) array substrate and a manufacturing method thereof. Depositing a transparent conductive layer and a first metal layer in turn on a substrate patterned by a first multi-tone mask (MTM) to form a gate, a common electrode and a reflecting layer; depositing a gate insulation layer and a semiconductor layer patterned by a second MTM to remain the semiconductor layer on the gate; and depositing a second metal layer patterned by a third MTM to form a source and a drain.

Abstract: An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current. The thin film transistor using an oxide semiconductor layer is formed by stacking an oxide semiconductor layer containing insulating oxide over the oxide semiconductor layer so that the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the oxide semiconductor layer containing insulating oxide interposed therebetween; whereby, variation in threshold voltage of the thin film transistors can be reduced and thus the electric characteristics can be stabilized. Further, an off current can be reduced.

Abstract: The present invention discloses a low temperature poly-silicon thin film transistor, a manufacturing method thereof, and a display device. Particularly, a metal film is formed between source and drain electrodes and a first conductive layer, and the metal film reacts with the poly-silicon of the source and drain electrodes to form metal silicide, whereby activating the source and drain electrodes at a low temperature. As such, the temperature of the manufacturing process of low temperature poly-silicon thin film transistor can be confined to 350° C. or lower.

Abstract: A semiconductor device includes a transistor which includes a gate electrode, a gate insulating film in contact with the gate electrode, and a stacked-layer oxide film facing the gate electrode with the gate insulating film provided therebetween. In the semiconductor device, the stacked-layer oxide film includes at least a plurality of oxide films, at least one of the plurality of oxide films includes a channel formation region, a channel length of the transistor is greater than or equal to 5 nm and less than 60 nm, and a thickness of the gate insulating film is larger than a thickness of the oxide film including the channel formation region.

Abstract: In an amorphous silicon thin film transistor-liquid crystal display device and a method of manufacturing the same, gate patterns including a gate line and a gate electrode are formed on an insulation substrate having a display region and a driving circuit region on which a plurality of shift resistors are formed. A gate insulating film, active layer patterns and data patterns including source/drain electrodes are formed successively on the substrate. A passivation layer on the substrate has a first contact hole exposing a drain electrode of the display region and second and third contact holes respectively exposing a gate electrode and source/drain electrode of a first transistor of each of the shift resistors.