Abstract: A method for manufacturing a semiconductor device is disclosed. The method comprises: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; forming a T-shape metal gate structure by filling a metal layer in the T-shape gate trench. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved.

Abstract: A multi-gate MOSFET includes a substrate, a dielectric layer and at least a fin-shaped structure. The substrate has a first area and a second area. The dielectric layer is only located in the substrate of the first area. At least a fin-shaped structure is located on the dielectric layer. Moreover, the present invention also provides a multi-gate MOSFET process forming said multi-gate MOSFET.

Abstract: There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.

Abstract: A method of forming a semiconductor device that includes providing a first strained layer of a first composition semiconductor material over a dielectric layer. A first portion of the layer of the first composition semiconductor material is etched or implanted to form relaxed islands of the first composition semiconductor material. A second composition semiconductor material is epitaxially formed over the relaxed island of the first composition semiconductor material. The second composition semiconductor material is intermixed with the relaxed islands of the first composition semiconductor material to provide a second strained layer having a different strain than the first strained layer.

Abstract: This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.

Abstract: Fabrication methods of a high frequency (sub-micron gate length) operation of AlInGaN/InGaN/GaN MOS-DHFET, and the HFET device resulting from the fabrication methods, are generally disclosed. The method of forming the HFET device generally includes a novel double-recess etching and a pulsed deposition of an ultra-thin, high-quality silicon dioxide layer as the active gate-insulator. The methods of the present invention can be utilized to form any suitable field effect transistor (FET), and are particular suited for forming high electron mobility transistors (HEMT).

Abstract: A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate electrode defining a surrounding channel region and having a gate dielectric material layer lining and including a conductive material having a top surface recessed to reduce overlap capacitance with respect to the source and drain diffusion regions formed at an upper substrate surface at either side of the gate electrode. There is optionally formed halo implants at either side of and abutting the gate electrode, each halo implants extending below the source and drain diffusions into the channel region. Additionally, highly doped source and drain extension regions are formed that provide a low resistance path from the source and drain diffusion regions to the channel region.

Abstract: A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.

Abstract: A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.

Abstract: A novel buried-channel graphene device structure and method for manufacture. The new structure includes a two level channel layer comprised of a buried-channel graphene layer with an amorphous silicon top channel layer. The method for making such structure includes the steps of depositing a graphene layer on a substrate, depositing an amorphous silicon layer on the graphene layer, converting the upper layer of the amorphous silicon layer to a gate dielectric by nitridation, oxidation or oxynitridation, while keeping the lower layer of the amorphous silicon layer to serve as part of the channel to form the buried-channel graphene device.

Abstract: A semiconductor device including at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. A method of fabricating a semiconductor structure includes forming an SOI substrate, forming a BOX layer over the SOI substrate, and forming at least one capacitor in wiring levels on the BOX layer, wherein the at least one capacitor is coupled to an active layer of the SOI substrate.

Abstract: Provided is a metal oxide semiconductor (MOS) capacitor, in which trenches (3) are formed in a charge accumulation region (6) of a p-type silicon substrate (1) to reduce a contact area between the p-type silicon substrate (1) and a lightly doped n-type well region (2), thereby reducing a leak current from the lightly doped n-type well region (2) to the p-type silicon substrate (1).

Abstract: A method of manufacturing a fin structure comprises forming a first structure of a first material type on a wafer and forming a buried channel of a second material adjacent sidewalls of the first structure. The second material type is different than the first material type. The structure includes a first structure and a buried channel.

Abstract: Known drawbacks associated with use of tungsten as a gate material in a semiconductor device are prevented. A gate oxide layer, a polysilicon layer, and a nitride layer are sequentially formed on a semiconductor substrate having a isolation layer for defining the active region. A groove is formed by etching the nitride layer. A metal nitride layer is formed to an U shape in the groove, and then a metal layer is formed to bury the groove. A hard mask layer is formed for defining a gate forming region on the nitride layer, the metal nitride layer, and the metal layer. A metal gate is formed by etching the nitride layer, the polysilicon layer, and the gate oxide layer using the hard mask layer as an etch barrier.

Abstract: A MLD-SIMOX wafer is obtained by forming a first ion-implanted layer in a silicon wafer; forming a second ion-implanted layer that is in an amorphous state; and subjecting the wafer to a high-temperature heat treatment to maintain the wafer in an atmosphere containing oxygen at a temperature that is not lower than 1300° C. but lower than a silicon melting point to change the first and the second ion-implanted layers into a BOX layer, wherein the dose amount for the first ion-implanted layer is 1.25 to 1.5×1017 atoms/cm2, the dose amount for the second ion-implanted layer is 1.0×1014 to 1×1016 atoms/cm2, the wafer is preheated to a temperature of 50° C. to 200° C. before forming the second ion-implanted layer, and the second ion-implanted layer is formed in a state where it is continuously heated to a preheating temperature.

Abstract: In an embodiment of the present invention, a Trench MOSFET includes a trench region provided on a semiconductor substrate. The semiconductor substrate includes a P-type semiconductor substrate, a P-type semiconductor epitaxial layer, an N-type semiconductor body region, and a P-type semiconductor source diffusion. The substrate, the epitaxial layer, the body region, and the source diffusion are adjacently formed in this order. A P-type semiconductor channel region formed of a SiGe layer is provided on a bottom surface and a side wall of the trench region. This facilitates carrier movement in the channel region, reducing ON resistance of the Trench MOSFET. Thus, a Trench MOSFET allowing reduction in the ON resistance without reducing a breakdown voltage is realized.

Abstract: A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.

Abstract: Methods and resulting structure of forming a transistor having a high mobility channel are disclosed. In one embodiment, the method includes providing a gate electrode including a gate material area and a gate dielectric, the gate electrode being positioned over a channel in a silicon substrate. A dielectric layer is formed about the gate electrode, and the gate material area and the gate dielectric are removed from the gate electrode to form an opening into a portion of the silicon substrate that exposes source/drain extensions. A high mobility semiconductor material, i.e., one having a carrier mobility greater than doped silicon, is then formed in the opening such that it laterally contacts the source/drain extensions. The gate dielectric and the gate material area may then be re-formed. This invention eliminates the high temperature steps after the formation of high mobility channel material used in related art methods.

Abstract: A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.

Abstract: By incorporating an atomic species of increased covalent radius, which may at least partially substitute germanium, a highly efficient strain mechanism may be provided, in which the risk of stress relief due to germanium conglomeration and lattice defects may be reduced. The atomic species of increased radius, such as tin, may be readily incorporated by epitaxial growth techniques on the basis of tin hydride.

Abstract: A MESFET and method for fabricating a MESFET are provided. The method includes forming an n-type channel portion in a substrate and forming a p-type channel portion in the substrate. A boundary of the n-type channel portion and a boundary of the p-type channel portion define an intrinsic region in the substrate.

Abstract: A method of fabricating Group III-V semiconductor metal oxide semiconductor (MOS) and III-V MOS devices are described.

Abstract: Methods for forming semiconductor devices are provided. A semiconductor substrate is etched such that the semiconductor substrate defines a trench and a preliminary active pattern. The trench has a floor and a sidewall. An insulating layer is provided on the floor and the sidewall of the trench and a spacer is formed on the insulating layer such that the spacer is on the sidewall of the trench and on a portion of the floor of the trench. The insulating layer is removed on the floor of the trench and beneath the spacer such that a portion of the floor of the trench is at least partially exposed, the spacer is spaced apart from the floor of the trench and a portion of the preliminary active pattern is partially exposed. A portion of the exposed portion of the preliminary active pattern is partially removed to provide an active pattern that defines a recessed portion beneath the spacer. A buried insulating layer is formed in the recessed portion of the active pattern. Related devices are also provided.

Abstract: In a method of fabricating a fin field effect transistor having a plurality of protruding channels, the fin field effect transistor is formed by forming a dummy gate pattern on a first hard mask pattern and a first insulating layer on a semiconductor substrate having an active region pattern, forming a source and drain region in a portion of the active region pattern, forming a plurality of vertically protruding channels between the source and drain region, forming a gate dielectric layer on the active region pattern having the plurality of protruding channels, and forming a gate electrode on the gate dielectric layer.

Abstract: Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the output lines form an array. A number of logic cells are formed at the intersections of output lines and address lines. Each of the logic cells includes a floating gate transistor which includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposing the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5 and/or a Perovskite oxide tunnel barrier.

Abstract: An integrated Schottky diode and method of manufacture of such a diode is disclosed. In a first aspect, a Schottky diode comprises a semiconductor substrate. The semiconductor substrate includes an epitaxial layer (EPI) on the substrate region. The diode includes a plurality of guard rings in the EPI layer and a plurality of oxidized slots. Finally, the diode includes metal within the plurality of slots to form a Buried Power Buss. A portion of the metal is completely oxide isolated from the other elements of the diode. In a second aspect, a method for manufacturing a Schottky diode comprises providing a substrate region, A buried N+ region providing an epitaxial (EPI) layer. The method also includes providing a plurality of guard rings in the EPI layer and providing a plurality of slots in the semiconductor substrate that is in contact with the EPI layer and the substrate region.

Abstract: A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a SiGe feature, depositing a layer having a first thickness above the oxide layer and the SiGe feature, and forming source and drain regions in the layer.

Abstract: A microwave field effect transistor (10) has a high conductivity gate (44) overlying a double heterojunction structure (14, 18, 22) that has an undoped channel layer (18). The heterojunction structure overlies a substrate (12). A recess layer that is a not intentionally doped (NID) layer (24) overlies the heterojunction structure and is formed with a predetermined thickness that minimizes impact ionization effects at an interface of a drain contact of source/drain ohmic contacts (30) and permits significantly higher voltage operation than previous step gate transistors. Another recess layer (26) is used to define a gate dimension. A Schottky gate opening (42) is formed within a step gate opening (40) to create a step gate structure. A channel layer (18) material of InxGa1?xAs is used to provide a region of electron confinement with improved transport characteristics that result in higher frequency of operation, higher power density and improved power-added efficiency.

Abstract: It is intended to achieve the reduction in number of heat treatments carried out at high temperature (at least 600° C.) and the employment of lower temperature processes (600° C. or lower), and to achieve step simplification and throughput improvement. In the present invention, a barrier layer (105), a second semiconductor film (106), and a third semiconductor layer (108) containing an impurity element (phosphorus) that imparts one conductive type are formed on a first semiconductor film (104) having a crystalline structure. Gettering is carried out in which the metal element contained in the first semiconductor film (104) is allowed to pass through the barrier layer (105) and the second semiconductor film (106) by a heat treatment to move into the third semiconductor film (107). Afterward, the second and third semiconductor films (106) and (107) are removed with the barrier layer (105) used as an etching stopper.

Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

Abstract: Methods and apparatus are provided for creating field effect transistor (FET) body connections with high-quality matching characteristics and no area penalty for partially depleted silicon-on-insulator (SOI) circuits. The FET body connections are created for partially depleted silicon-on-insulator (SOI) technologies by forming adjacent FET devices inside a shallow trench shape. The adjacent FET devices share a common diffusion area, such as source or drain. Selectively spacing apart adjacent gate lines form an underpath connecting bodies of the adjacent FET devices. The underpath is defined by forming an undepleted region on top of a buried oxide layer. The adjacent polysilicon gate lines are selectively spaced apart to define a depth of depletion in a shared diffusion region for creating the underpath. Also, adjacent FET devices with connecting bodies can be built by adding an ion implant masking step to the fabrication process. This masking step changes the depletion depth under the shared diffusion area.

Abstract: A method of fabricating a memory cell is described in which an access transistor is first formed on an SOI substrate. The access transistor contains source and drain regions in a semiconductor material layer of the substrate and at least one gate stack which includes a gate region electrically connected with a word line. At least one capacitor is formed con a first side of the substrate and is electrically connected to one of the source and drain regions. At least one bit line conductor is formed on the reverse or flip side of the substrate, wherein the bit line conductor is electrically connected to the other of the source and drain regions. Self-aligned contact openings are formed through insulative material over the substrate to provide vias for the electrical connections for each of the capacitor and bit line conductor. These contact openings and the deposited contact material are substantially preserved throughout the entire fabrication process.

Abstract: A method for moving resist stripper across the surface of a semiconductor substrate. The method includes applying a wet chemical resist stripper, such as an organic or oxidizing wet chemical resist stripper, to at least a portion of a photomask positioned over the semiconductor substrate. A carrier fluid, such as a gas, is then directed toward the semiconductor substrate so as to move the resist stripper across the substrate. The carrier fluid may be directed toward the substrate as the resist stripper is being applied thereto or following application of the resist stripper. A system for effecting the method is also disclosed.

Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor substrate between first diffusion layers, a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gate portion, a first width in a channel direction of the first gate portion being substantially equal to a width in that of the gate insulating film, and a second width in the channel direction of the second gate portion being larger than the first width, a gate side wall insulating film including a first side wall portion formed on a side surface of the first gate portion and the gate insulating film and a second side wall portion formed on a side surface of the second gate portion, and a second diffusion layer formed apart from the first diffusion layers below the gate insulating film.

Abstract: A method of fabricating a memory cell is described in which an access transistor is first formed on an SOI substrate. The access transistor contains source and drain regions in a semiconductor material layer of the substrate and at least one gate stack which includes a gate region electrically connected with a word line. At least one capacitor is formed on a first side of the substrate and is electrically connected to one of the source and drain regions. At least one bit line conductor is formed on the reverse or flip side of the substrate, wherein the bit line conductor is electrically connected to the other of the source and drain regions. Self-aligned contact openings are formed through insulative material over the substrate to provide vias for the electrical connections for each of the capacitor and bit line conductor. These contact openings and the deposited contact material are substantially preserved throughout the entire fabrication process.

Abstract: A method of fabricating a buried contact. On a substrate having a shallow trench isolation thereon, a gate oxide layer and a polysilicon layer are sequentially formed. The polysilicon layer and the gate oxide layer are patterned to expose a portion of the substrate. A diffusion region is formed in the exposed substrate. On the polysilicon layer and the exposed diffusion region, an amorphous silicon layer is formed. Consequently, a native oxide layer is formed between the polysilicon layer and the amorphous silicon layer, and between the amorphous silicon layer and the diffusion region. An anti-reflection coating layer is formed on the amorphous silicon layer. Using the native oxide layer as an etching buffer, the anti-reflection coating layer and the amorphous silicon layer are patterned until the diffusion region and the polysilicon layer are exposed.

Abstract: A process of forming on a monocrystalline-silicon body an etching-aid region of polycrystalline silicon; forming, on the etching-aid region a nucleus region of polycrystalline silicon surrounded by a protective structure having an opening extending as far as the etching-aid region; TMAH-etching the etching-aid region and the monocrystalline body to form a tub-shaped cavity; removing the top layer of the protective structure; and growing an epitaxial layer on the monocrystalline body and the nucleus region. The epitaxial layer, of monocrystalline type on the monocrystalline body and of polycrystalline type on the nucleus region, closes upwardly the etching opening, and the cavity is thus completely embedded in the resulting wafer.

Abstract: The method for fabricating a semiconductor device comprises the steps of forming on a semiconductor substrate a gate electrode, and an eave-shaped film of an inorganic material formed on the upper surface of the gate electrode and having a eave-shaped portion projected beyond the edge of the gate electrode; and ion-implanting a dopant with the gate electrode as a mask and with the eave-shaped portion of the eave-shaped film as a through film to form a first diffusion layer in the semiconductor substrate immediately below the eave-shaped portion and a second diffusion layer which is connected to the first diffusion layer, and is deeper and has a higher dopant concentration than the first diffusion layer, in the semiconductor substrate in a region where the eave-shaped film is not formed.

Abstract: A process of manufacturing a semiconductor device including a buried channel field effect transistor comprising, for realizing said field effect transistor, steps of forming a stacked arrangement of semiconductor layers on a substrate including an active layer (3), forming a recess in said active layer, referred to as gate recess (A4), for constituting a channel between source and drain electrodes, and forming a submicronic gate electrode (G) which is in contact with the active layer (3) in said gate recess (A4), wherein:

Abstract: A transistor structure with a degradation-stop layer that prevents degradation of underlying semiconductor layers while minimizing any increase in the gate leakage current is disclosed. In one embodiment, a transistor structure includes: a substrate; a channel layer formed of a charge transport material over the substrate; a Schottky barrier layer formed of an aluminum-containing material over the channel layer; a degradation-stop layer formed of a substantially aluminum-free material over the Schottky barrier layer; and a source, a drain and a gate. The source and the drain being formed over or alloyed through the degradation-stop layer, and a lower portion of the gate extends down through an exposed portion of the degradation-stop layer and is in physical and electrical contact with the Schottky barrier layer.

Abstract: The method includes patterning a first polysilicon layer on a substrate. A first dielectric having a first via hole is defined over the substrate. A second polysilicon layer is formed along the surface of the first dielectric layer and refilled into the first via hole. Then, an etching is used to etch the layer. A residual portion of the layer is located at the lower portion of the first via hole. An undoped polysilicon is then patterned on the first dielectric layer and along the surface of the first via hole. An isolation structure is then refilled into the first via hole. An oxide layer is formed on the first polysilicon, the first dielectric layer and the upper surface of isolation structure to act as the gate oxide of the TFT. Then, the oxide and the first dielectric layer are etched to define a second via hole. A further polysilicon layer is pattern on the first dielectric layer and refilled into the second via hole for defining the gate.

Abstract: In a compound semiconductor device constituting a field effect transistor having a buried p region 3, a channel region 4 is formed thin and highly doped by n-type impurity, and the buried p region 3 is formed shallowly and highly doped by p-type impurity to compensate the highly doped channel region 4. In order to prevent a leakage current between the highly doped buried p region 3 and a gate electrode 5, a low concentration p-type impurity region 2 is formed on both sides of the highly doped buried p region 3 to thus prevent a current flow via a portion other than a channel region. Accordingly, there can be provided the compound semiconductor device including an FET which is able to suppress both the deterioration in the pinch-off characteristic and the leakage current between neighboring elements due to p-type impurity conduction other than a channel in an FET which has a high concentration and thin active layer, while suppressing the short channel effect.

Abstract: The present invention provides a method of fabricating a field-effect transistor comprising the steps of forming a masking layer having an opening therein on laminated compound semiconductor layers, removing a portion of the laminated layers using an etching solution acting through the opening and creating a gate-forming recess having sidewalls tapering in a direction away from the masking layer, filling the gate-forming recess with gate metal and forming a gate electrode, and forming a recess around the gate electrode.

Abstract: A crystal growth 301 is carried out by diffusing a metal element, and a nickel element is moved into regions 108 and 109 which has been doped with phosphorus. An axis coincident with the moving directions 302 and 303 of the nickel element at this time is made to coincide with an axis coincident with the direction of the crystal growth, and a TFT having the regions as channel forming regions is manufactured. In the path of the region where nickel moved, since high crystallinity is obtained in the moving direction, the TFT having high characteristics can be obtained by this way.

Abstract: A method for forming a dual inlaid contact structure (damascene) begins by etching dual inlaid contact structures (32, 34, and 36). Masking layers (28) are (228) and the deposition of low-K dielectric material 26 is used to selectively form low-K regions (30) only in critical areas where low-K dielectric material is absolutely needed. Other portions of the wafer remain covered with conventional oxide (24) so that adverse impacts of low-K dielectric material is minimized. Conductive material (38, 40, and 42) is then formed to complete dual inlaid contact structures whereby low-K dielectric plugs (30) reduce cross talk and capacitance within the final structure.

Abstract: A memory cell having a grooved gate formed in a sub-lithographic groove, and methods of making thereof are disclosed. The groove extends the channel length to include the groove sidewalls and width of the groove. Sidewall sections of the channel located along the gate sidewalls have a larger length than the bottom channel section length located along the gate bottom width. Thus, the memory device is primarily controlled by the sidewall channel sections, instead of the bottom channel section. The groove may be a stepped groove formed by a two step etch to further increase the channel length and may be formed centered along the gate conductor width.

Abstract: A thin film transistor which includes an oxide layer containing a trench; a semiconductor layer formed on the oxide layer, including the trench; a buffer layer formed on the semiconductor layer in the trench; a gate electrode aligned on the semiconductor layer on one side of the trench; and an impurity region formed in the semiconductor layer adjacent the gate electrode on one side of the trench, and an impurity region also formed in the semiconductor layer on the other side of the trench.

Abstract: The present invention proposes a method for fabricating a high-density shallow trench contactless nonvolatile memory. First, a stacked pad oxide/silicon nitride layer is deposited on the substrate and the buried bit line region is defined by a photoresist. An anisotropic etching follows to etch the silicon layer and then the n+ impurity ions are implanted to form the source and drain. After stripping the photoresist, a high temperature steam oxidation process is used to grow a thick field oxide, and the doped ions are active and driven in to form the buried bit lines simultaneously. The silicon nitride layer and the pad oxide layer are then removed, and the silicon substrate is recessed by using the field oxide as an etching mask. After rounding the trench corners by using thermal oxidation and etching back processes, a thin silicon oxy-nitride film is regrown. An in-situ doped polysilicon film is deposited to refill the trench region and then etch back by using a CMP process to form the floating gates.

Abstract: A semiconductor process in which a trench transistor is formed between a pair of planar transistors such that the source/drain regions of the trench transistor are shared with the source/drain regions of the planar transistors. A substrate is provided and first and second planar transistors are formed upon the upper surface of the substrate. The gate dielectric of the trench transistor is vertically displaced below the upper surface of the substrate. The trench transistor shares a first shared source/drain structure with the first planar transistor and a second shared source/drain structure with the second planar transistor. The formation of the trench transistor preferably includes the steps of etching a trench into the substrate, thermally oxidizing a floor of the trench to form a trench gate dielectric, and filling the trench with a conductive material to form a trench gate structure. The trench floor is vertically displaced below the upper surface of the substrate by a trench depth.

Abstract: There is provided a technique for fabricating a thin film transistor having excellent performance. A configuration is employed in which when the thin film transistor is in an on-state, the flowing direction of the on-current coincides with the direction of crystal growth. With such a configuration, grain boundaries of the crystalline silicon in the active layer will not block the on-current. Further, when the thin film transistor is in an off-state, the off-current is always orthogonal to the grain boundaries of the crystalline silicon. The grain boundaries of the crystalline silicon effectively suppresses the off-current in such locations.