Abstract: A method of manufacturing a semiconductor device including a complementary metal oxide semiconductor (CMOS) and a bipolar junction transistor (BJT), the method comprising the steps of: forming a gate oxide layer on a substrate having a p-type and an n-type well; removing the gate oxide layer on the p-type well; forming bases on the p-type well; forming a first photosensitive layer pattern that exposes the bases on the substrate; implanting p-type impurity ions into the bases through the first photosensitive layer pattern; removing the first photosensitive layer pattern; forming a second photosensitive layer pattern that exposes the p-type and the n-type wells; and implanting n-type impurity ions into the p-type and the n-type wells through the second photosensitive layer pattern to form an emitter and a collector, respectively, to form the BJT. Therefore, CMOS manufacturing processes are used to form a high frequency BJT having improved frequency and noise characteristics.

Abstract: A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices having different optimum unity current gain cutoff frequency (fT) and breakdown voltage (BVCEO and BVCBO) on a common wafer.

Abstract: A semiconductor device comprising: a first insulating film formed on a semiconductor substrate; a semiconductor layer at least a part of which is formed on the first insulating film; a second insulating film comprising a non-doped silicon oxide film and formed on the semiconductor layer; a third insulating film comprising a silicon oxide film containing at least phosphorus formed on the second insulating film; and a fourth insulating film comprising a non-doped silicon oxide film formed on the third insulating film.

Abstract: A method for forming a SiGe HBT, which combines a SEG and Non-SEG growth, is disclosed. The SiGe base layer is deposited by a Non-SEG method. Then, the first-emitter layer is developed directly upon the SiGe base layer that has a good interface quality between the base-emitter. Next, a second poly silicon layer, which has a dopant concentration range within 1E19 to 1E21 (atom/cc), is deposited by SEG method. It not only reduces the resistance of the SiGe base layer, but also avoids the annealing that may influence the performance of the device.

Abstract: The following layers are successively formed on a heavily-doped n-type first subcollector layer: a heavily-doped n-type second subcollector layer made of a material having a small band gap; an i-type or a lightly-doped n-type collector layer; a heavily-doped p-type base layer; an n-type emitter layer made of a material having a large band gap; a heavily-doped n-type emitter cap layer; and a heavily-doped n-type emitter contact layer made of a material having a small band gap. Alloying reaction layers are formed under an emitter electrode, a base electrode and a collector electrode.

Abstract: A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed after the low dose implant. A gate definition spacer is then formed on the wall the trench to establish the lateral extent of a second, high dose implant gate region. After the second implant, the gate is annealed. The double dose gate structure produced by the superposition of two different and overlapping regions provides an additional degree of flexibility in determining the ultimate gate region doping profile. A further step comprises using the gate definition spacer to define the walls of a second etched trench that is used to remove a portion of the p-n junction, thereby further reducing the junction capacitance.

Abstract: The object of the present invention is to provide a semiconductor device, which is suitable for use to connect electric condenser microphones. A semiconductor device, comprises: a conductivity-type substrate; an epitaxial layer formed on top of the substrate; island regions separating the epitaxial layer; an input transistor formed on one of the island regions; an insulation layer covering the surface of the input transistor layer; an expansion electrode formed above the insulation layer so as to provide an electrical connection to an input terminal of the input transistor; and resistivity of the epitaxial layer formed below the expansion electrode being in a range of 1000˜5,000 ?·cm.

Abstract: A bipolar transistor in which the occurrence of Kirk effect is suppressed when a high current is injected into the bipolar transistor and a method of fabricating the bipolar transistor are described. The bipolar transistor includes a first collector region of a first conductive type having high impurity concentration, a second collector region of a first conductive type which has high impurity concentration and is formed on the first collector region, a base region of a second conductive type being formed a predetermined portion of the second collector region, and an emitter region of a first conductive type being formed in the base region. The bipolar transistor further includes the third collector region, which has higher impurity concentration than the second collector region, at the bottom of the base region.

Abstract: A BiCMOS semiconductor, and manufacturing method therefore, is provided. A semiconductor substrate having a collector region is provided. A pseudo-gate is formed over the collector region. An emitter window is formed in the pseudo-gate to form an extrinsic base structure. An undercut region beneath a portion of the pseudo-gate is formed to provide an intrinsic base structure in the undercut region. An emitter structure is formed in the emitter window over the intrinsic base structure. An interlevel dielectric layer is formed over the semiconductor substrate, and connections are formed through the interlevel dielectric layer to the collector region, the extrinsic base structure, and the emitter structure. The intrinsic base structure comprises a compound semiconductive material such as silicon and silicon-germanium, or silicon-germanium-carbon, or combinations thereof.

Abstract: Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.

Abstract: A polysilicon-emitter-type transistor has a substrate with a collector region, a base region on the collector region, and an oxide layer on the base region with an emitter window therein exposing part of the base region. The polysilicon emitter is formed by forming a first polysilicon layer of approximately 30 to 100 Angstroms at least within the emitter window and at least on the exposed base region. Then, an interfacial oxide layer being approximately 5 to 50 Angstroms thick is formed in an upper portion of the first polysilicon layer, for example, by exposing the first polysilicon layer to oxygen and annealing. Then, a second polysilicon layer is formed on the interfacial oxide layer. The thickness of the second polysilicon layer may be approximately 500 to 5000 Angstroms thick. Subsequent annealing diffuses dopants in the emitter more uniformly into the base region.

Abstract: The object of the present invention is to provide a semiconductor device, which is suitable for use to connect electric condenser microphones. A semiconductor device, comprises: a conductivity-type substrate; an epitaxial layer formed on top of the substrate; island regions separating the epitaxial layer; an input transistor formed on one of the island regions; an insulation layer covering the surface of the input transistor layer; an expansion electrode formed above the insulation layer so as to provide an electrical connection to an input terminal of the input transistor; and resistivity of the epitaxial layer formed below the expansion electrode being in a range of 1000˜5,000 &OHgr;·cm.

Abstract: An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor deposition. Nitrogen implantation is expected to minimize oxide growth variation.

Abstract: A lateral bipolar transistor with a doped zone of a small lateral width can be obtained by means of a method for manufacturing a lateral bipolar transistor with a collector region and a base region in a SOI wafer slice with an insulating layer, a silicon layer over the insulating layer, with a protective coating of oxide over the silicon layer, with trenches through the protective layer and the silicon layer as far as the insulating layer with substantially lateral walls, which are bounded by substantially lateral faces of the protective coating and the silicon layer, by implanting dopants in the silicon layer, in which the implantation takes place on one of the substantially lateral faces of the silicon layer.

Abstract: According to one embodiment of the invention, a method for manufacturing bipolar junction transistors includes disposing a first oxide layer between a semiconductor substrate and a base polysilicon layer, forming a dielectric layer outwardly from the base polysilicon layer, and forming an emitter region by removing a portion of the dielectric layer and a portion of the base polysilicon layer. The method further includes removing a portion of the first oxide layer to form undercut regions adjacent the emitter region and to enlarge the emitter region, and forming an oxide pad outwardly from the semiconductor substrate in the emitter region.

Abstract: A lateral bipolar field effect transistor having a drift region of a first conductivity formed on a silicon-on insulation substrate with a buried insulation layer, a gate region of a second conductivity formed over and from the buried insulation layer separated by a channel depth, in the drift region, a source region of the first conductivity contacting with the gate region and formed on the buried insulation layer, and a drain region of the first conductivity opposite to the source region, the drain region separated from the gate region by a selected distance. The gate region comprises a plurality of cells arranged parallel to an extension of the source region, each cell separated from adjacent cell by a channel width.

Abstract: The present invention includes field effect transistors, field emission apparatuses, thin film transistors, and methods of forming field effect transistors. According to one embodiment, a field effect transistor includes a semiconductive layer configured to form a channel region; a pair of spaced conductively doped semiconductive regions in electrical connection with the channel region of the semiconductive layer; a gate intermediate the semiconductive regions; and a gate dielectric layer intermediate the semiconductive layer and the gate, the gate dielectric layer being configured to align the gate with the channel region of the semiconductive layer. In one aspect, chemical-mechanical polishing self-aligns the gate with the channel region. According to another aspect, a field emission device includes a transistor configured to control the emission of electrons from an emitter.

Abstract: Upon fabrication of semiconductor devices, a semiconductor substrate is subjected to ion implantation with high energy. Subsequent annealing of the ion-implanted semiconductor substrate, when conducted by heating the substrate to a temperature of from 1,000° C. to 1,200° C. at a ramp-up rate of at least 200° C./sec, makes it possible to provide the resulting semiconductor devices with smaller leakage currents of reduced variations (&sgr;/X). The present invention can therefore provide a process for the fabrication of semiconductor devices featuring both smaller leakage currents and reduced variations of the leakage currents even when ion implantation is conducted with high energy.

Abstract: The present invention relates to a solar cell (10) comprising a semiconductor body (12) having an n+p junction. In order that the solar cell exhibits a good EOL behavior, it is proposed that the solar cell (10) comprise first and second areas (28, 30, 32, 34, 48) having differing thicknesses (d1, d2), the first area (28, 30, 48) forming a support structure of the solar cell and the second area (32, 34) having a considerably lower thickness than the first area.

Abstract: A semiconductor device such as a light emitting semiconductor device comprising a mask layer having opening areas and a selective growing layer comprising a semiconductor grown selectively by way of the mask layer, with each of the mask layer and the selective growing layer being disposed by two or more layers alternately. The semiconductor device is manufactured by a step of laminating on a substrate a mask layer having opening areas and a selective growing layer comprising a semiconductor grown selectively way of a mask layer, each by two or more layers alternately and a subsequent step of laminating semiconductor layers thereon. Threading dislocations in the underlying layer are interrupted by the first mask layer and the second mask layer and do not propagate to the semiconductor layer. The density of the threading dislocations is lowered over the entire surface and the layer thickness can be reduced.

Abstract: A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substrat

Abstract: The present invention relates to a method of manufacturing a JFET transistor in an integrated circuit containing complementary MOS transistors, this JFET transistor being formed in an N-type well of a P-type substrate, including the steps of forming a P-type channel region at the same time as lightly-doped drain/source regions of the P-channel MOS transistors of; forming an N-type gate region at the same time as lightly-doped drain/source regions of the N-channel MOS transistors; and forming P-type drain/source regions at the same time as heavily-doped drain/source regions of P-channel MOS transistors of channel.

Abstract: A highly uniform, planar and high speed JHEMT-HBT MMIC is fabricated using a single growth process. A multi-layer structure including a composite emitter-channel layer, a base-gate layer and a collector layer is grown on a substrate. The composite emitter-channel layer includes a sub-emitter/channel layer that reduces the access resistance to the HBT's emitter and the JHEMT's channel, thereby improving the HBT's high frequency performance and increasing the JHEMT's current gain. The multi-layer structure is then patterned and metallized to form an HBT collector contact, planar HBT base and JHEMT gate contacts, and planar HBT emitter and JHEMT source and drain contacts.

Abstract: A method for preventing damage to a gate oxide layer from a floating well in a CMOS device includes a first via plug and a second via plug formed in a dielectric layer. The first via plug is coupled to a substrate and the second via plug is coupled to the well. These two via plugs are further coupled by a conductive bridge so that both the well and the substrate have the same voltage.

Abstract: An N-channel JFET (60) and a method of forming the N-channel JFET (60) in a BiCMOS process. The N-channel JFET (60) is monolithically fabricated with an N-channel IGFET (70), a P-channel IGFET (75), and an NPN BJT (80) in an epitaxial layer (21). The N-channel JFET (60) is formed in an isolated N-channel JFET region (24), the P-channel IGFET (75) is formed in an isolated P-channel IGFET region (27), and the NPN BJT (80) is formed in an isolated BJT region (29). The N-channel IGFET (70) is fabricated in a P-type well (26) that is not isolated from other N-channel IGFET's in the epitaxial layer (21). Accordingly, the N-channel JFET (60), the N-channel IGFET (70), the P-channel IGFET (75), and an NPN BJT (80) are monolithically formed in the BiCMOS process.