Abstract: The object of the present invention is to provide a semiconductor device, which is suitable for use to connect electric condenser microphones. A semiconductor device, comprises: a conductivity-type substrate; an epitaxial layer formed on top of the substrate; island regions separating the epitaxial layer; an input transistor formed on one of the island regions; an insulation layer covering the surface of the input transistor layer; an expansion electrode formed above the insulation layer so as to provide an electrical connection to an input terminal of the input transistor; and resistivity of the epitaxial layer formed below the expansion electrode being in a range of 1000˜5,000 &OHgr;·cm.

Abstract: A method of improving the tolerance of a back-end-of-the-line (BEOL) thin film resistor is provided. Specifically, the method of the present invention includes an anodization step which is capable of converting a portion of base resistor film into an anodized region. The anodized resistor thus formed has a sheet resistivity that is higher than that of the base resistor film.

Abstract: A silicon semiconductor substrate has a plurality of active regions having an impurity region and an isolating region which electrically isolates these active regions from each other. The isolating region is formed of a silicon nitride film. A contact hole penetrates an interlayer insulating film and reaches an impurity region. In this semiconductor device, when the contact hole falls across the impurity region and the isolating region, an amount of erosion in the isolating region is reduced.

Abstract: A semiconductor fabrication apparatus, located in an apparatus installation area, includes a front-opening unified pod (FOUP) index, a plate, a first transfer device, a second transfer device, and an engineering FOUP index and multiple processing chambers. The FOUP index can be located in a line, vertically, horizontally, on top, and on bottom. The engineering FOUP index is used for manually locating the FOUP thereon in case of processing irregular single wafers that are not stored in a lot. As the FOUP index is located in the semiconductor fabrication apparatus installed in the apparatus installation area, dead space between the apparatus and air eddies generated above and below the FOUP index can be eliminated to increase the efficiency of working area and improve the environment in fabrication.

Abstract: When a plasma is ignited in a plasma generator, an ion beam is made to run in the plasma generator, and in this state, a positive voltage with respective to ground is applied to a plasma production chamber from a DC power source. Secondary electrons are generated when the ion beam collides with a plasma generating gas which flows out of the plasma production chamber into a path of the ion beam. The secondary electrons are led into the plasma production chamber by the positive voltage, and within the plasma production chamber, a plasma ignition is triggered using the secondary electrons led into the plasma production chamber and a radio frequency.

Abstract: The integrated inductor comprises a coil of metal which is formed in the second metal level. The coil is supported by a bracket extending above spaced from a semiconductor material body by an air gap obtained by removing a sacrificial region formed in the first metal level. The bracket is carried by the semiconductor material body through support regions which are arranged peripherally on the bracket and are separated from one another by through apertures which are connected to the air gap. A thick oxide region extends above the semiconductor material body, below the air gap, to reduce the capacitive coupling between the inductor and the semiconductor material body. The inductor thus has a high quality factor, and is produced by a process compatible with present microelectronics processes.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: A unitary-formed electrode structure serving as both a collector and a polarization electrode includes an electrically conductive base serving as the collector, and a polarization electrode that includes a multiplicity of separate polarization particles dispersed throughout the base and exposed in at least a part of a surface of the base.

Abstract: It is an object of the present invention to provide a semiconductor device capable of decreasing electric resistance of a lower electrode provided therein, as well as capable of accurately responding to external signals having high frequencies inputted therein. The lower electrode 7 consists of three layers such as a silicon lower electrode layer 7a made of poly-crystalline silicon, a tungsten-silicide layer 7b made of tungsten silicide as a chemical compound of tungsten and silicon, and a protection layer 7c made of poly-crystalline silicon. By constructing the semiconductor device as described above, oxidation of the tungsten-silicide layer 7b may be prevented by the protection layer 7c made of poly-crystalline silicon even when oxidation layers of an ONO (silicon oxidation) layer 11 is formed by thermal oxidation. Consequently, electric resistance of the lower electrode 7 can be decreased.

Abstract: An anode lead 17 extending from a capacitor body 18 of a capacitor element 14 is mounted on a connecting portion 21 of an anode terminal 12 and the anode lead 17 and the connecting portion 21 are welded together by laser light B. The welding operation is performed by laser light B in a state where the anode lead 17 is urged to the connecting portion 21 in a region between said anode lead and said connecting portion. Alternatively, the welding operation is performed by laser light B in a state where a reflection plate having a slot and functioning to reflect reflected laser light is arranged in a region between the connecting portion and the capacitor body while the anode lead is received in said slot.

Abstract: The invention provides systems and methods for interconnecting circuit devices, wherein decoupling capacitors are disposed on a substrate and an interconnect layer having a pattern of circuit connections is formed by a deposition process over the capacitors thereby embedding the decoupling capacitors within the interconnect layer. Circuit devices can be mounted to the surface of the deposited interconnect layer at locations that minimize, or substantially minimize, the interconnect length between the chip device and the decoupling capacitors for that circuit device.

Abstract: The structure of a high-Q inductor applied in a monolithic circuit according to the invention comprises a plurality of spiral metal lines and a plurality of dielectric layers, each dielectric layer formed between two adjacent spiral metal lines. Furthermore, via plugs are formed in each dielectric layer to electrically connect two adjacent spiral metal lines. A spiral air trench is formed along the spacing of the spiral metal lines in the dielectric layers. Therefore, the 3D-structure of the inductor of the invention can greatly reduce the series resistance thereof without widening the spiral metal lines. In addition, the spiral air trench, filled with air which has a lower dielectric constant, can efficiently reduce the parasitic capacitance between the spacing of the spiral metal lines. As a result, the inductor of the invention has a higher quality factor at a proper RF operating frequency region.

Abstract: A method for forming viable floating gate memory cells in a semiconductor substrate. At various points within the memory cell manufacturing process rapid thermal annealing is used to repair any damage that may be caused to the crystals in the substrate by various processing steps. By quickly repairing any damage to the crystals of the substrate, the rate and amount of overall transient enhanced diffusion of the various dopants within the substrate can be greatly reduced, thereby allowing the production of a viable memory cell. Specifically, the present invention uses rapid thermal annealing during and following the formation of the source and drain regions and the interconnection regions effecting electrical connection between the source regions. This desensitizes the erase rates of the semiconductor device to the etching conditions employed to form the connections.

Abstract: A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substrat

Abstract: Method for forming an inter-level dielectric layer upon a substrate employed within a microelectronics fabrication. There is first provided a substrate. There is then formed upon the substrate a patterned microelectronics layer. There is then formed upon and between the patterned microelectronics layer and substrate a blanket first silicon oxide layer employing high density plasma chemical vapor deposition. There is then an optional exposure of the first blanket silicon oxide layer to a nitrogen plasma treatment prior to formation thereupon of a second blanket silicon oxide dielectric layer employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition, where the nitrogen plasma exposure results in improved gap fill within the silicon oxide dielectric layer, whereas avoidance of exposure to the nitrogen plasma results in formation of voids within the blanket second silicon oxide dielectric layer, leading to lower capacitance.

Abstract: The dummy oxide used to form DRAM capacitor cells is left in place over the peripheral transistors, reducing the height difference between the DRAM array and the peripheral circuitry and protecting against edge effects.

Abstract: A semiconductor package in which a semiconductor chip 16 is formed above a die pad 12 interposing a capacitor 22 therebetween, or the semiconductor chip 16 and the capacitor 22 in a vortex-shaped form are respectively formed on both faces of the die pad 12, or the condensers 22 are formed on both faces of the die pad 12 and the semiconductor chip 16 is formed on one of the condensers 22, and the die pad 12, the semiconductor chip 16 and the condensers 22 are sealed by resin by which adverse effect of noise is reduced, wherein the shape of the capacitor may be in a vortex-shaped form or opposed faces of metal layers may be roughened.

Abstract: The present invention provides a method for enlarging the surface area of hemi-spherical grains on the surface of a semiconductor chip. The hemi-spherical grain structure is formed by combining a poly-silicon layer with an underlying amorphous silicon layer. In processing, the two layers are etched with a corrosive solution that etches the amorphous silicon layer at a higher rate than it etches the poly-silicon layer. In this way, a ring-shaped slot forms at the bottom of each hemi-spherical grain thus increasing the total surface area of the hemi-spherical grain structure. Furthermore, surface area of the storage node is increased and the cell capacitor capacitance increases in excess of 15%.

Abstract: A structure of metal contact portion of a semiconductor device, includes a semiconductor substrate having an impurity doped junction therein, an insulating layer pattern formed on the semiconductor substrate having a contact hole through the insulating layer pattern to expose the doped junction, a conductive projection formed directly on a portion of the doped junction, and a metal layer formed on opposite sides of the conductive projection and contacting the doped junction and the conductive projection, whereby a contact area for the doped junction is increased.

Abstract: An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects.

Abstract: Cathode and anode sides of a plurality of solid electrolytic capacitors are connected by simultaneous electric welding. The welding step is effected to connect an anode lead of a lead frame to the anode electrode of a capacitor body and simultaneously connect a cathode lead of the lead frame to the cathode conductor layer of an adjacent capacitor body. The welding electrode for the cathode lead exerts moderate force to the capacitor bodies using a spring function of the capacitor lead. The simultaneous welding for the adjacent capacitor bodies and the moderate force prevent electrical and mechanical damages of the insulator layer of the solid electrolytic capacitors during the welding.