Utilizing Gate Sidewall Structure Patents (Class 438/230)
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Patent number: 8513075Abstract: A manufacturing method for manufacturing a semiconductor device includes depositing a spacer material on a semiconductor substrate, the substrate includes an NMOS region and a PMOS region, each region has a gate formed thereon. The method further includes covering the NMOS region with a first mask, forming a spacer for the PMOS gate by etching the spacer material, forming a recess in the PMOS region by etching, and growing SiGe or SiGe with in-situ-doped B in the recess of the PMOS region to form a PMOS source/drain region. The method further includes performing an anisotropic wet etching on the recess. After growing SiGE or SiGe with in-situ-doped B, the method further includes covering the PMOS region with a second mask and forming a spacer for the NMOS gate by etching the spacer material. The spacer for the PMOS and NMOS gate has a different critical dimension.Type: GrantFiled: November 29, 2011Date of Patent: August 20, 2013Assignee: Semiconductor Manufacturing International CorporationInventors: Yonggen He, Jingang Wu, Haibiao Yao
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Patent number: 8507351Abstract: By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.Type: GrantFiled: June 3, 2011Date of Patent: August 13, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Anthony Mowry, Markus Lenski, Guido Koerner, Ralf Otterbach
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Patent number: 8501571Abstract: A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.Type: GrantFiled: March 14, 2012Date of Patent: August 6, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Naoyoshi Tamura
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Patent number: 8502325Abstract: A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer, selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.Type: GrantFiled: March 28, 2012Date of Patent: August 6, 2013Assignee: International Business Machines CorporationInventors: Leland Chang, Jeffrey W. Sleight, Isaac Lauer, Renee T. Mo
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Publication number: 20130187205Abstract: Disclosed is a semiconductor article which includes a semiconductor substrate; a gate structure having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain adjacent to the gate structure, the raised source/drain filling the faceted space and having a surface parallel to the semiconductor substrate. Also disclosed is a method of making the semiconductor article.Type: ApplicationFiled: January 23, 2012Publication date: July 25, 2013Applicant: Internationa Business Machines CorporationInventors: THOMAS N. ADAM, KANGGUO CHENG, ALI KHAKIFIROOZ, ALEXANDER REZNICEK
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Patent number: 8492236Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.Type: GrantFiled: January 12, 2012Date of Patent: July 23, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong, Huang Liu
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Patent number: 8492830Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate having a gate groove and first to third grooves, the first to third grooves being formed on a bottom surface of the gate groove and the third groove being formed between the first and second grooves, and a gate electrode having a first gate portion formed in the first groove, a second gate portion formed in the second groove, a third gate portion formed in the third groove, and a fourth gate portion formed in the gate groove. A cell transistor having the gate electrode has a first channel region formed in the semiconductor substrate between the first and third gate portions and a second channel region formed in the semiconductor substrate between the second and third gate portions.Type: GrantFiled: September 19, 2011Date of Patent: July 23, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Kajiyama
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Patent number: 8486778Abstract: A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.Type: GrantFiled: July 15, 2011Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Balasubramanian S. Haran, Hemanth Jagannathan, Sivananda K. Kanakasabapathy, Sanjay Mehta
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Publication number: 20130175632Abstract: A time clock clearly identifies where a user should position a time card therein. The clock and a printer platen are fixed relative to a base, and has the time card rests thereon. A printing mechanism moves relative to the base and has a target area, it is traversable between a print position and an idle position, and it impresses the time indicia onto the time card while in the print position. A ribbon shield is fixed relative to the base. A focused illuminated guide is fixed relative to the base, and in combination with the ribbon shield, guides the time card with respect to the printing mechanism to clearly identify where the user should position the time card in the time clock.Type: ApplicationFiled: January 6, 2012Publication date: July 11, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ming CAI, Dechao GUO, Ahmet S. OZCAN, Liyang SONG, Chun-chen YEH
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Patent number: 8470662Abstract: The present invention relates to a semiconductor device and a manufacturing method for making the same, wherein, according to the method, after the gate stack is formed, a buffer layer is formed on sidewalls of an PMOS gate stack, the buffer layer being formed of a porous low-k dielectric layer; and then, sidewall spacers and source/drain/halo regions, and source and drain regions are formed for the device; and finally, a high-temperature anneal is conducted in an oxygen environment such that the oxygen in the oxygen environment diffuse through the buffer layer into the high-k dielectric layer of the second gate stack. The present invention lowers threshold voltage of the PMOS device without affecting the threshold voltage of the NMOS device, avoids damages to the gate and substrate incurred by removing the PMOS sidewall spacer in a traditional process, and hereby effectively improves the overall performance of the device.Type: GrantFiled: June 28, 2010Date of Patent: June 25, 2013Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Zhijiong Luo, Huilong Zhu, Haizhou Yin
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Patent number: 8470664Abstract: A dual polysilicon gate is fabricated by, inter alia, forming a polysilicon layer doped with impurities of a first conductivity type on a substrate having a first region and a second region, forming a mask pattern that covers the polysilicon layer in the first region and leaves the polysilicon layer in the second region, injecting impurities of a second conductivity type into the polysilicon layer in the second region left exposed by the mask pattern. Removing the mask pattern, and patterning the polysilicon layer to form a first polysilicon pattern in the first region and a second polysilicon pattern in the second region. The second polysilicon pattern is formed to have protrusions that laterally protrude from sidewalls thereof. Subsequently, impurities of the second conductivity type are injected into the substrate in the second region and into the protrusions of the second polysilicon pattern.Type: GrantFiled: February 3, 2012Date of Patent: June 25, 2013Assignee: SK Hynix Inc.Inventors: Kyong Bong Rouh, Yong Seok Eun
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Patent number: 8470661Abstract: During a replacement gate approach, the inverse tapering of the opening obtained after removal of the polysilicon material may be reduced by depositing a spacer layer and forming corresponding spacer elements on inner sidewalls of the opening. Consequently, the metal-containing gate electrode material and the high-k dielectric material may be deposited with enhanced reliability.Type: GrantFiled: November 24, 2009Date of Patent: June 25, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Kai Frohberg, Uwe Griebenow, Katrin Reiche, Heike Berthold
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Patent number: 8466520Abstract: In a transistor, a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may be positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain-inducing semiconductor alloy. For this purpose, two or more “disposable” spacer elements of different etch behavior may be used in order to define different lateral offsets at different depths of the corresponding cavities. Consequently, enhanced uniformity and, thus, reduced transistor variability may be accomplished, even for sophisticated semiconductor devices.Type: GrantFiled: May 14, 2012Date of Patent: June 18, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Stephan Kronholz, Vassilios Papageorgiou, Gunda Beernink
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Patent number: 8450169Abstract: The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.Type: GrantFiled: November 29, 2010Date of Patent: May 28, 2013Assignee: International Business Machines CorporationInventors: Unoh Kwon, Ramachandra Divakaruni, Siddarth A. Krishnan, Ravikumar Ramachandran
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Publication number: 20130130449Abstract: Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region.Type: ApplicationFiled: December 18, 2012Publication date: May 23, 2013Applicant: GLOBALFOUNDRIES Inc.Inventor: GLOBAL FOUNDRIES Inc.
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Patent number: 8445345Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes forming a first transistor device and a second transistor device on a semiconductor substrate. The first transistor device and second transistor device initially have sacrificial dummy gate structures. The sacrificial dummy gate structures are removed and a set of vertical oxide spacers are selectively formed for the first transistor device. The set of vertical oxide spacers are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device.Type: GrantFiled: September 8, 2011Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni
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Publication number: 20130119473Abstract: A metal gate structure with a channel material and methods of manufacture such structure is provided. The method includes forming dummy gate structures on a substrate. The method further includes forming sidewall structures on sidewalls of the dummy gate structures. The method further includes removing the dummy gate structures to form a first trench and a second trench, defined by the sidewall structures. The method further includes forming a channel material on the substrate in the first trench and in the second trench. The method further includes removing the channel material from the second trench while the first trench is masked. The method further includes filling remaining portions of the first trench and the second trench with gate material.Type: ApplicationFiled: November 10, 2011Publication date: May 16, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Unoh Kwon, Ramachandran Muralidhar, Viorel Ontalus
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Patent number: 8441070Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.Type: GrantFiled: August 6, 2012Date of Patent: May 14, 2013Assignee: Renesas Electronics CorporationInventor: Hiroki Fujii
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Patent number: 8426266Abstract: In sophisticated semiconductor devices, stress memorization techniques may be applied on the basis of a silicon nitride material, which may be subsequently modified into a low-k dielectric material in order to obtain low-k spacer elements, thereby enhancing performance of sophisticated semiconductor devices. The modification of the initial silicon nitride-based spacer material may be accomplished on the basis of an oxygen implantation process.Type: GrantFiled: December 9, 2010Date of Patent: April 23, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Jan Hoentschel, Andreas Kurz, Uwe Griebenow, Thilo Scheiper
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Patent number: 8420470Abstract: The disclosed method of fabricating a semiconductor device structure forms a dummy gate structure on a substrate, deposits a dielectric material overlying the dummy gate structure in a manner that forms angled sidewalls of the deposited dielectric material outboard the spacers, and conformally deposits a compressive material overlying the deposited dielectric material such that the deposited compressive material forms angled peaks overlying the dummy gate structure. The method continues by forming an upper dielectric layer overlying the deposited compressive material, planarizing the resulting device structure, and exposing the temporary gate element of the dummy gate structure. Thereafter, the temporary gate element is removed, while leaving sections of the deposited compressive material outboard the spacers, and the gate recess is filled with a gate electrode material. The compressive material pulls the upper ends of the spacers apart to facilitate filling the gate recess.Type: GrantFiled: August 26, 2010Date of Patent: April 16, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventor: Kisik Choi
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Patent number: 8415213Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).Type: GrantFiled: July 19, 2011Date of Patent: April 9, 2013Assignee: Renesas Electronics CorporationInventors: Kazunobu Ota, Hirokazu Sayama, Hidekazu Oda
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Patent number: 8410568Abstract: A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.Type: GrantFiled: August 25, 2009Date of Patent: April 2, 2013Assignee: Tau-Metrix, Inc.Inventors: Gary Steinbrueck, James S. Vickers, Mario M. Pelella, Majid Aghababazadeh, Nader Pakdaman
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Patent number: 8409975Abstract: A method for decreasing polysilicon gate resistance in a carbon co-implantation process which includes: depositing a first salicide block layer on a formed gate of a MOS device and etching it to form a first spacer of a side surface of the gate of the MOS device; performing a P-type heavily doped boron implantation process and a thermal annealing treatment, so as to decrease the resistance of the polysilicon gate; removing said first spacer, performing a lightly doped drain process, and performing a carbon co-implantation process at the same time, so as to form ultra-shallow junctions at the interfaces between a substrate and source region and drain region below the gate; re-depositing a second salicide block layer on the gate and etching the mask to form a second spacer; forming a self-aligned silicide on the surface of the MOS device. The invention can decrease the resistance of the P-type polysilicon gate.Type: GrantFiled: December 29, 2011Date of Patent: April 2, 2013Assignee: Shanghai Huali Microelectronics CorporationInventor: Liujiang Yu
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Patent number: 8389392Abstract: The present invention relates to a FinFET with separate gates and to a method for fabricating the same. A dielectric gate-separation layer between first and second gate electrodes has an extension in a direction pointing from a first to a second gate layer that is smaller than a lateral extension of the fin between its opposite lateral faces. This structure corresponds with a processing method that starts from a covered basic FinFET structure with a continuous first gate layer, and proceeds to remove parts of the first gate layer and of a first gate-isolation layer through a contact opening to the gate layer. Subsequently, a replacement gate-isolation layer that at the same time forms the gate separation layer fabricated, followed by filling the tunnel with a replacement gate layer and a metal filling.Type: GrantFiled: February 9, 2009Date of Patent: March 5, 2013Assignee: NXP B.V.Inventors: Jan Sonsky, Radu Surdeanu
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Patent number: 8383500Abstract: In a replacement gate approach, one work function metal may be provided in an early manufacturing stage, i.e., upon depositing the gate layer stack, thereby reducing the number of deposition steps required in a later manufacturing stage. Consequently, the further work function metal and the electrode metal may be filled into the gate trenches on the basis of superior process conditions compared to conventional replacement gate approaches.Type: GrantFiled: October 28, 2010Date of Patent: February 26, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Gerd Marxsen, Joachim Metzger, Robert Binder, Markus Lenski
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Publication number: 20130032887Abstract: A manufacturing method for manufacturing a semiconductor device includes depositing a spacer material on a semiconductor substrate, the substrate includes an NMOS region and a PMOS region, each region has a gate formed thereon. The method further includes covering the NMOS region with a first mask, forming a spacer for the PMOS gate by etching the spacer material, forming a recess in the PMOS region by etching, and growing SiGe or SiGe with in-situ-doped B in the recess of the PMOS region to form a PMOS source/drain region. The method further includes performing an anisotropic wet etching on the recess. After growing SiGE or SiGe with in-situ-doped B, the method further includes covering the PMOS region with a second mask and forming a spacer for the NMOS gate by etching the spacer material. The spacer for the PMOS and NMOS gate has a different critical dimension.Type: ApplicationFiled: November 29, 2011Publication date: February 7, 2013Applicant: Semiconductor Manufacturing International (Beijing) CorporationInventors: Yonggen HE, Jingang WU, HaiBiao YAO
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Patent number: 8361869Abstract: The present application discloses a method for manufacturing a gate-all-around field effect transistor, comprising the steps of: forming a suspended fin in a semiconductor substrate; forming a gate stack around the fin; and forming source/drain regions in the fin on both sides of the gate stack, wherein an isolation dielectric layer is formed in a portion of the semiconductor substrate which is adjacent to bottom of both the fin and the gate stack. The present invention relates to a method for manufacturing a gate-all-around device on a bulk silicon substrate, which suppress a self-heating effect and a floating-body effect of the SOI substrate, and lower a manufacture cost. The inventive method is a conventional top-down process with respect to a reference plane, which can be implemented as a simple manufacture process, and is easy to be integrated into and compatible with a planar CMOS process. The inventive method suppresses a short channel effect and promotes miniaturization of MOSFETs.Type: GrantFiled: February 17, 2011Date of Patent: January 29, 2013Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huajie Zhou, Yi Song, Qiuxia Xu
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Patent number: 8357576Abstract: A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target.Type: GrantFiled: January 14, 2011Date of Patent: January 22, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Chong-Kwang Chang, Sung-Hon Chi, Hong-Jae Shin, Yong-Jin Chung, Young-Mook Oh, Ju-Beom Yi
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Patent number: 8357573Abstract: Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region.Type: GrantFiled: May 3, 2010Date of Patent: January 22, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventors: Stephan Kronholz, Markus Lenski, Vassilios Papageorgiou
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Publication number: 20130015527Abstract: The present disclosure is directed to various methods of forming metal silicide regions on an integrated circuit device. In one example, the method includes forming a PMOS transistor and an NMOS transistor, each of the transistors having a gate electrode and at least one source/drain region formed in a semiconducting substrate, forming a first sidewall spacer adjacent the gate electrodes and forming a second sidewall spacer adjacent the first sidewall spacer.Type: ApplicationFiled: July 12, 2011Publication date: January 17, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Hans-Juergen Thees, Peter Baars
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Patent number: 8338831Abstract: Recesses are formed in a pMOS region 2, and a SiGe layer is then formed so as to cover a bottom surface and a side surface of each of the recesses. Next, a SiGe layer containing Ge at a lower content than that in the SiGe layer is formed on each of the SiGe layers.Type: GrantFiled: June 29, 2010Date of Patent: December 25, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Naoyoshi Tamura, Yosuke Shimamune, Hirotaka Maekawa
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Publication number: 20120315734Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming an offset spacer on the sidewall of the gate structure; forming a cap layer to cover the substrate and the gate structure; performing an ion implantation process to implant carbon atoms into the cap layer; performing a first etching process to form a recess in the substrate adjacent to two sides of the gate structure; and forming an epitaxial layer in the recess.Type: ApplicationFiled: June 9, 2011Publication date: December 13, 2012Inventors: Chan-Lon Yang, Ger-Pin Lin, Tsuo-Wen Lu
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Patent number: 8329526Abstract: Dielectric cap layers of sophisticated high-k metal gate electrode structures may be efficiently removed on the basis of a sacrificial fill material, thereby reliably preserving integrity of a protective sidewall spacer structure, which in turn may result in superior uniformity of the threshold voltage of the transistors. The sacrificial fill material may be provided in the form of an organic material that may be reduced in thickness on the basis of a wet developing process, thereby enabling a high degree of process controllability.Type: GrantFiled: October 15, 2010Date of Patent: December 11, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Jens Heinrich, Frank Seliger, Ralf Richter, Markus Lenski
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Patent number: 8324689Abstract: Provided is a self aligned field effect transistor structure. The self aligned field effect transistor structure includes: an active region pattern on a substrate; a first gate electrode and a second gate electrode facing each other with the active region pattern therebetween; and a source electrode and a drain electrode connected to the active region pattern and disposed to be symmetric with respect to a line connecting the first and second gate electrodes, wherein the first and second gate electrodes and the source and drain electrodes are disposed on the same plane of the substrate.Type: GrantFiled: December 10, 2009Date of Patent: December 4, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Lee-Mi Do, Kyu-Ha Baek
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Patent number: 8318570Abstract: A device and method for improving performance of a transistor includes gate structures formed on a substrate having a spacing therebetween. The gate structures are formed in an operative relationship with active areas fainted in the substrate. A stress liner is formed on the gate structures. An angled ion implantation is applied to the stress liner such that ions are directed at vertical surfaces of the stress liner wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect provided by a height and spacing between adjacent structures.Type: GrantFiled: December 1, 2009Date of Patent: November 27, 2012Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Ying Zhang
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Patent number: 8309411Abstract: A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; forming a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.Type: GrantFiled: March 23, 2011Date of Patent: November 13, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hoonjoo Na, Sangjin Hyun, Yugyun Shin, Hongbae Park, Sughun Hong, Hye-Lan Lee, Hyung-Seok Hong
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Publication number: 20120280250Abstract: A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described.Type: ApplicationFiled: May 4, 2011Publication date: November 8, 2012Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan S. Basker, Kangguo Cheng, Bruce B. Doris, Johnathan E. Faltermeier, Sivananda K. Kanakasabapathy, Hemant Adhikari
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Patent number: 8288219Abstract: A stack of two polysilicon layers is formed over a semiconductor body region. A DDD implant is performed to form a DDD source region in the semiconductor body region along a source side of the polysilicon stack but not along a drain side of the polysilicon stack. Off-set spacers are formed along opposing side-walls of the polysilicon stack. A source/drain implant is performed to form a drain region in the semiconductor body region along the drain side of the polysilicon stack and to form a highly doped region within the DDD source region such that the extent of an overlap between the polysilicon stack and each of the drain region and the highly doped region is inversely dependent on a thickness of the off-set spacers, and a lateral spacing directly under the polysilicon stack between adjacent edges of the DDD source region and the highly doped region is directly dependent on the thickness of the off-set spacers.Type: GrantFiled: March 20, 2008Date of Patent: October 16, 2012Assignee: Hynix Semiconductor, Inc.Inventors: Peter Rabkin, Hsingya Arthur Wang, Kai-Cheng Chou
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Patent number: 8278686Abstract: A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode laterally extending over but being insulated from the silicon-germanium layer, a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region, and source region of the first conductivity type extending in the silicon-germanium layer. The gate electrode laterally overlaps both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.Type: GrantFiled: May 9, 2011Date of Patent: October 2, 2012Assignee: Fairchild Semiconductor CorporationInventors: James Pan, Qi Wang
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Patent number: 8264037Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.Type: GrantFiled: January 20, 2012Date of Patent: September 11, 2012Assignee: Renesas Electronics CorporationInventor: Hiroki Fujii
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Publication number: 20120211838Abstract: When forming sophisticated semiconductor devices including complementary transistors having a reduced gate length, the individual transistor characteristics may be adjusted on the basis of individually provided semiconductor alloys, such as a silicon/germanium alloy for P-channel transistors and a silicon/phosphorous semiconductor alloy for N-channel transistors. To this end, a superior hard mask patterning regime may be applied in order to provide compatibility with sophisticated replacement gate approaches, while avoiding undue process non-uniformities, in particular with respect to the removal of a dielectric cap layer.Type: ApplicationFiled: February 10, 2012Publication date: August 23, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Stephan Kronholz, Gunda Beernink, Markus Lenski
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Patent number: 8247279Abstract: A semiconductor device according to one embodiment includes: a first transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first channel region formed in the substrate under the first film, and first epitaxial crystal layers formed on both sides of the first channel region in the substrate, the first layers comprising a first crystal; and a second transistor comprising a second gate electrode formed on the substrate via a second gate insulating film, a second channel region formed in the substrate under the second film, second epitaxial crystal layers formed on both sides of the second channel region in the substrate, and third epitaxial crystal layers formed on the second layers, the second layers comprising a second crystal, the third layers comprising the first crystal, the second transistor having a conductivity type different from that of the first transistor.Type: GrantFiled: September 14, 2009Date of Patent: August 21, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Shintaro Okamoto
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Patent number: 8247286Abstract: One embodiment of inventive concepts exemplarily described herein may be generally characterized as a semiconductor device including an isolation region within a substrate. The isolation region may define an active region. The active region may include an edge portion that is adjacent to an interface of the isolation region and the active region and a center region that is surrounded by the edge portion. The semiconductor device may further include a gate electrode on the active region and the isolation region. The gate electrode may include a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, and a first impurity region of a first conductivity type within the center gate portion and outside the edge portion. The semiconductor device may further include a gate insulating layer disposed between the active region and the gate electrode.Type: GrantFiled: February 25, 2010Date of Patent: August 21, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Dong-Ryul Chang
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Publication number: 20120199813Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.Type: ApplicationFiled: April 18, 2012Publication date: August 9, 2012Applicant: Intel CorporationInventors: Suman Datta, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Majumdar Amian, Justin K. Brask, Been-Yih Jin, Matthew V. Metz, Robert S. Chau
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Publication number: 20120181617Abstract: The present invention relates to a semiconductor device and a manufacturing method for making the same, wherein, according to the method, after the gate stack is formed, a buffer layer is formed on sidewalls of an PMOS gate stack, the buffer layer being formed of a porous low-k dielectric layer; and then, sidewall spacers and source/drain/halo regions, and source and drain regions are formed for the device; and finally, a high-temperature anneal is conducted in an oxygen environment such that the oxygen in the oxygen environment diffuse through the buffer layer into the high-k dielectric layer of the second gate stack. The present invention lowers threshold voltage of the PMOS device without affecting the threshold voltage of the NMOS device, avoids damages to the gate and substrate incurred by removing the PMOS sidewall spacer in a traditional process, and hereby effectively improves the overall performance of the device.Type: ApplicationFiled: June 28, 2010Publication date: July 19, 2012Inventors: Zhijiong Luo, Huilong Zhu, Haizhuo Yin
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Patent number: 8216907Abstract: A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer; selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.Type: GrantFiled: September 13, 2010Date of Patent: July 10, 2012Assignee: International Business Machines CorporationInventors: Leland Chang, Jeffrey W. Sleight, Isaac Lauer, Renee T. Mo
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Publication number: 20120164803Abstract: A CMOS semiconductor integrated circuit device includes an NMOS device comprising a gate region, a source region, and a drain region and an NMOS channel region formed between the source region and drain region. A silicon carbide material is formed within the source region and formed within the drain region. The silicon carbide material causes the channel region to be in a tensile mode. The CMOS device also has a PMOS device comprising a gate region, a source region, and a drain region. The PMOS device has a PMOS channel region formed between the source region and the drain region. A silicon germanium material is formed within the source region and formed with in the drain region. The silicon germanium material causes the channel region to be in a compressive mode.Type: ApplicationFiled: March 6, 2012Publication date: June 28, 2012Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: JOHN CHEN, Simon Yang
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Patent number: 8207030Abstract: A method for producing one or more nMOSFET devices and one or more pMOSFET devices on the same semiconductor substrate is disclosed. In one aspect, the method relates to the use of a single activation anneal that serves for both Si nMOS and Ge pMOS. By use of a solid phase epitaxial regrowth (SPER) process for the Si nMOS, the thermal budget for the Si nMOS can be lowered to be compatible with Ge pMOS.Type: GrantFiled: April 28, 2009Date of Patent: June 26, 2012Assignee: IMECInventors: David Paul Brunco, Brice De Jaeger, Simone Severi
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Publication number: 20120153399Abstract: The drain and source regions may at least be partially formed by in situ doped epitaxially grown semiconductor materials for complementary transistors in sophisticated semiconductor devices designed for low power and high performance applications. To this end, cavities may be refilled with in situ doped semiconductor material, which in some illustrative embodiments also provides a desired strain in the channel regions of the complementary transistors.Type: ApplicationFiled: July 28, 2011Publication date: June 21, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Jan Hoentschel, Stefan Flachowsky, Steven Langdon, Thilo Scheiper
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Patent number: 8202777Abstract: In a transistor, a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may be positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain-inducing semiconductor alloy. For this purpose, two or more “disposable” spacer elements of different etch behavior may be used in order to define different lateral offsets at different depths of the corresponding cavities. Consequently, enhanced uniformity and, thus, reduced transistor variability may be accomplished, even for sophisticated semiconductor devices.Type: GrantFiled: December 17, 2009Date of Patent: June 19, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Stephan Kronholz, Vassilios Papageorgiou, Gunda Beernink