Abstract: According to one disclosed embodiment, a transistor gate is fabricated on a substrate. For example, the gate can be a polycrystalline silicon gate in a FET. Thereafter, a conformal layer is deposited over the substrate and the gate and is then etched back to form spacers on the sides of the gate. An underlying dielectric layer is formed on the substrate, gate, and spacers. The conformal layer and the underlying dielectric layer can be comprised of, for example, a dielectric such as silicon dioxide, silicon nitride, or a low-k dielectric. Next, an overcoat layer is fabricated on the underlying dielectric layer. The overcoat layer can be, for example, polycrystalline silicon. Following, an opening is etched in the overcoat layer and the underlying dielectric layer wherein subsequent films can be grown. For example, silicon germanium can be grown in the opening for fabrication of a silicon germanium heterojunction bipolar transistor.

Abstract: A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate is provided by implanting oxygen into a Si/SiGe multilayer heterostructure which comprises alternating Si and SiGe layers. Specifically, the high quality, relaxed SiGe-on-insulator is formed by implanting oxygen ions into a multilayer heterostructure which includes alternating layers of Si and SiGe. Following, the implanting step, the multilayer heterostructure containing implanted oxygen ions is annealed, i.e., heated, so as to form a buried oxide region predominately within one of the Si layers of the multilayer structure.

Abstract: A semiconductor structure and a method of forming same is disclosed. The method includes forming, on a substrate, an n-doped collector structure of InAs/AlSb materials; forming a base structure on said collector structure which base structure comprises p-doped GaSb; and forming, on said base structure, an n-doped emitter structure of InAs/AlSb materials. The collector and emitter structure are preferably superlattices each comprising a plurality of periods of InAs and AlSb sublayers. A heterojunction bipolar transistor manufactured using the method is disclosed.

Abstract: A SiGe bipolar transistor including a semiconductor substrate having a collector and sub-collector region formed therein, wherein the collector and sub-collector are formed between isolation regions that are also present in the substrate is provided. Each isolation region includes a recessed surface and a non-recessed surface which are formed utilizing lithography and etching. A SiGe layer is formed on the substrate as well as the recessed non-recessed surfaces of each isolation region, the SiGe layer includes polycrystalline Si regions and a SiGe base region. A patterned insulator layer is formed on the SiGe base region; and an emitter is formed on the patterned insulator layer and in contact with the SiGe base region through an emitter window opening.

Abstract: A transistor includes a base, a collector, and an emitter comprising a group III/VI semiconductor. Microcircuits having at least one metal oxide semiconductor (MOS) transistor and the previously described transistor are provided. Processes for manufacturing a transistor and a BiMOS microcircuit are also provided.

Abstract: A method for making a heterojunction bipolar transistor on an insulated semiconductor substrate. A highly doped subcollector is formed on an insulated substrate. A lightly doped collector is formed adjacent to and in direct contact with the subcollector. An extrinsic base film stack is deposited on the lightly doped collector. A collector base S and base emitter junction window are etched in the extrinsic base film stack. A doped semiconductor intrinsic base is formed in the junction window. A self aligning base emitter spacer is formed and etched in the junction window and the emitter material is deposited and etched in the junction window. Oxide spacers are deposited and etched adjacent walls of the emitter material. The extrinsic base is defined and conductors are deposited on the device to provide a heterojunction bipolar transistor having improved resistance and capacitance characteristics.

Abstract: A method of simultaneously forming differential gate oxide for both high and low voltage transistors using a two-step wet oxidation process is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas and wherein there is at least one low voltage area in which a low voltage transistor will be formed and at least one high voltage area in which a high voltage transistor will be formed. The surface of the semiconductor substrate is wet oxidized to form a first layer of gate oxide on the surface of the semiconductor substrate in the active areas. The low voltage active area is covered with a mask. The surface of the semiconductor substrate is wet oxidized again where it is not covered by the mask to form a second layer of gate oxide under the first gate oxide layer in the high voltage active area. The mask is removed.

Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

Abstract: A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has an emitter region characterized by a y-shaped structure formed from bilayer polysilicon. The bilayer polysilicon includes a first polysilicon emitter structure and a second polysilicon emitter structure. The method of forming the bipolar transistor includes forming an emitter stack on a substrate. The emitter stack comprises the first polysilicon emitter structure and a plug structure. The emitter stack defines the substrate into a masked portion and exposed adjacent portions. The exposed adjacent portions are selectively doped with a dopant to define an extrinsic base region, wherein the dopant is blocked from entering the masked portion. After selectively doping the extrinsic base region, the plug structure is removed from the emitter stack and the second polysilicon emitter structure is formed on the first polysilicon emitter structure to define the emitter region of the bipolar transistor.

Abstract: The invention relates to the protection of devices in a monolithic chip fabricated from an epitaxial wafer, such as a wafer for a Group III-V compound semiconductor or a wafer for a Group IV compound semiconductor. Devices fabricated from Group III-V compound semiconductors offer higher speed and better isolation than comparable devices from silicon semiconductors. Semiconductor devices can be permanently damaged when exposed to an undesired voltage transient such as electrostatic discharge (ESD). However, conventional techniques developed for silicon devices are not compatible with processing techniques for Group III-V compound semiconductors, such as gallium arsenide (GaAs). Embodiments of the invention advantageously include transient voltage protection circuits that are relatively efficiently and reliably manufactured to protect sensitive devices from undesired voltage transients.

Abstract: A transistor includes a base, a collector, and an emitter comprising a group III/VI semiconductor. Microcircuits having at least one metal oxide semiconductor (MOS) transistor and the previously described transistor are provided. Processes for manufacturing a transistor and a BiMOS microcircuit are also provided.

Abstract: A hetero-bipolar transistor according to the present invention enhances reliability that relates to the breaking of wiring metal. The transistor comprises a semiconductor substrate, a sub-collector layer formed on a (100) surface of the substrate, a collector mesa formed on the sub-collector layer, and an emitter contact layer. The transistor further includes a collector electrode and wiring metal connected to the collector electrode. The edge of the sub-collector layer forms a step S, the angle of which is in obtuse relative to the substrate. Therefore, the wiring metal traversing the step S bends in obtuse angle at the step S, thus reducing the breaking of the wiring metal.

Abstract: A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.

Abstract: A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.

Abstract: The present invention realizes a heterobipolar transistor using a SiGeC base layer in order to improve its electric characteristics. Specifically, the distribution of carbon and boron within the base layer is controlled so that the concentration of boron is higher than the concentration of carbon on the side bordering on the emitter layer, and upon the formation of the emitter layer, both boron and carbon are dispersed into a portion of the emitter layer that comes into contact with the base layer.

Abstract: A process fabricates a vertical structure high carrier mobility transistor on a substrate of crystalline silicon doped with impurities of the N type, the transistor having a collector region located at a lower portion of the substrate.

Abstract: The invention relates to a method for producing bipolar transistors with the aid of selective epitaxy for producing a collector and base. The inventive method is advantageous in that the area of the base is widened by the isotropic etching of the conductive layer or by the oxidation of the conductive layer and by the subsequent removal of the oxide layer. This widening of the area of the base prevents the occurrence of short-circuits between the emitter and the collector during the subsequent production of the base.

Abstract: A heterojunction bipolar transistor has a stack comprised of a base layer, an emitter layer and a ballast layer made of AlGaAs. The emitter layer is comprised of a single layer or a multiplicity of layers, and at least one of which is comprised of a material that prevents hole injection from the base layer into the ballast layer. Thus, the hole injection from the base layer into the emitter layer is prevented. Accordingly, it is able to prevent the conductivity modulation of the ballast layer that is the cause of a deterioration in temperature characteristics.

Abstract: In a GaAs type semiconductor device, InpGa1−pN (0<p≦1) is used to thereby form heterojunction having a large difference in energy gap, thereby providing a high performance semiconductor device.

Abstract: In a gas-phase treating process of a semiconductor wafer using hydrogen, there is provided a technique for safely eliminating the hydrogen in an exhaust gas discharged from a gas-phase treating apparatus. The profile at the end portions of the side walls of gate electrodes of a poly-metal structure is improved by forming the gate electrodes over a semiconductor wafer IA having a gate oxide film and then by supplying the semiconductor wafer 1A with a hydrogen gas containing a low concentration of water, as generated from hydrogen and oxygen by catalytic action, to oxidize the principal face of the semiconductor wafer 1A selectively. After this, the hydrogen in the exhaust gas, as discharged from an oxidizing furnace, is completely converted into water by causing it to react with oxygen by a catalytic method.

Abstract: An emitter of a heterojunction bipolar transistor has a double-layer protrusion formed of a first emitter layer and a second emitter layer and protruded outside an external base region. The protrusion of 50 nm in total thickness is enough to prevent damage during formation of the protrusion by etching or during later fabricating processes. Penetration of moisture through damaged places is eliminated. A base ohmic electrode is continuously formed on the first and second emitter layers on the external base region up to the protrusion. Thus, the protrusion is reinforced so as to be further hard to damage. By ensuring a large area for the base ohmic electrode, an alignment margin can be taken during formation of a base lead electrode.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor is fabricated by forming a metastable epitaxial silicon-germaniuim base on a collector. The metastable epitaxial silicon-gernaniuim base, for example, may have a concentration of germanium greater than 20.0 atomic percent of germanium. The heterojunction bipolar transistor, for example, may be an NPN silicon-germanium heterojunction bipolar transistor. According to this exemplary embodiment, the heterojunction bipolar transistor is further fabricated by fabricating an emitter over the metastable epitaxial silicongermanium base. The heterojunction bipolar transistor is further fabricated by doping the emitter with a first dopant. The first dopant, for example, may be arsenic.

Abstract: A method of fabricating a bipolar transistor structure is provided in which a blanket silicon-germanium (SiGe) film is used in a self-aligned manner to form the active base region of the bipolar device, thereby eliminating the need for a complicated selective SiGe process.

Abstract: A method of manufacturing a semiconductor device comprising the step of epitaxially growing of an n-type doped layer of a semiconductor material using an n-type dopant gas, the growth process being performed at a pressure higher than 2.66×104 Pa.

Abstract: A silicon oxide layer is formed on a semiconductor wafer by performing a high temperature oxidation (HTO) process using dichlorosilane (SiH2Cl2) and nitrous oxide (N2O), as reacting gases, having a flow rates with a ratio greater than 2:1, respectively. The reacting moles of dichlorosilane to nitrous oxide are in the proportion of 1:2.

Abstract: A compound collector double heterojunction bipolar transistor (CCHBT) incorporates a collector comprising two layers: a wide bandgap collector region (e.g., GaAs), and a narrow bandgap collector region (e.g., InGaP). The higher electric field is supported in the wide bandgap region, thereby increasing breakdown voltage and reducing offset voltage. At the same time, the use of wide bandgap material in the depleted portion of the collector, and a higher mobility material toward the end and outside of the depletion region, reduces series resistance as well as knee voltage.

Abstract: In the present invention, a semiconductor device is formed which includes an MIM capacitor located on the upper surface of a heterostructure from which the emitter, base and collector sections of a nearby HBT are defined. In this way the capacitor and HBT share a substantially common structure, with the base and emitter electrodes of the HBT fashioned from the same metal layers as the upper and lower capacitor plates, respectively. Furthermore, as the insulator region of the capacitor is formed prior to definition of the HBT structure, the dielectric material used can be deposited by means of a plasma enhanced process, without damaging the HBT structure.

Abstract: A III-N compound semiconductor bipolar transistor structure and method of manufacture. An epitaxial layer structure is formed over a substrate. The epitaxial layer structure includes a nucleation layer, a buffer layer, an emitter layer containing first type dopants (conductive type) and a base layer containing second type dopants (conductive type). Ion implantation is conducted to form a first conductive region within the base layer for forming a collector terminal. A portion of the emitter layer is etched for forming an emitter terminal. In addition, two ion-implantation regions may form inside the base layer. The ion-implantation regions serve separately as the collector terminal and the emitter terminal of the bipolar transistor, respectively, so that a more planar transistor structure is formed.

Abstract: The invention relates to a silicon germanium hetero bipolar transistor and a method of fabricating the epitaxial individual layers of a silicon germanium hetero bipolar transistor.

Abstract: Disclosed is a manufacturing method to fabricate Heterojunction Bipolar Transistors (HBTs) that enables self-alignment of emitter and base metal contact layers with precise sub-micron spacing using a dielectric-assisted metal lift-off process. Such an HBT process relies on the formation of an “H-shaped” dielectric (i.e., Si3N4/SiO2) mask conformally deposited on top of the emitter contact metalization that is used to remove excess base metal through lift-off by a wet chemical HF-based etch. This HBT process also uses a thin selective etch-stop layer buried within the emitter layer to prevent wet chemical over-etching to the base and improves HBT reliability by forming a non-conducting, depleted ledge above the extrinsic base layer. The geometry of the self-aligned emitter and base metal contacts in the HBT insures conformal coverage of dielectric encapsulation films, preferably Si3N4 and/or SiO2, for reliable HBT emitter p-n junction passivation.

Abstract: An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor deposition. Nitrogen implantation is expected to minimize oxide growth variation.

Abstract: In one disclosed embodiment, a silicon-germanium base is formed, which includes an extrinsic base region, a link base region, and an intrinsic base region. An etch stop layer, which can be silicon oxide, is deposited over the silicon-germanium base. A polycrystalline silicon layer is then formed on the etch stop layer above the silicon-germanium base. The polycrystalline silicon layer is patterned to form a temporary emitter. The link base regions can be implant doped after fabricating the temporary emitter, for example, to reduce the resistance of the link base regions. Link spacers are then fabricated on the sides of the temporary emitter. The link spacers can be formed by depositing a conformal layer of silicon oxide over the temporary emitter and then etching back the conformal layer. The length of the link base regions, which are below the spacers, can be determined by the deposition thickness of the conformal layer. The extrinsic base regions are implant doped after fabricating the link spacers.

Abstract: According to a disclosed embodiment, a transistor region comprising a collector region is opened adjacent to an oxide region. The oxide region may be, for example, a field oxide region. Additionally, an extrinsic collector region is formed under the oxide region. A blanket layer of dielectric is deposited over the transistor region and the oxide region. The blanket layer of dielectric can comprise, for example, silicon dioxide. The blanket layer of dielectric is etched away from the transistor region, leaving behind a dielectric segment on the oxide region. Following, a base region comprising, for example, single-crystal silicon-germanium, is grown over the collector region. Concurrently, a conductive region that is electrically connected to the base region is formed over the oxide region. The dielectric segment on the oxide region increases the separation between the conductive region and the extrinsic collector region, thus lowering the base to collector capacitance.

Abstract: A Heterojunction Bipolar Transistor (HBT) is provided where the SiGe base region is formed through selective deposition, after the formation of the base electrode layer and the emitter window. A sacrificial oxide layer is deposited between the collector and base electrode. The contact to the SiGe base is made at an extrinsic area, underneath the base electrode, after removal of the sacrificial oxide. The SiGe is covered with a temporary oxide layer during further processes, and this protective layer is removed immediately before the deposition of the emitter material. The selective deposition of the SiGe at a relatively late stage of the fabrication process helps insure that the film remains free of the stresses which can degrade electron mobility. A process of fabricating the above-described HBT device is also provided.

Abstract: A semiconductor component (100) includes a semiconductor substrate (16) that is formed with trench(27). A semiconductor layer (20) is formed in the trench for coupling a control signal (VB) through a sidewall (25) of the trench to route a current (Ic) through a bottom surface (23) of the trench.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract: A semiconductor structure includes a monocrystalline silicon substrate, an amorphous oxide material overlying the monocrystalline silicon substrate, a monocrystalline perovskite oxide material overlying the amorphous oxide material, and a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material. A composite transistor includes a first transistor having first active regions formed in the monocrystalline silicon substrate, a second transistor having second active regions formed in the monocrystalline compound semiconductor material, and a mode control terminal for controlling the first transistor and the second transistor.

Abstract: A semiconductor structure for a high frequency monolithic switch matrix includes a monocrystalline silicon substrate, an amorphous oxide material overlying the monocrystalline silicon substrate, a monocrystalline perovskite oxide material overlying the amorphous oxide material, a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material, and a high frequency semiconductor integrated formed in and over the monocrystalline compound semiconductor material having one or more input ports and one or more output ports. The high frequency semiconductor integrated circuit also includes a high frequency switch circuit that is electrically coupled to a switch driver control circuit that is fabricated on the monocrystalline compound semiconductor material and which provides the DC signals required to control the high frequency circuit.

Abstract: The invention concerns a bipolar transistor with upper heterojunction comprising in particular stacked on a substrate: an emitter layer (EM); a base layer (BA), a collector layer (CO). In said transistor, the base-emitter junction surface is of smaller dimension than the base-collector junction surface and the material of the base layer has a lower electric conducting sensitivity to ion implantation than the electric conducting sensitivity of the material of the emitter layer to the same ion implant.

Abstract: The present invention provides a method of forming a super self-aligned bipolar transistor with enhanced electrical characteristics. The power gain and frequency response of the transistor are improved by horizontally etching an area for the base region that is wider than the active emitter and collector regions. By removing polysilicon layers within the device, the base region resistance goes down and unwanted capacitive effects are reduced.

Abstract: A semiconductor material which has a high carbon dopant concentration includes gallium, indium, arsenic and nitrogen. The disclosed semiconductor materials have a low sheet resistivity because of the high carbon dopant concentrations obtained. The material can be the base layer of gallium arsenide-based heterojunction bipolar transistors and can be lattice-matched to gallium arsenide emitter and/or collector layers by controlling concentrations of indium and nitrogen in the base layer. The base layer can have a graded band gap that is formed by changing the flow rates during deposition of III and V additive elements employed to reduce band gap relative to different III-V elements that represent the bulk of the layer. The flow rates of the III and V additive elements maintain an essentially constant doping-mobility product value during deposition and can be regulated to obtain pre-selected base-emitter voltages at junctions within a resulting transistor.

Abstract: A self-aligned double-polysilicon type bi-polar transistor with a heterojunction base comprises a semiconducting heterojunction region lying over an active region of a semiconductor substrate and over an isolating region delimiting the active region, and incorporating the intrinsic base region of the transistor. An emitter region situated above the active region and coming into contact with the upper surface of the semiconducting heterojunction region. A polysilicon layer forming the extrinsic base region of the transistor, situated on each side of the emitter region and separated from the semiconducting heterojunction region by a separation layer comprising an electrically conducting connection part situated just outside the emitter region. This connection part ensures an electrical contact between the extrinsic base and the intrinsic base.

Abstract: Disclosed is a manufacturing method to fabricate Heterojunction Bipolar Transistors (HBTs) that enables self-alignment of emitter and base metal contact layers with precise sub-micron spacing using a dielectric-assisted metal lift-off process. Such an HBT process relies on the formation of an “H-shaped” dielectric (i.e., Si3N4/SiO2) mask conformally deposited on top of the emitter contact metalization that is used to remove excess base metal through lift-off by a wet chemical HF-based etch. This HBT process also uses a thin selective etch-stop layer buried within the emitter layer to prevent wet chemical over-etching to the base and improves HBT reliability by forming a non-conducting, depleted ledge above the extrinsic base layer. The geometry of the self-aligned emitter and base metal contacts in the HBT insures conformal coverage of dielectric encapsulation films, preferably Si3N4 and/or SiO2, for reliable HBT emitter p-n junction passivation.

Abstract: Disclosed is a method for manufacturing a hetero junction bipolar transistor capable of forming a ledge by using a low-priced contact aligner and in a selective wet etching manner, without having any expensive stepper and dry etching and forming a ballasting resistor, without having an additional NiCr thin film, whereby the manufacturing processes thereof can be embodied in simple and easy manners, thereby improving productivity and an economical efficiency.

Abstract: A method of manufacturing a hetero-junction bipolar transistor including a carbon-doped base layer includes the steps of (a) growing a base layer on an underlying layer through chemical vapor deposition, (b) forming at least one semiconductor layer over the base layer, and (c) then subjecting the base layer to thermal annealing at a temperature of 520° C. to 650° C.

Abstract: In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

Abstract: An electronic power device is integrated on a substrate of semiconductor material having a first conductivity type, on which an epitaxial layer of the same type of conductivity is grown. The power device comprises a power stage PT and a control stage CT, this latter enclosed in an isolated region having a second type of conductivity type. The power stage PT comprises a first buried area having the second type of conductivity type and a second buried area, partially overlapping the first buried area and having the first conductivity type. The isolation region and the control stage CT comprise respectively a third buried area, having the second conductivity type, and a fourth buried area, partially overlapped to the third buried area and having the first conductivity type. Said first, second, third and fourth buried areas are formed in the epitaxial layers at a depth sufficient to allow the power stage PT and the control stage CT to be entirely formed in the epitaxial layers.

Abstract: A Heterojunction Bipolar Transistor (HBT) is provided which is formed by selectively depositing silicon germanium (SiGe) in a base region subsequent to the deposition of the base electrodes. Vertical bridging structures of SiGe are formed in the intrinsic area of the base to connect to the base electrode. During the formation of the dielectric sidewall defining the emitter space the SiGe base region is protected with a thin coat of oxide formed in a high-pressure low-temperature oxidation (HIPOX) process. Prior to the emitter silicon deposition the HIPOX is removed. A method for forming an HBT with a vertical bridging structure, as described above, is also provided.

Abstract: A SiGe heterojunction bipolar transistor including at least an emitter formed on a SiGe base region wherein the sidewalls of the emitter are protected by a conformal passivation layer. The conformal passivation layer is formed on the exposed sidewalls of said emitter prior to siliciding the structure. The presence of the passivation layer in the structure prevents silicide shorts from occurring by eliminating bridging between adjacent silicide regions; therefore improved SiGe bipolar yield is obtained. A method for forming such a structure is also provided.

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.