Abstract: A SiGe bipolar transistor including a semiconductor substrate having a collector and sub-collector region formed therein, wherein the collector and sub-collector are formed between isolation regions that are also present in the substrate is provided. Each isolation region includes a recessed surface and a non-recessed surface which are formed utilizing lithography and etching. A SiGe layer is formed on the substrate as well as the recessed non-recessed surfaces of each isolation region, the SiGe layer includes polycrystalline Si regions and a SiGe base region. A patterned insulator layer is formed on the SiGe base region; and an emitter is formed on the patterned insulator layer and in contact with the SiGe base region through an emitter window opening.

Abstract: A semiconductor structure and a method of forming same is disclosed. The method includes forming, on a substrate, an n-doped collector structure of InAs/AlSb materials; forming a base structure on said collector structure which base structure comprises p-doped GaSb; and forming, on said base structure, an n-doped emitter structure of InAs/AlSb materials. The collector and emitter structure are preferably superlattices each comprising a plurality of periods of InAs and AlSb sublayers. A heterojunction bipolar transistor manufactured using the method is disclosed.

Abstract: A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.

Abstract: High electron mobility transistors (HEMTs) and methods of fabricating HEMTs are provided Devices according to embodiments of the present invention include a gallium nitride (GaN) channel layer and an aluminum gallium nitride (AlGaN) barrier layer on the channel layer. A first ohmic contact is provided on the barrier layer to provide a source electrode and a second ohmic contact is also provided on the barrier layer and is spaced apart from the source electrode to provide a drain electrode. A GaN-based cap segment is provided on the barrier layer between the source electrode and the drain electrode. The GaN-based cap segment has a first sidewall adjacent and spaced apart from the source electrode and may have a second sidewall adjacent and spaced apart from the drain electrode. A non-ohmic contact is provided on the GaN-based cap segment to provide a gate contact. The gate contact has a first sidewall which is substantially aligned with the first sidewall of the GaN-based cap segment.

Abstract: A method of producing a bipolar transistor includes the step of providing a sacrificial mesa over a layer of SiGe in order to prevent a polysilicon covering layer from forming over a predetermined region of the SiGe layer forming the transistor base. After an etching process removes the sacrificial mesa and the SiGe layer is exposed, an oppositely doped material is applied over top of the SiGe layer to form an emitter. This makes it possible to realize a thin layer of silicon germanium to serve as the transistor base. This method prevents the base layer SiGe from being affected, as it otherwise would be using a conventional double-poly process.

Abstract: A bipolar transistor device with a large current capacity is formed by connecting a plurality of transistor elements to each other in parallel, each transistor element having a collector layer, a base layer, and an emitter layer formed respectively in a semiconductor substrate. In the bipolar transistor device, the base layers of a plurality of the transistor elements are extended in parallel to each other and those base layers are separated from each other. In each separated base layer, a first base electrode is formed on a part of the base layer which is separated from an emitter junction with the emitter layer, and a second base electrode is formed on another portion of the base layer closer to the emitter junction than the first base electrode. To dispose the base electrodes of a plurality of the transistor elements in parallel to each other, a base wiring is connected to the first base electrodes of those elements electrically.

Abstract: A method of manufacturing a semiconductor component and the component thereof includes forming a dielectric layer (620) over a portion of a passivation ledge (640) in an emitter layer (280) and overlapping a base contact (660) onto the dielectric layer (620).

Abstract: A bipolar transistor device with a large current capacity is formed by connecting a plurality of transistor elements to each other in parallel, each transistor element having a collector layer, a base layer, and an emitter layer formed respectively in a semiconductor substrate. In the bipolar transistor device, the base layers of a plurality of the transistor elements are extended in parallel to each other and those base layers are separated from each other. In each separated base layer, a first base electrode is formed on a part of the base layer which is separated from an emitter junction with the emitter layer, and a second base electrode is formed on another portion of the base layer closer to the emitter junction than the first base electrode. To dispose the base electrodes of a plurality of the transistor elements in parallel to each other, a base wiring is connected to the first base electrodes of those elements electrically.

Abstract: A voltage variable resistor formed on heterojunction bipolar transistor epitaxial material includes a current channel made on emitter material. Emitter mesas separated by a recess provide the contacts for the voltage variable resistor. Each mesa is topped with emitter metal forming the resistor contacts. The emitter mesas are layered on top of the current channel that is layered atop of a base layer. The voltage variable resistor's control contact is provided by a base contact located on the base layer and separated from the current channel.

Abstract: A method and structure for producing nitride based heterostructure devices having substantially lower reverse leakage currents and performance characteristics comparable to other conventional devices. The method and structure include placing one or more layers of nitride-based compounds over a substrate. Additionally, a dielectric layer including silicon dioxide is placed over the nitride-based layers.

Abstract: A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.

Abstract: In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.

Abstract: A silicon-germanium base capable of use in heterojunction bipolar transistor includes a silicon substrate having a mesa surrounded by a trench. The mesa has a top surface and a silicon-germanium layer is disposed only on the top surface of the mesa. In addition, a heterojunction bipolar transistor includes the silicon-germanium base as described.

Abstract: A method of production of a semiconductor device able to be miniaturized by preventing the decline of the hfe at a low current caused by an increase of a surface recombination current of a bipolar transistor and forming the external base region by self-alignment with respect to emitter polycrystalline silicon in the BiCMOS process. An intrinsic base region of a first semiconductor element is formed, an insulating film having an opening at an emitter formation region of part of the intrinsic base region is formed, and then an emitter electrode of the first semiconductor element and a protective film are formed on an insulating film having the opening. Next, a sidewall insulating film is left on the gate electrode side portion. Simultaneously, the insulating film is removed while partially leaving the emitter region forming-use insulating film under the emitter electrode.

Abstract: In accordance with the invention, a bipolar transistor is fabricated by disposing a sacrificial layer over the conventional semiconductor workpiece. The sacrificial layer is patterned into a stripe corresponding to the emitter stripe, and the base contacts are formed in relation to the sacrificial stripe. The stripe is removed, and the base and emitter are formed. In the preferred embodiment, the sacrificial layer is a stack of layers providing etch selectivity.

Abstract: Semiconductor structures and a method of forming semiconductor structures The avalanche breakdown characteristics, such as breakdown voltage and impact ionisation coefficient, of a semiconductor structure can be controlled by controlling the Brillouin-zone-averaged energy bandgap (<Ec>) of the material forming the structure. Consequently, the avalanche breakdown characteristics of a device may be tailored independently of the bandgap Eg. The Brillouin-zone-averaged energy bandgap (<Ec>) may be controlled by controlling the composition of the semiconductor used or by straining its lattice.

Abstract: Method and apparatus for improving the high current operation of bipolar transistors while minimizing adverse affects on high frequency response are disclosed. A local implant to increase the doping of the collector at the collector to base interface is achieved by the use of an angled ion implant of collector impurities through the emitter opening. The resulting area of increased collector doping is larger than the emitter opening, which minimizes carrier injection from the emitter to the collector, but is smaller than the area of the base.

Abstract: A monolithically integrated semiconductor device comprises: a hetero-junction bipolar transistor having at least an electrode contact layer which contacts directly with at least one of collector, base and emitter electrodes; and at least a passive device having at least a passive device electrode and at least a resistive layer, wherein the electrode contact layer and the resistive layer comprise the same compound semiconductor layer.

Abstract: A semiconductor structure and a method of forming same is disclosed. The method includes forming, on a substrate, an n-doped collector structure of InAs/AlSb materials; forming a base structure on said collector structure which base structure comprises p-doped GaSb; and forming, on said base structure, an n-doped emitter structure of InAs/AlSb materials. The collector and emitter structure are preferably superlattices each comprising a plurality of periods of InAs and AlSb sublayers. A heterojunction bipolar transistor manufactured using the method is disclosed.

Abstract: A transistor manufacturing process includes the formation, on a layer (15) that will form the base of the transistor, of a stack of an SiGe alloy layer (16), a silicon oxide layer (17) and a silicon nitride layer (18), so as to form in this layer, a false emitter (20), to form, in the layer (15) that will form the base, an extrinsic base region (22) and to siliconize the surface of this extrinsic base region, to cover the extrinsic base region (22) and the false emitter (20) with a silicon dioxide layer (24) which is chemically and mechanically polished down to the level of the false emitter (20), to etch the false emitter (20) in order to form a window (25) and to form, in the window (25) and on the silicon dioxide layer (24), a polysilicon emitter (27). This process has particular application to manufacturing heterojunction bipolar transistors.

Abstract: A semiconductor device includes: a semiconductor layered structure including a predetermined mesa portion, formed on a semiconductor substrate; a support member formed so as to bury the mesa portion; and an interconnection layer formed on a top surface of the semiconductor layered structure so as to extend over a top surface of the support member. The interconnection layer is in contact with only a top surface of the mesa portion without being in contact with a bottom surface of the mesa portion. The top surface of the support member has a smoothed profile, and the top surface of the mesa portion and the smoothed top surface of the support member are in substantially the same plane.

Abstract: Provided with a semiconductor device including: a semiconductor substrate having a first conductivity type; a first well having a second conductivity type formed in a first region in a major surface of the semiconductor substrate; a second well having the first conductivity type formed in a second region in the major surface of the semiconductor substrate; a first MOS transistor having the first conductivity type and a first contact region having the second conductivity type formed in the first well; a second MOS transistor having the second conductivity type and a second contact region having the second conductivity type formed in the second well; a heavily doped region of buried layer having the second conductivity type formed at a portion corresponding to the first contact region in the first well; and a heavily doped region of buried layer having the first conductivity type formed at a portion corresponding to the second contact region in the second well.

Abstract: A method of manufacturing a hetero-junction bipolar transistor including a carbon-doped base layer includes the steps of (a) growing a base layer on an underlying layer through chemical vapor deposition, (b) forming at least one semiconductor layer over the base layer, and (c) then subjecting the base layer to thermal annealing at a temperature of 520° C. to 650° C.

Abstract: Reduction in the base to collector capacitance of a heterojunction bipolar transistor, and, improved high frequency performance is achieved using existing materials and processes by undercutting the collector (5) under the base (7) along two parallel sides of the base mesa (7—FIG. 4), and providing a sloped collector edge (5—FIG. 6) along the remaining two parallel sides of the base. The foregoing is accomplished by selective etching and with the four sides of the mesa regions oriented as a non-rectangular parallelogram (7, 9—FIG. 4) in which one pair of sides is in parallel with one of the said [0 0 1] and [0 0 {overscore (1)}] planes of the crystalline structure and the other pair of sides in parallel with one of the [0 1 1] and [0 {overscore (1)} {overscore (1)}] planes of the crystalline structure.

Abstract: A method of fabricating a self-aligned bipolar junction transistor in a semiconductor structure having a first layer of silicon carbide generally having a first conductivity type and a second layer of silicon carbide generally having a second conductivity type, opposite to the first conductivity type. The method comprises forming a pillar in the second silicon carbide layer, the pillar having a side wall and defining an adjacent horizontal surface on the second layer, forming a dielectric layer having a predetermined thickness on the second semiconductor layer, including the side wall and the horizontal surface. After formation of the dielectric layer, the dielectric layer on a portion of the horizontal surface adjacent the side wall is anisotropically etched while at least a portion of the dielectric layer remains on the side wall, thereby exposing a portion of the horizontal surface.

Abstract: A porous silicon dioxide insulator having a low relative dielectric constant of about 2.0 or less is formed from a silicon carbide base layer. Initially, at least one layer of silicon carbide is deposited on a semiconductor substrate. The silicon carbide layer is then etched to form a porous silicon carbide layer, which is oxidized to produce the final porous silicon dioxide layer.

Abstract: A heterojunction bipolar transistor and its fabrication method is disclosed. The heterojunction bipolar transistor includes a substrate; a collector layer formed to have a ledge or MESA on the substrate; a collector electrode formed on the collector layer surrounding the ledge; a base layer formed on the ledge of the collector layer; an ohmic cap layer on the emitter layer; an emitter layer formed in the center of the base layer; an emitter electrode formed on the ohmic cap layer; a base electrode formed on the base layer surrounding the emitter electrode; an insulating layer formed to cover the base electrode and to overlay on the insulating layer; a metal wire formed to cover the emitter electrode; and an air bridge brought in contact with the metal wire and electrically connected to an external pad lying on an ion-implanted isolation region.

Abstract: The present invention is a semiconductor device having an element isolation structure of STI, in which after the formation of the STI trench, a silicon nitride film is left over only on the side wall portion of the trench, to form a side wall. Further, ions are implanted from the bottom surface of the trench on which the side wall is formed, and thus a high-concentration punch-through suppression region having the same conductivity as that of the substrate (or well) and a concentration higher that the impurity concentration of the other section close to the substrate (or well), is formed selectively only in the section of the substrate (or well) which is near the bottom surface of the trench. In this manner, the punch-through suppression region can be formed only in the bottom portion of the STI in a self-alignment manner by the thickness of the side wall.

Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

Abstract: A BiCMOS integrated circuit is formed with CMOS transistors on an SOI substrate in a silicon layer having a standard thickness of 0.1 &mgr;m to 0.2 &mgr;m and with Bipolar SiGe transistors formed in an epitaxial layer nominally 0.5 &mgr;m thick. The CMOS transistors are formed first with standard processing, then covered with an insulating film. The insulating film is stripped in the bipolar areas and an epitaxial SiGe layer is deposited on the Si substrate. The bipolar transistors are formed using the SiGe epi layer for the base and having an encapsulated structure for device isolation using shallow isolation trenches and the buried oxide.

Abstract: The adhesion of a barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by depositing the capping layer under high density plasma conditions at an elevated temperature, such as about 450° C. to about 650° C., e.g. about 450° C. to about 550° C. High density plasma deposition at such elevated temperatures increases the surface roughness of the exposed Cu metallization, thereby increasing adhesion of the deposited capping layer, such as silicon nitride and increasing the density of the silicon nitride capping layer thereby improving its etch stop characteristics. Embodiments of the present invention include treating the exposed surface of the Cu or Cu alloy interconnect member after CMP in a hydrogen-containing plasma, and depositing a silicon nitride capping layer under high density plasma conditions on the treated surface.

Abstract: A method of forming a DRAM capacitor that utilizes cap layers and spacers to surround the gate and bit line so that the necessary contact openings in a DRAM can be formed in two self-aligned contact processing operations. The capacitor of the DRAM is fabricated by forming contact node and openings within an insulating layer above a substrate, and then forming a first conductive layer conformal to the surface profile of the substrate above the substrate structure. Next, spacers are formed on the sidewalls of the conductive layer, and then a second conductive layer is formed filling the spacer between the spacers and over the substrate structure. Thereafter, a portion of the first conductive layer and the second conductive layer is removed to expose the spacers and the insulating layer. Finally, the spacers and the insulating layer are removed to expose a lower electrode structure that comprises the first and the second conductive layers.

Abstract: A process for fabricating a DRAM metal capacitor structure, featuring simultaneous formation of specific bit line, and storage node features, has been developed. The DRAM capacitor storage node is comprised of a stack of tungsten interconnect structures, overlying specific insulator layers, connected by tungsten plugs, formed in the specific insulator layers. Removal of a portion of the upper level insulator layers, exposes a stack of tungsten plugs and tungsten interconnects, that comprise the metal storage node structure, for the DRAM metal capacitor structure. The process of fabricating the DRAM metal capacitor structure, features the simultaneous formation of a tungsten bit line contact plug, and a tungsten storage node contact plug, in addition to the simultaneous formation of a tungsten bit line interconnect structure, and a tungsten interconnect structure, used as components of the DRAM metal capacitor structure.

Abstract: A silicon nitride film is left behind on only regions for forming the gate electrodes (word lines) of memory-cell selecting MISFETs constituting a DRAM, and it is not left behind on either of the gate electrodes of MISFETs constituting a logic LSI and those of MISFETs constituting the memory cells of an SRAM. Thereafter, the gate electrodes (word lines) in the DRAM and the gate electrodes in the logic LSI and the SRAM are simultaneously patterned by etching which employs the silicon nitride film and a photoresist film as a mask. Thus, in the manufacture of a semiconductor integrated circuit device wherein both the DRAM and the logic LSI are mounted, a contact hole forming process (gate-SAC) for the DRAM is made compatible with a contact hole forming process (L-SAC).

Abstract: In a semiconductor device manufacturing method, a buried collector region (5) of a bipolar transistor is formed, and then born is ion-implanted into at least the lower portion of a graft base region (15) to form a region (10) having a low donor concentration, whereby the capacitance between the collector and the base of the bipolar transistor can be reduced to achieve a high-speed operation of a circuit.

Abstract: A capacitor structure of a semiconductor device which includes a semiconductor substrate, a first metal layer formed on the substrate, and a second metal layer formed on the first metal layer. The first metal layer has a nitridation-treated film along its outer surface. A tungsten film having a rugged surface is formed on the entire outer surfaces of the first and second metal layers. Because of the nitridation-treated film along the first layer, the tungsten film will be uniformly distributed along the first and second metals. A thin dielectric film is then formed on the surface of the tungsten, followed by a third metal layer formed on the dielectric film.

Abstract: Regulation of eucaryotic gene expression is controlled by procaryotic peptides. The peptides recognize specific DNA sequences present in the gene, which may be derived from procaryotic genes, and either activate or repress gene transcription. Hybrid procaryotic peptides may be used containing both repressor and activator peptides.

Abstract: This invention discloses a semiconductor device comprising a semiconductor substrate, a first conducting layer formed on the surface of the semiconductor substrate, an insulating layer formed above the semiconductor substrate, the insulating layer having a contact hole reaching the first conducting layer to expose it, a second conducting layer formed on the insulating layer, the sidewall of the contact hole, and the first conducting layer, and an anti-oxidation layer formed on at least part of the surface of the second conducting layer.