Abstract: Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented, after silicidation and removal of any unreacted nickel, by treating the exposed surfaces of the silicon nitride sidewall spacers with a HDP plasma to oxidize nickel silicide thereon forming a surface layer comprising silicoin oxide and silicon oxynitride. Embodiments include treating the silicon nitride sidewall spacers with a HDP plasma to form a surface silicon oxide/silicon oxynitride region having a thickness of about 40 Å to about 50 Å.

Abstract: The present invention relates to a memory cell structure of a flash memory and a method for fabricating the same and, more particularly, to a flash memory having annular floating gates. The present invention uses the capacitance coupling between the source and the floating gate to form a channel in the substrate under the floating gate. Hot electrons are injected into the floating gate or released from the floating gate to the control gate through inerpoly dieletric by injection point on the top of floating gate In the proposed memory cell, a floating gate is etched to form an annular shape situated between a drain, a source, and two field oxides. An interpoly dielectric and a control gate are stacked in turn on the floating gate and on the surface of the substrate not covered by the floating gate through means of self-alignment. An injection point not covered by the SiN film of the interpoly dielectric is formed on the top of the floating gate.

Abstract: A method of manufacturing a semiconductor memory device with a gate dielectric stack is provided. A first insulating layer is formed on a semiconductor substrate with a first conductive type. A first conductive layer is formed on the first insulating layer. A second insulating layer with a stack of silicon dioxide/silicon nitride/silicon oxynitride/silicon dioxide is formed on the first conductive layer. A second conductive layer is formed on the second insulating layer. Patterning the first insulating layer, the first conductive layer, the second insulating layer and the second conductive layer to form a first gate dielectric layer, a floating gate, a second gate dielectric layer and a control gate. A source/drain with a second conductive type beside the floating gate is formed in the semiconductor substrate.

Abstract: A method for shrinking a semiconductor device is disclosed. An etch stop layer is eliminated and is replaced with a consumable second sidewall spacers so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. In a preferred embodiment, the present invention provides a method for forming self-aligned contacts by forming multi-layer structures on a region on a semiconductor substrate, forming first sidewall spacers around the multi-layer structures, forming second sidewall spacers around the first sidewall spacers, forming a dielectric layer directly over the substrate and in contact with second sidewall spacers, forming an opening in the dielectric layer to expose a portion of the region on the semiconductor substrate adjacent the second sidewall spacers, and filling the opening with a conductive material to form a contact.

Abstract: A nitride ready only memory cell with two top oxide layers and the method for manufacturing the same are disclosed. By high temperature oxidation (HTO), a more oxide layer is deposited on the floating gate of the ONO structure (Oxide-Nitride-Oxide structure) as a protecting layer so as to prevent the charges trapped in the silicon nitride layer of the ONO floating gate from being discharged between a polysilicon layer and a nitride layer so as to increase the reliability of the memory.

Abstract: Memory cell array and process of fabrication in which a floating gate is formed on a substrate for each of a plurality of memory cells, a control gate is formed above and in vertical alignment with each of the floating gates, source regions are formed in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, bit lines are formed in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, and a select gate is formed across the control gates, the floating gates, the bit lines and the source regions.

Abstract: The present invention relates to a method of manufacturing a semiconductor device. The present invention sequentially forms a DCS HTO film and a nitride film on the entire structure after a self align source etch process so that so that they can serve as a spacer for compensating for the sidewall of a gate structure damaged upon the self align source etch process. Therefore, the present invention can increase the integrity capability of data by preventing movement of charges and holes between a floating gate electrode and peripheral circuits and can mitigate a stress due to the nitride film in a subsequent process. Further, the present invention can prevent increase of the thickness of the dielectric film between a first polysilicon silicon layer and a second polysilicon layer in a subsequent annealing process and can secure the uniformity of a screen oxide film to make uniform the depth of the junction upon a high concentration ion implantation process.

Abstract: A ROM device is fabricated by forming a first conductive layer pattern including a sidewall, on an insulating layer on an integrated circuit substrate. Ions are implanted into the integrated circuit substrate using the first conductive layer pattern as an implantation mask. At least a portion of the integrated circuit substrate, and at least a portion of the sidewall are thermally oxidized, to form a thermal oxide layer on at least a portion of the integrated circuit substrate and on the sidewall, and to form a buried doping layer from the implanted ions beneath the thermal oxide layer. A second conductive layer pattern is then formed on at least a portion of the thermal oxide layer and on at least a portion of the first conductive layer pattern.

Abstract: CMOS semiconductor devices comprising MOS transistors of different channel conductivity type are formed in or on a common semiconductor substrate using a minimum number of critical masks. Embodiments include forming conductive gate/insulator layer stacks on spaced-apart, different conductivity portions of the main surface of the substrate, forming etch-resistant inner sidewall spacers on side surfaces of the layer stacks, and forming easily etched, amorphous semiconductor disposable outer sidewall spacers on the inner sidewall spacers. The use of disposable outer sidewall spacers allows heavy and light source/drain implantations of opposite conductivity type to be performed for forming PMOS and NMOS transistors with the use of only two critical masks, thereby reducing production cost and duration, while increasing manufacturing throughput.

Abstract: A method for manufacturing a semiconductor device having a non-volatile memory transistor may include the steps of forming a floating gate 22 over a semiconductor layer 10 through a first insulation layer 20, forming a second insulation layer 26 that contacts the floating gate 22, forming a control gate 28 over the second insulation layer 26, forming a source region 14 and a drain region 16 in the semiconductor layer 10, depositing a insulation layer 40 over the semiconductor layer 10, and etching the insulation layer 40 to form a sidewall insulation layer, wherein the etching of the insulation layer 40 is conducted such that the insulation layer 40 remains above the floating gate 40, and the floating gate 22 is not exposed.

Abstract: A method of fabricating a memory cell of self-aligned split gate flash memory first provides a substrate having an active area. A first gate insulating layer, a conductive layer and a buffer layer are formed within the active area. A portion of the buffer layer is removed to form a first opening. A buffer spacer is formed on the side walls of the first opening. A portion of the conductive layer and first gate insulating layer under the first opening are removed to form a second opening. The contact spacers, the source region and the contact plug are formed in the second opening in sequence. After the buffer spacers are removed, a third opening is formed. The bottom surface of the third opening and the top surface of the contact plug are oxidized to form the oxide layers. Another buffer spacers fill the third opening. The remaining buffer layer is removed to form the fourth opening.

Abstract: In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1, Vsg2 of the select gate of the select transistor in the selected block so as to make it possible to achieve a high speed reading without bringing about the breakdown of the insulating film interposed between the select gate and the channel of the select transistor. The high speed reading can also be made possible in the DINOR cell, the AND cell, NOR cell and the NAND cell having a single memory cell connected thereto, if the control gate voltage of the memory cell is made different from the voltage of the select gate of the select transistor.

Abstract: A plurality of core gate stacks and periphery gates on the substrate, each core gate stack and periphery gate having at least one side and first and second protective shoulders formed on said plurality of core gate stacks and periphery gates, such that a dopant can be implanted sequentially into source and drain regions of a substrate supporting the stacks to establish transistors and such that charge migration into said at least one side of the gate stacks during interlayer dielectric (ILD) formation and device metallization is prevented, at least the second shoulder being frabricated from at least one material selected from a group consisting essentially of nitride and silicon oxynitride (SiON).

Abstract: Methods and devices are disclosed which provide for memory devices having reduced memory cell square feature sizes. Such square feature sizes can permit large memory devices, on the order of a gigabyte or large, to be fabricated on one chip or die. The methods and devices disclosed, along with variations of them, utilize three dimensions as opposed to other memory devices which are fabricated in only two dimensions. Thus, the methods and devices disclosed, along with variations, contains substantially horizontal and vertical components.

Abstract: Methods of patterning sidewall spacers are provided. In one aspect, a method of fabricating a circuit device includes forming a gate on a substrate and forming a first oxide spacer and a second oxide spacer adjacent to the gate. The width of the gate and the first and second oxide spacers is measured. The widths of the first and second oxide spacers are trimmed if the width of the gate and the first and second oxide spacers exceeds a preselected maximum value by exposing the first and second oxide spacers to a solution of NH4OH, H2O2 and H2O for a preselected time and rinsing with deionized water. Spacer width may be finely tuned to reduce the risk of weak overlap and to improve device characteristics through shorter channels.

Abstract: To provide a semiconductor memory device in which no separation of a silicide layer formed on a control gate takes place and a process for manufacturing the same. A gate dielectric layer and floating gate (4 in FIG. 4) are formed on a silicon substrate. A sidewall made of polysilicon (7 in FIG. 4) is disposed on the lateral side of the floating gate in such a manner that a stop oxide layer (6a in FIG. 4) which functions as an etching stop for the polysilicon is sandwiched between the floating gate and the sidewall. A control gate (8 in FIG. 4) is laminated on the upper side of the floating gate having a step which is sloped by the sidewall in such a manner that an ONO layer (5 in FIG. 4) is sandwiched between the floating gate and the control gate.

Abstract: A method of fabricating a trenched flash memory cell is provided. A plurality of shallow trench isolation structures are formed to enclose at least an active area in a silicon substrate. A doped region is formed in the silicon substrate, followed by the deposition of an isolation layer on the silicon substrate. A first photo and etching process (PEP) is performed to form two trenches within the active area. A tunnel oxide layer, a floating gate, and ONO dielectric layer are formed in the trenches, respectively. A doped polysilicon layer is then formed on the silicon substrate to fill the trenches, followed by the removal of a portion of the doped polysilicon layer to form two controlling gates in the active area. Next, a self-alignment common source is formed between the two controlling gates and a plurality of spacers are formed on either side of each controlling gate. Finally, a silicide layer is formed on the surfaces of the controlling gates and the common source.

Abstract: A semiconductor device having a multi-layered spacer and a method of manufacturing the semiconductor device include gate electrodes each comprising a gate oxide layer, a gate conductive layer, and a capping dielectric layer formed on a semiconductor substrate, a gate polyoxide layer formed on sidewalls of the gate conductive layer and the gate oxide layer and being in contact with a predetermined portion of the semiconductor substrate, a silicon nitride layer being in contact with sidewalls of the capping dielectric layer and the gate polyoxide layer, an oxide layer being in contact with the silicon nitride layer, and an external spacer being in contact with the oxide layer.

Abstract: A method of fabricating a trenched flash memory cell is provided. A plurality of shallow trench isolation structures are formed to enclose at least an active area in a silicon substrate. A doped region is formed in the silicon substrate, followed by the deposition of an isolation layer on the silicon substrate. A first photo and etching process (PEP) is performed to form two trenches within the active area. A tunnel oxide layer, a floating gate, and an ONO dielectric layer are formed in the trenches, respectively. A doped polysilicon layer is then formed on the silicon substrate to fill the trenches, followed by the removal of a portion of the doped polysilicon layer to form two controlling gates in the active area. Next, a self-alignment common source is formed between the two controlling gates and a plurality of spacers are formed on either side of each controlling gate. Finally, a silicide layer is formed on the surfaces of the controlling gates and the common source.

Abstract: A merged two transistor memory cell of an EEPROM, and method of fabricating same, is provided. The memory cell includes a substrate and insulating layer formed on the substrate. It also includes a memory transistor having a floating gate and a control gate, and a select transistor having a gate that is shared with the memory transistor. The memory cell is configured so that the shared gate serves both as the control gate of the memory transistor and the wordline of the select transistor. The memory cell further includes an ONO stack film that is disposed between the floating gate and the shared gate. In fabricating the memory, the ONO stack film is formed adjacent to the top and side surfaces of the floating gate. The ONO stack film is also formed so as not to be interposed between a potion of the shared gate that is adjacent to the substrate and the insulating layer.

Abstract: A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. Use of the process to produce layers, spacers, memory units, and gates is also disclosed, as well as the structures so produced.

Abstract: An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floating gates. The dual gate cell increases the density of data that can be stored. Rather than providing a separate steering gate for each column of floating gates, an individual steering gate is shared by two adjacent columns of floating gates that have a diffusion between them. Processing methods of forming such a cell array include two etching steps to separate strips of conductive material into individual floating gates that are self-aligned with source/drain diffusions and other gate elements. In one embodiment, this is accomplished by two etching steps with separate masks.

Abstract: A modified nitride spacer and making of the same are disclosed. The modified nitride spacer is formed adjacent a high-temperature oxide (HTO) layer which in turn is formed adjacent the sidewalls of a gate electrode. It is shown that the placement of an intervening oxide layer between the sidewalls of the gate electrode and the nitride spacer, in that order only, provides a significant improvement in charge retention in floating gate memory cells. Also, forming of the spacer from pure, undoped oxide only yields the same favorable results.

Abstract: A method and apparatus are disclosed for achieving a desired thickness profile in a semiconductor device (44) using a flow-flange reactor (10), by adjusting input flow ratios in the flow-flange (12) of the reactor (10). A target thickness profile is established. A first set of optimum input flow ratios are then determined in response to the target thickness profile, based upon a first plurality of sample thickness profiles and a first plurality of sets of sample input flow ratios, wherein each of the sample thickness profiles corresponds to one of the first plurality of sets of sample input flow ratios. The input flow ratios of the reactor (10) are then adjusted in response to the first optimum set of input flow ratios.

Abstract: There is disclosed a method of manufacturing a flash memory device by which an insulating film spacer is formed on both sidewalls of a gate electrode and a drain region is then formed. Thus, the present invention can improve coverage during a deposition process for forming a select gate and reduce the overlapping area of a floating gate and a drain region. Therefore, as the resistance of the select gate itself is reduced depending on the coverage, the present invention can increase the operating speed of a device and can improve the erase characteristic by F-N tunneling due to reduced overlapping area.

Abstract: Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a plagiarized architecture obtained starting from a semiconductor substrate on which is provided a plurality of active elements extending along separate parallel lines e.g., memory cell bit lines and comprising gate regions made up of a first conducting layer, an intermediate dielectric layer and a second conducting layer with said regions being insulated from each other by insulation regions to form said architecture with said word lines being defined photolithographically by protective strips implemented by means of: a vertical profile etching for complete removal from the unprotected areas of the first conducting layer of the second conducting layer and of the intermediate dielectric layer respectively, and a following isotropic etching of the first conducting layer.

Abstract: A novel method of forming a polysilicon gate tip (poly tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly tip is further enhanced by forming a notched nitride layer over the tip. At the same time, a method of forming a self-aligned source (SAS) line is disclosed. A relatively thin polygate is formed so as to decrease the growth of the protrusion of conventional gate bird's beak (GBB) to a smaller and sharper tip. It will be known by those skilled in the art that GBB is easily damaged during conventional poly etching where polyoxide is used as a hard mask. To use polyoxide as a hard mask, thick polysilicon is needed in the first place. Such thick poly will increase gate coupling ratio, which has the attendant effect of degrading program and erasing performance of the memory cell.

Abstract: An EPROM cell and a method that includes a gate structure having a sidewall spacer. The sidewall spacer is made by way of an amorphous or polycrystalline silicon layer, which is converted into an insulating layer such as silicon dioxide. Deposition of the amorphous or polycrystalline silicon layer is more accurate and produces a more uniform layer than conventional dielectric layer deposition.

Abstract: In the flash memory cell, a floating gate overlaps a thick insulator covering a source region and overlaps a thin insulator covering a channel region. A control gate formed over the floating gate also partially overlaps the thick insulator. A thin sidewall spacer is formed on the floating gate sidewall, and a thick sidewall space is formed on the control gate sidewall. An erase gate is formed adjacent to the thin and thick sidewall spacers.

Abstract: A method is provided for forming a split-gate flash memory cell having reduced size, increased coupling ratio and improved program speed. A split-gate cell is also provided where the a first polysilicon layer forms the floating gate disposed over an intervening intergate oxide formed over a second polysilicon layer forming the control gate. However, the second polysilicon layer is also formed over the source region and overlying the other otherwise exposed portion of the floating gate such that this additional poly line now shares the voltage between the source and the floating gate, thereby reducing punch-through and junction breakdown voltages. In addition, the presence of another poly wall along the floating gate increases the coupling ratio between the source and the floating gate, which in turn improves program speed of the split-gate flash memory cell.

Abstract: A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. Use of the process to produce layers, spacers, memory units, and gates is also disclosed, as well as the structures so produced.

Abstract: A method for shrinking a semiconductor device is disclosed. An etch stop layer is eliminated and is replaced with a consumable second sidewall spacers so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. In a preferred embodiment, the present invention provides a method for forming self-aligned contacts by forming multi-layer structures on a region on a semiconductor substrate, forming first sidewall spacers around the multi-layer structures, forming second sidewall spacers around the first sidewall spacers, forming a dielectric layer directly over the substrate and in contact with second sidewall spacers, forming an opening in the dielectric layer to expose a portion of the region on the semiconductor substrate adjacent the second sidewall spacers, and filling the opening with a conductive material to form a contact.

Abstract: A method is provided to improve the control of bird's beak profile of poly in a split gate flash memory cell. The control of the bird's beak profile is achieved in a first embodiment where the polycrystalline layer of the floating gate is annealed at a high temperature. The annealing promotes small grain size and hence smoother surface in the polysilicon, which in turn promotes sharper poly tip. The smoother poly surface also results in thinner inter-poly between the floating gate and the control gate, which together with the sharp poly tip, enhances the erase speed of the split-gate flash memory cell. In a second embodiment, the performance is further enhanced by providing an amorphous silicon for the floating gate, because the amorphous nature of the silicon yields a very smooth surface. This smooth surface is transferred to the recrystallized state of the silicon layer through annealing. Thus, a good control for the bird's beak is achieved.

Abstract: An enlarged contact area (62, 162) is formed for a gate structure (14, 114) by providing a substrate (12, 112) having at least one gate electrode (22, 122) thereon. An implant sidewall (42, 142) is formed outwardly from the gate electrode (22, 122) and defines an implant area (44, 144) in the substrate (12, 112). A terminal (50, 150) is formed for the gate electrode (22, 122) by implanting dopants (46, 146) into the implant area (44, 144) in the substrate (12, 112). The implant sidewall (42, 142) is removed and an insulative sidewall (60, 160) is formed outwardly from the gate electrode (22, 122). The insulative sidewall (60, 160) has a thickness less than that of the implant sidewall (42, 142) to define an enlarged contact area (62, 162) for the terminal (50, 150).

Abstract: The present invention relates to a nonvolatile semiconductor memory device; which contains, in a memory cell, a memory transistor having a floating gate that is set over a tunnel insulating film on a semiconductor substrate, and a control gate that is set over an interlayer insulating film on this floating gate; and a select transistor having a select gate that is set over a gate insulating film on the semiconductor substrate; wherein the thickness of the gate insulating film in the above-mentioned select transistor is less than the thickness of the tunnel insulating film in the above-mentioned memory transistor. The present invention can provide a nonvolatile semiconductor memory device capable to operate at a high speed with a good stability.

Abstract: The method for forming flash memory includes the following steps. At first, a semiconductor substrate with an isolation region formed upon is provided. The semiconductor substrate has a pad oxide layer and a first nitride layer formed over. A portion of the first nitride layer and of the pad oxide layer are removed to define a gate region. A first oxide layer is formed and then a sidewall structure is formed. The semiconductor substrate is doped with first type dopants. A first thermal process is performed to form a second oxide layer and drive in the first type dopants. The sidewall structure and the first nitride layer are then removed, and the first oxide layer is removed to expose a portion of the substrate under the first oxide layer. Silicon grains are formed on the pad oxide layer, the exposed portion of substrate, and the second oxide layer. The exposed portion of the substrate is then etched to leave a rugged surface on the exposed portion of the substrate.

Abstract: A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F—N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.

Abstract: Ions of arsenic are selectively implanted at a high concentration into a substrate through a first passivation film of silicon dioxide to obtain a shallow junction, thereby forming a source region with a low resistivity and a first drain region. Then, after the first passivation film is removed, a second passivation film of silicon dioxide is deposited over the substrate as well as over a stacked cell electrode by a CVD process performed at a relatively low temperature. Thereafter, the substrate is annealed in a nitrogen ambient at such a temperature as activating the dopant introduced. In this manner, the dopant in source region and first drain region is activated.

Abstract: The present invention provides method to fabricate a snap-back flash EEPROMS device. The method begins by forming a gate structure 22 24 28 26 on a substrate. The gate structure comprises: a tunnel oxide layer 22, a floating gate 24, integrate dielectric layer 28, and a control gate 26. A drain 14 is formed adjacent to the gate structure by an masking 51 and ion implant process. Next, a source side doped region 18 is formed adjacent to and under a portion of the gate structure 22 24 28 26 by an masking and ion implant process. Spacers 32 are now formed on the sidewalls of the gate structure. A source 20 is formed overlapping portion of the side source doped region 18 and adjacent to the spacers 32. The side source doped region has a lower dopant concentration than the source 20. This method forms a snap-back memory cell wherein the side source doped region 18 is used to apply a high voltage to operate the EEPROM cell in a snap-back erase mode.

Abstract: A non-volatile semiconductor memory device is provided with a circuit that protects a tunnel oxide film from the charging phenomenon. This circuit comprises a first junction diode including an N+-type diffusion layer and a P-type well, and a second junction diode including a P-type well and an N-type well. When a voltage applied to the control gate is greater than all of a write voltage, a read voltage, and an erasure voltage that would be applied to the control gate, a current is guided through that circuit.

Abstract: Nonvolatile memory cell and process in which a control gate or a thick dielectric film is used as a mask in the formation of a floating gate and also as a step in the formation and alignment of a select gate. The floating gate is relatively thin and has a side wall with a rounded curvature which, in some embodiments, serves as a tunneling window for electrons migrating to the select gate during erase operations. In other embodiments, the gate oxide beneath the floating gate is relatively thin, and the electrons tunnel through the gate oxide to the source region in the substrate below.

Abstract: A process for fabricating a semiconductor device includes the formation of a metal device feature layer using lithographic techniques, followed by an oxidation process to reduce the lateral dimension of the metal device feature. The oxidation process is carried out by selectively, laterally oxidizing the metal composition of the device feature that overlies a dielectric layer. The lateral oxidation process forms metal oxide sidewall spacers on the device feature. Upon completion of the oxidation process, the metal oxide sidewall spacers are removed and a residual layer of unoxidized metal remains. The lateral dimension of the residual layer can be substantially less than that achievable by optical lithographic techniques.

Abstract: A method is disclosed for forming a split-gate flash memory cell having a salicidated control gate and self-aligned contacts. Salicidation is normally performed with single gate devices, such as logic devices. In a split-gate where the control gate overlays the floating gate with an intervening intergate oxide layer, it is conventionally incompatible to form self-aligned silicides over the control gate due to its position at a different level from that of the floating gate. Furthermore, oxide spacers that are normally used are inadequate when applied to memory cells. It is shown in the present invention that by a judicious use of an additional nitride/oxide layer over the control gate, oxide spacers can now be used effectively to delineate areas on the control gate that can be silicided and also self-aligned.

Abstract: A MOS transistor in a single-transistor memory cell having a locally thickened gate oxide, and a process for producing the transistor. The MOS transistor can be used as a selection transistor in a single-transistor memory cell having nitride spacers, or another spacer material acting as an oxidation barrier. The transistor also has a bird's beak in the gate oxide to reduce leakage currents. The production process enables the bird's beak to be produced before the nitride spacers are produced. The MOS transistor can be used in a DRAM, particularly as a selection transistor.

Abstract: A floating gate electrode configuration and process reduces a space critical dimension between adjacent floating gate electrodes while reducing the consumption of a device isolation layer during etching of a dielectric layer overlying the floating gate electrode. The end portions of the floating gate electrode, which is formed separated on a device isolation region, have a step or rounded pattern. In order to realize such a pattern, after a first partial etch of a floating gate electrode material, polymer spacers or silicon nitride spacers are formed along the etched sidewalls. Then, using those spacers as an etching mask, a second etch is performed on the floating gate electrode material to separate the same. Furthermore, after forming polysilicon on the partially etched floating gate electrode material, blanket etching is performed on the polysilicon to form a floating gate electrode having a round pattern of end portions.

Abstract: The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device.

Abstract: A method of protecting a tunnel dielectric area from subsequent processing steps in EEPROM fabrication after formation of a memory cell poly 1 floating gate on a P-type substrate, including first implanting the substrate to form a buried N+ junction below and beside the floating gate, and then growing a first thin oxide layer over the N+ junction and on sidewalls of the floating gate and a selection device gate. A thin layer of polysilicon is deposited and then a second thin oxide layer is grown over the thin polysilicon layer. A photoresist is applied, and then removed from the top surface and the sidewalls of the gate structures. The second thin oxide layer is removed from the top surface and the vertical sidewalls of the gate structures.

Abstract: A flash memory and a method of forming a flash memory, includes forming a polysilicon wordline on a substrate, the wordline having first and second sidewalls, the first sidewall being tapered, with respect to a surface of the substrate, to have a slope angle and the second sidewall having a slope angle greater than the slope angle of the first sidewall. Thereafter, a polysilicon spacer is formed on the second sidewall such that the spacer includes only one side which abuts the second sidewall of the polysilicon wordline.

Abstract: A method for fabricating a polysilicon thin film transistor combining the channel oxidation process and the plasma hydrogenation process is disclosed. The fabrication process includes the following steps: (a) forming a field oxide layer on a silicon substrate, (b) forming a polysilicon layer on a portion of the field oxide layer to serve as a gate, (c) forming a gate oxide on the polysilicon layer and another portion of the field oxide layer, (d) forming a polysilicon channel on the gate oxide layer, (e) defining a source region and a drain region in a portion of the polysilicon channel, (f) oxidizing another portion of the polysilicon channel, (g) forming a dielectric layer on said polysilicon channel, and (h) hydrogenating said polysilicon thin film transistor by plasma. Such a combination results in an better efficiency for passivating the tail state traps, and can prevent the polysilicon thin film from being damaged caused by the plasma glow during the plasma hydrogenation process.

Abstract: An EEPROM (Electrically Erasable Programmable Read Only Memory) has a structure in which the corners of a floating gate electrode of each memory cell MISFET near the source region thereof are rounded. The EEPROM is manufactured by a method characterized in that the ions of an impurity at a high dose are implanted in self-alignment with the floating gate electrode and control gate electrode of the memory cell MISFET so as to form the source and drain regions thereof, whereupon an oxidizing treatment is carried out.