Abstract: A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure.

Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Abstract: A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed between a gate electrode and an outer portion of an active region of a FET. Also provided is a structure having a high-leakage dielectric formed between the gate electrode and the active region of the FET and a method of manufacturing such structure.

Abstract: Disclosed are embodiments of an integrated circuit structure that incorporates at least two field effect transistors (FETs) that have the same conductivity type and essentially identical semiconductor bodies (i.e., the same semiconductor material and, thereby the same conduction and valence band energies, the same source, drain, and channel dopant profiles, the same channel widths and lengths, etc.). However, due to different gate structures with different effective work functions, at least one of which is between the conduction and valence band energies of the semiconductor bodies, these FETs have selectively different threshold voltages, which are independent of process variables. Furthermore, through the use of different high-k dielectric materials and/or metal gate conductor materials, the embodiments allow threshold voltage differences of less than 700 mV to be achieved so that the integrated circuit structure can function at power supply voltages below 1.0V.

Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

Abstract: High voltage-resistant semiconductor devices adapted to control threshold voltage by utilizing threshold voltage variation caused by plasma damage resulting from the formation of multilayer wiring, and a manufacturing method thereof. Exemplary high voltage-resistant semiconductor devices include a plurality of MOS transistors having gate insulating films not less than about 350 ? in thickness on a silicon substrate, and the MOS transistors have different area ratios between gate electrode-gate insulating film contact areas and total opening areas of contacts formed on the gate electrodes.

Abstract: A method is provided for manufacturing an integrated circuit having a plurality of MOSFET devices, comprising the steps of: providing a plurality of MOSFET devices each having a first and a second structural parameter associated therewith, wherein a value of one of the first and a second structural parameter of each device is selected to provide a value of a performance parameter of the device substantially equal to a predetermined reference value, the predetermined reference value being the same for each device.

Abstract: Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.

Abstract: A method for forming a contactless flash memory cell array is disclosed. According to an embodiment of the invention, a plurality of active regions is formed on a substrate. An insulating layer is then deposited over the active regions, and a portion of the insulating layer is removed to form a one-dimensional slot and to provide access to the active regions. A bit line is then formed in the slot in contact with the active regions.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Abstract: A method of fabricating a semiconductor memory device includes alternately and repeatedly stacking sacrificial layers and insulating layers on a substrate, forming an active pattern penetrating the sacrificial layers and the insulating layers, continuously patterning the insulating layers and the sacrificial layers to form a trench, removing the sacrificial layers exposed in the trench to form recess regions exposing a sidewall of the active pattern, forming an information storage layer on the substrate, forming a gate conductive layer on the information storage layer, such that the gate conductive layer fills the recess regions and defines an empty region in the trench, the empty region being surrounded by the gate conductive layer, and performing an isotropic etch process with respect to the gate conductive layer to form gate electrodes in the recess regions, such that the gate electrodes are separated from each other.

Abstract: A method of manufacturing a semiconductor device is provided which comprises: forming a first gate insulating film and a second gate insulating film in an active region of a semiconductor substrate; introducing an impurity of a first conductivity type into a first site where a first body region is to be formed, the first site being disposed under the first gate insulating film in the active region; forming a gate electrode on each of the first gate insulating film and the second gate insulating film; and introducing an impurity of the first conductivity type into the first site and a second site where a second body region is to be formed, the second site being disposed under the second gate insulating film in the active region, to form the first body region and the second body region, respectively.

Abstract: A semiconductor device includes a substrate (20), a source region (58) formed over the substrate, a drain region (62) formed over the substrate, a first gate electrode (36) over the substrate adjacent to the source region and between the source and drain regions, and a second gate electrode (38) over the substrate adjacent to the drain region and between the source and drain regions.

Abstract: A method of manufacturing a semiconductor device includes forming a trench in an interlayer dielectric film on the semiconductor substrate, the trench reaching a semiconductor substrate and having a sidewall made of silicon nitride film; depositing a gate insulation film made of a HfSiO film at a temperature within a range of 200 degrees centigrade to 260 degrees centigrade, so that the HfSiO film is deposited on the semiconductor substrate which is exposed at a bottom surface of the trench without depositing the HfSiO film on the silicon nitride film; and filling the trench with a gate electrode made of metal.

Abstract: An SRAM finFET cell includes fins (30 . . . 40) and respective insulated gates (62 . . . 72) forming finFET transistors, together with interconnects (86 . . . 92) connecting the fins and gates. The regions of the fins not covered by the insulated gates are doped. Each of the fins (30 . . . 40) extends in the same longitudinal direction; and each of the fins (30 . . . 40) is arranged laterally adjacent to another fin of the same conductivity type. The cell design reduces the effects of process spread.

Abstract: A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the recess region, wherein a top surface of the device isolation layer adjacent to the recess region is lower than the bottom surface of the recess region.

Abstract: A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulating material, an active layer of crystalline semiconductor material, an upper gate insulating layer of crystalline rare earth insulating material, and an upper gate layer of crystalline rare earth conductive material. The upper gate layer and the upper gate electrically insulating layer are etched and a contact is deposited on the upper gate layer to define an upper gate structure. An impurity is implanted into the lower gate layer to define a lower gate area aligned with the upper gate structure. A source and drain are formed in the active layer and contacts are deposited on the source and drain, respectively.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate comprising an element isolation region; two gate electrodes formed in substantially parallel on the semiconductor substrate via respective gate insulating films; two channel regions each formed in regions of the semiconductor substrate under the two gate electrodes; a source/drain region formed in a region of the semiconductor substrate sandwiching the two channel regions; a first stress film formed so as to cover the semiconductor substrate and the two gate electrodes; and a second stress film formed in at least a portion of a void, the void being formed in a region between the two gate electrodes.

Abstract: A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A body region is formed in a semiconductor material that has a major surface. A gate trench is formed in the epitaxial layer and a gate structure is formed on the gate trench. A source region is formed adjacent the gate trench and extends from the major surface into the body region and a field plate trench is formed that extends from the major surface of the epitaxial layer through the source and through the body region. A field plate is formed in the field plate trench, wherein the field plate is electrically isolated from the sidewalls of the field plate trench. A source-field plate-body contact is made to the source region, the field plate and the body region. A gate contact is made to the gate region.

Abstract: An integrated circuit comprises a first source, a first drain, a second source, a first gate arranged between the first source and the first drain, and a second gate arranged between the first drain and the second source. The first and second gates define alternating first and second regions in the drain. The first and second gates are arranged farther apart in the first regions than in the second regions.

Abstract: A semiconductor memory device according to one embodiment includes: a semiconductor substrate having an active region divided by an element isolation region; a plurality of stacked-gate type memory cell transistors connected in series on the active region; select transistors connected to both ends of the plurality of memory cell transistors on the active region; and a bit line contact connected to a drain region belonging to the select transistor in the active region, a vertical cross sectional shape of a lower portion of the bit line contact in a channel width direction of the plurality of memory cell transistors being in a skirt shape.

Abstract: A gate of a transistor in an integrated circuit is protected against the production of an interconnection terminal for a source/drain region. The transistor includes a substrate, at least one active zone formed in the substrate, at least one insulating zone formed in the substrate and a gate, the gate being formed above an active zone. A dielectric layer is formed on the transistor, the dielectric layer covering the gate. The dielectric layer is then etched while leaving it remaining at least on the gate so that the gate is electrically insulated from other elements formed above the dielectric layer. This etching is preferably carried out using a mask which was used for fabricating the gate and a mask which was used for fabricating the insulating zone.

Abstract: A semiconductor device is provided with a semiconductor substrate, a plurality of active regions separated from each other by element isolation regions formed on the semiconductor substrate; gate oxide films formed on the active regions; gate electrodes formed on the gate oxide films; side wall insulation films formed on side surfaces of the gate electrodes; recessed parts formed in exposed surfaces of the active regions excluding regions that are covered by the gate electrodes and the side wall insulation films; dam insulation films provided to a periphery of the recessed parts; and silicon epitaxial layers formed within the recessed parts.

Abstract: A method of fabricating a semiconductor device having a gate spacer layer with a uniform thickness wherein a gate electrode layer pattern is formed on a substrate and ion implantation processes of respectively different doses are formed on side walls of the gate electrode layer patterns in respective first and second regions of the substrate. A first gate spacer layer is formed on the gate electrode layer pattern where the ion implantation process is performed. A second gate spacer layer is formed on the first gate spacer layer.

Abstract: A nonvolatile memory device including one resistor and one transistor. The resistor may correspond to a resistance layer electrically connected to a first impurity region and a second impurity region of the transistor.

Abstract: A semiconductor element structure includes a first MOS having a first high-K material and a first metal for use in a first gate, a second MOS having a second high-K material and a second metal for use in a second gate and a bridge channel disposed in a recess connecting the first gate and the second gate for electrically connecting the first gate and the second gate, wherein the bridge channel is embedded in at least one of the first gate and the second gate.

Abstract: An integrated circuit and gate oxide forming process are disclosed which provide a gate structure that is simple to integrate with conventional fabrication processes while providing different gate oxide thicknesses for different transistors within the integrated circuit. For a flash memory, which may utilize the invention, the different gate oxide thicknesses may be used for lower voltage transistors, memory array transistors, and higher voltage transistors.

Abstract: A method for forming multiple self-aligned gate stacks, the method comprising, forming a first group of gate stack layers on a first portion of a substrate, forming a second group of gate stack layers on a second portion of the substrate adjacent to the first portion of the substrate, etching to form a trench disposed between the first portion and the second portion of the substrate, and filling the trench with an insulating material.

Abstract: The present invention provides a thin film transistor having excellent formability and processability, and particularly a thin film transistor using plastics as a substrate; an organic semiconductor as an active layer; and SiO2 thin films formed by coating as a sealing layer and a gate insulating layer, and a process for producing the same. The present invention provides a field-effect type thin film transistor having an active layer of an organic semiconductor, comprising on a plastic substrate, a sealing layer of a SiO2 thin film formed by coating; a gate electrode; a gate insulating layer of a SiO2 thin film formed by coating; gate and drain electrodes; and a semiconductor active layer. The high-quality SiO2 thin film is obtained by using a silicon compound as a starting material and irradiating a coated thin film of the solution of the starting material with light in an oxygen atmosphere.

Abstract: A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.

Abstract: According to some embodiments of the invention, a method of forming a transistor includes forming a device isolation layer in a semiconductor substrate. The device isolation layer is formed to define at least one active region. A channel region is formed in a predetermined portion of the active region of the semiconductor substrate. Two channel portion holes are formed to extend downward from a main surface of the semiconductor substrate to be in contact with the channel region. Gate patterns fill the channel portion holes and cross the active region. The resulting transistor is capable of ensuring a constant threshold voltage without being affected by an alignment state of the channel portion hole and the gate pattern.

Abstract: By forming a stressed semiconductor material in a gate electrode, a biaxial tensile strain may be induced in the channel region, thereby significantly increasing the charge carrier mobility. This concept may be advantageously combined with additional strain-inducing sources, such as embedded strained semiconductor materials in the drain and source regions, thereby providing the potential for enhancing transistor performance without contributing to process complexity.

Abstract: By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.

Abstract: Systems and arrangements to interconnect cells and structures within cells of an integrated circuit to enhance cell density are disclosed. Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the wire pitch for at least one metallization layer is adjusted to match the pitch for the polysilicon gate. In one embodiment, the next to the lowest metallization layer running in the same orientation as the polysilicon gate, utilized to access the input or output of the interconnected cell structures is relaxed to match the minimum contacted gate pitch and the metal is aligned above each polysilicon gate. In another embodiment, the polysilicon gate pitch may be relaxed to attain a smaller lowest common multiple with the wire pitch for an integrated circuit to reduce the minimum step off.

Abstract: A method of fabricating a semiconductor device is provided. Spacers can be formed on adjacent gate structures and used as an ion implantation mask for forming source/drain regions. The spacers can include a nitride layer and an oxide layer. An etch stop layer can be provided between the gate structures, and the oxide layer can be removed from the spacers. A first oxide layer formed below the nitride layer can be protected from being etched away during removal of the oxide layer from the spacers by the etch stop layer. The etch stop layer and the first oxide layer can be removed, and an interlayer dielectric layer can be deposited.

Abstract: In a method of fabricating a semiconductor device, an additive gas is mixed with an etching gas to reduce a fluorine ratio of the etching gas. The etching gas having a reduced fluorine rate is utilized in the process for etching a nitride layer formed on an oxide layer to prevent the oxide layer formed below the nitride layer from being etched along with the nitride layer. The method comprises primarily etching an exposed charge storage layer using an etching gas; and secondarily etching the charge storage layer using the etching gas under a condition that a ratio of fluorine contained in the etching gas utilized in the secondary etching step is less than a ratio of fluorine contained in the etching gas utilized in the primary etching step. Thus, the tunnel insulating layer formed below the charge storage layer is not damaged when the charge storage layer is patterned.

Abstract: The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.

Abstract: A static random access memory at least includes: pluralities of transistors disposed on a substrate, each transistor at least includes a gate, a gate dielectric layer, a source doped region and a drain doped region, in which some of the source doped regions are used for connecting with a Vss voltage or a Vdd voltage, and a salicide layer disposed on the gates, the source doped regions except those source doped regions used for connecting a Vss voltage and a Vdd voltage and the drain doped regions.

Abstract: Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 9° or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.

Abstract: A memory capable of reducing the memory cell size is provided. This memory includes a first conductive type first impurity region formed on a memory cell array region of the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a plurality of second conductive type second impurity regions, formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode.

Abstract: A unit cell for an integrated circuit includes a first conductive type active region and a second conductive type active region which extend in a first direction. Each of the active regions has first and second ends. The first end of the second conductive type active region opposes the second end of the first conductive type active region. A poly-silicon pattern extends in the first direction across the first conductive type active region and second conductive type active region. A first contact region is adjacent the first end of the first conductive type active region in the first direction. A second contact region is adjacent the second end of the second conductive type active region in the first direction.

Abstract: Misalignment created during a multiple-patterning process is a serious challenge for critical dimension (CD) control and layout design in continuing integrated-circuit device scaling. A number of post-lithography misalignment correction technologies based on the shadow effect are invented for multi-patterning lithographic applications. When applied to transfer patterns from a top layer to an underneath layer, the subtractive shadow effect in anisotropic plasma etching combined with a hard-mask process, will shift the position of features such that the previously produced misalignment can be corrected. Also, additive shadow effect in a sputtering/evaporation process can be used. Misalignment correction methods allow the semiconductor industry to print sub-32 nm (half-pitch) features using the double-patterning technique with currently existing lithographic tools (e.g., 193-nm DUV scanner), therefore postponing the need of expensive next-generation lithography (NGL).

Abstract: A semiconductor device is formed with a normal, non-recessed, spacer structure in a cell region and a recessed spacer structure in a peripheral region. The recessed spacer structure is formed as by etch masking those in the cell region and exposing those in the peripheral region, then performing an etch process. The increased height of the cell region spacers is adapted to further prevent over-etching during gate interconnect formation which would otherwise result in etching through the spacer to the substrate and subsequent short circuit. Therefore, it is also possible to prevent bridge defects due to over-etching, which occurs because the barrier metal layer for a subsequent interconnection contact is accidentally connected to the underlying substrate. Also, since the recessed spacer structure is provided in the peripheral region, it is possible to remarkably enhance a resistance distribution of a cobalt silicide layer occurring in a gate line width of 100 nm or less.

Abstract: Semiconductor device structures and fabrication methods for field effect transistors in which a gate electrode is provided with an air gap or void disposed adjacent to a sidewall of the gate electrode. The void may be bounded by a dielectric spacer proximate to the sidewall of the gate electrode and a dielectric layer having a spaced relationship with the dielectric spacer. The methods of the invention involve the use of a temporary spacer consisting of a sacrificial material supplied adjacent to the sidewall of the gate electrode, which is removed after the dielectric layer is formed.

Abstract: A method of forming a MOSFET is provided. The method comprises forming a relatively thin layer of dielectric on a substrate. Depositing a gate material layer on the relatively thin layer of dielectric. Removing portions of the gate material layer to form a first and second gate material regions of predetermined lateral lengths. Introducing a first conductivity type dopant in the substrate to form a top gate using first edges of the first and second gate material regions as masks, Introducing a second conductivity dopant of high dopant density in the substrate to form a drain region adjacent the surface of the substrate using a second edge of the second gate material region as a mask to form a first edge of the drain region, wherein a spaced distance between the top gate and the drain region is determined by the lateral length of the second gate material region.

Abstract: The invention relates to a method of fabricating a flash memory device. According to the method, select transistors and memory cells are formed on, and junctions are formed in a semiconductor substrate. The semiconductor substrate between a select transistor and an adjacent memory cell are over etched using a hard mask pattern. Accordingly, migration of electrons can be prohibited and program disturbance characteristics can be improved. Further, a void is formed between the memory cells. Accordingly, an interference phenomenon between the memory cells can be reduced and, therefore, the reliability of a flash memory device can be improved.

Abstract: A method for fabricating a transistor having metal gate is disclosed. First, a substrate is provided, in which the substrate includes a first transistor region and a second transistor region. A plurality of dummy gates is formed on the substrate, and a dielectric layer is deposited on the dummy gate. The dummy gates are removed to form a plurality of openings in the dielectric layer. A high-k dielectric layer is formed to cover the surface of the dielectric layer and the opening, and a cap layer is formed on the high-k dielectric layer thereafter. The cap layer disposed in the second transistor region is removed, and a metal layer is deposited on the cap layer of the first transistor region and the high-k dielectric layer of the second transistor region. A conductive layer is formed to fill the openings of the first transistor region and the second transistor region.

Abstract: An apparatus and method for the reduction of gate leakage in deep sub-micron metal oxide semiconductor (MOS) transistors, especially useful for those used in a cross coupled static random access memory (SRAM) cell, is disclosed. In accordance with the invention, the active element of the SRAM cell is used to reduce the voltage on the gate of its transistor without impacting the switching speed of the circuit. Because the load on the output of the inverter is fixed, a reduction in the gate current is optimized to minimize the impact on the switching waveform of the memory cell. An active element formed by two materials with different Fermi potentials is used as a rectifying junction or diode. The rectifying junction also has a large parallel leakage path, which allows a finite current flow when a signal of opposite polarity is applied across this device.