Abstract: A method of fabricating an HV-I/O ESD MOS device comprising the following steps. A structure having a first device region, a second device region and an HV-I/O ESD MOS device region is provided. A gate is formed over an oxide layer within the first device region. A gate is formed over an oxide layer within the second device region. A gate is formed over an oxide layer within the HV-I/O ESD MOS device region. The first device gate oxide layer is thinner than the second device gate oxide layer and the HV-I/O ESD MOS device gate oxide layer. The gate and oxide layers within each region have exposed side walls. An LV-LDD mask is formed over the gate and the structure within the second device region. An LV-LDD implant is performed into the structure adjacent the first device gate and the HV-I/O ESD MOS device gate to form first device LV-LDD implants and HV-I/O ESD MOS device LV-LDD implants. The LV-LDD mask is removed. An HV-LDD mask is formed over the gate and the structure within the first device region.

Abstract: A method of forming metal fuses. A conductive layer is formed in a substrate. A dielectric layer is formed over the substrate. The dielectric layer has an opening that exposes a portion of the conductive layer. A metallic layer is formed over the dielectric layer. The metallic layer is patterned to form a metal fuse and a bonding pad. The bonding pad is electrically connected to the conductive layer via the opening. Both the metal fuse and the bonding pad have undercut sidewalls. Spacers are formed on the undercut sidewalls of the metal fuse and the bonding pad. Finally, a passivation layer that exposes the metal fuse and the bonding pad is formed over the substrate.

Abstract: An integrated circuit fuse is formed on a substrate by etching a polysilicon, metal or alloy layer deposited thereon to include a central region, at the end of which are zones with electrical contacts. The central region has at least two first electrically parallel arms. A zone of intersection of the first two arms forms a point for focusing a fusing current which facilitates the fusing of the fuse by increasing local current density flowing through the integrated circuit.

Abstract: A semiconductor device causing no malfunction and having high ESD resistance against all cases of surges as well as a method of manufacturing the same are obtained.

Abstract: The semiconductor device includes a semiconductor substrate, an insulating layer on the semiconductor substrate wherein a groove is patterned to a predetermined depth in an upper surface of the insulating layer, a fuse layer at sidewalls and on a bottom of the groove, and a wire connected electrically to the fuse layer.

Abstract: The current density profile in the conduction channel of a field effect transistor is controlled and thermal gradients are limited under extreme operating conditions by providing lateral resistive ballasting at the source/drain regions adjacent the conduction channel. A distributed resistance is formed by inhibiting conversion of a region of deposited salicide from a high resistance phase state to a low resistance phase state through formation of the deposit with a width or area less than a critical dimension.

Abstract: In a semiconductor device having a fuse and an etching stopper film covering the fuse, an optical window exposing the etching stopper film and a contact hole exposing a conductor pattern are formed simultaneously. By applying a dry etching process further to the etching stopper film, an insulation film covering the fuse is exposed in the optical window.

Abstract: Method and apparatus are disclosed for protection of a circuit against process-induced electrical discharge. The method includes forming a diode in close proximity to a charge collector structure capable of exhibiting the antenna effect, and connecting the diode to the charge collector structure by means of local interconnect techniques during intermediate processing steps. Additionally, the diode may be formed beneath a connecting pad to reduce or eliminate antenna effect problems without significant loss of die area.

Abstract: An improved fuse structure in an integrated circuit (IC) structure is made by forming a gate stack comprised of layers of polysilicon and a silicide. Subsequent to the formation of the silicide layer, an etch stop silicon nitride layer is deposited over the silicide layer. The silicon nitride layer is patterned to expose the silicide layer. A soft passivation layer is deposited over the exposed silicide layer. The soft passivation layer has a low thermal conductivity which confines energy in the silicide layer, minimizing the current needed to program the fuse. The inherent ductility of the soft passivation layer prevents the generation of cracks in the surrounding layers.

Abstract: Provided is a semiconductor device with a silicide protection structure that prevents the over-etching of a source/drain layer in forming a contact hole and prevents a voltage drop in surge voltage without increasing the area of the source/drain layer, as well as a manufacturing method of the device. There is defined an active region (AR) of an MOS transistor and a gate electrode (10) that constitutes a field-shield isolation structure formed in a rectangular loop shape. Over the FS gate electrode (10) and the active region (AR), a gate electrode (20) of the MOS transistor is formed so as to divide the FS gate electrode (10) in two. Each of the active regions (AR) facing each other across the gate electrode (20) has a silicide protection structure (PS1), whose surrounding is an S/D layer (30), and a silicide film (SF1) is formed over the structure (PS1).

Abstract: The invention includes a method for manufacturing a merged contact in a window, comprising opening a window to one of a source and a drain of a field effect transistor and to and only partially overlapping a gate electrode of the field effect transistor, and depositing an electrical conductor connecting the gate electrode with one of the source and the drain to provide a merged contact between the gate and one of the source and the drain. Also described are devices made thereby.

Abstract: A Schottky diode which provides a structure having no P-N junction while improving voltage resistance against a reverse bias when employed in combination with an insulated gate semiconductor device in particular. In order to attain the aforementioned object, a P-type impurity region having a surface exposed on a surface of an N-type semiconductor substrate functioning as a drain for functioning as a channel region and a gate insulator film covering it are provided. A gate electrode is extended from above the gate insulator film over a first taper of an oxide film. In a Schottky diode rendering the semiconductor substrate a cathode and having a boundary layer as a Schottky region, on the other hand, an anode electrode is extended from above the boundary layer over a second taper of the oxide film existing above an end portion of the boundary layer.

Abstract: The present invention relates to a laser fuse. The laser fuse comprises an element comprising a heat conductive material. The fuse also includes an absorption element comprising a material with an adjustable capacity for heat or light absorption that overlays the heat conductive element. The fuse also includes an outer insulating element that overlays and encloses the heat conductive element and the absorption element.

Abstract: A transient fuse (102) and antenna (110) for detecting charge-induced plasma damage in a device (112). When the transient fuse (102) is placed between the antenna (110) and the device (112), only charge-induced damage during a metal clear portion of an etch occurs in device (112). When the transient fuse (102) is placed between ground and both the device (112) and the antenna (110), charge-induced damage occurring during an overetch portion of the etch can be detected in the device (112).

Abstract: In an integrated circuit structure, the improvement comprising a self-passivating Cu-laser fuse characterized by resistance to oxidation and corrosion and improved adhesion in the interface between Cu and metallization lines and Cu and a dielectric cap subsequent to blowing the fuse by an energizing laser, the fuse comprising:

Abstract: Provided are a self-aligned semiconductor fuse structure, a method of making such a fuse structure, and apparatuses incorporating such a fuse structure. The fuse break point, that point at which the electrical link of which the fuse is part is severed by a laser beam, is self-aligned by the use of photolithographically patterned anti-reflective dielectric coatings. The self-alignment allows the size location of the break point to be less sensitive to the laser beam size and alignment. This has several advantages including allowing photolithographic control and effective size reduction of the laser spot irradiating the fuse material and surrounding structure. This permits reduced fuse pitch, increasing density and the efficiency of use of chip area, and results in reduced thermal exposure, which causes less damage to chip. In addition, laser alignment is less critical and therefore less timely, which increases throughput in fabrication.

Abstract: A metal silicide fuse for a semiconductor device. The fuse includes a conductive region positioned adjacent a common well of a first conductivity type, a terminal region positioned adjacent a well of a second conductivity type, and a narrowed region located between the terminal region and the conductive region and positioned adjacent a boundary between the two wells. Upon applying at least a programming current to the fuse, the fuse “blows” at the narrowed region. The diodes between wells of different conductivity types wells and the Schottky diode or diodes between the remaining portions of the fuse and wells adjacent thereto control the flow of current through the remainder of the fuse and through the associated wells of the semiconductor device. When the fuse has been “blown,” the diodes and Schottky diodes prevent current of a normal operating voltage from flowing through the wells of the semiconductor device.

Abstract: In a semiconductor device having a fuse and an etching stopper film covering the fuse, an optical window exposing the etching stopper film and a contact hole exposing a conductor pattern are formed simultaneously. By applying a dry etching process further to the etching stopper film, an insulation film covering the fuse is exposed in the optical window.

Abstract: A method of fabricating a semiconductor device has the steps of: forming a sacrificial layer having a first trench for exposing a first predetermined area of the substrate on the ESD protecting device region; forming a first impurity layer of a second conductivity type in the first predetermined area of the substrate on the ESD protecting region; patterning the sacrificial layer to form a second trench for exposing a second predetermined area of the substrate on the internal circuit device region and a third trench for exposing a third predetermined area of the substrate on the ESD protecting device region; forming a gate insulating layer on the exposed substrate, and then filling the first trench, the second trench and the third trench with a conductive layer which serves as a dummy gate electrode of the ESD protecting device, a gate electrode of the internal circuit device and a gate electrode of the ESD protecting device respectively; removing the sacrificial layer and then forming a second impurity layer

Abstract: There is described a semiconductor device having a copper fuse which prevents damage to a silicon substrate beneath the copper fuse, which would otherwise be caused by a laser beam radiated to blow the copper fuse. A light absorbing layer is formed on the copper fuse layer from material whose light absorption coefficient is greater than that of a copper wiring layer. Light absorbed by the light absorbing layer is transmitted, through heat conduction, to the copper wiring layer beneath the light absorbing layer and further to a barrier metal layer beneath the copper wiring layer. Even when the widely-used conventional laser beam of infrared wavelength is used, the copper fuse can be blown. Since a guard layer is formed below the fuse layer, there can be prevented damage to the silicon substrate, which would otherwise be caused by exposure to the laser beam of visible wavelength.

Abstract: A method of forming nano-scale features with conventional multilayer structures, and nano-scale features formed thereby. The method generally entails forming a multilayer structure that includes a polycrystalline layer and at least one constraining layer. The multilayer structure is patterned to form first and second structures, each of which includes the polycrystalline and constraining layers. At least the first structure is then locally heated, during which time the constraining layer restricts the thermal expansion of the polycrystalline layer of the first structure. As a result, stresses are induced in the polycrystalline layer of the first structure, causing substantially two-dimensional grain growth from the edge of the first structure. Sufficient grain growth occurs to produce a third structure which, based on the grain size of the polycrystalline layer, will be a nano-scale structure.

Abstract: In the fuse element structure of the semiconductor device, the first insulating film region is provided in a groove-like manner in the semiconductor substrate. Further, the fuse element is formed on the first insulating film region, and the second insulating film region is formed on the region on the fuse element and the first insulating film. The metal plug is connected to the fuse element, and the surface thereof is exposed to the surface of the second insulating film region. With this structure, the meltdown of the fuse by the laser blow is facilitated, and the area of the fuse is reduced. Thus, as the downsizing of the element is further advanced, it is possible to provide a fuse element structure capable of melting down a fuse without causing an affect on another fuse adjacent to the melted-down fuse with the scattering pieces thereof.

Abstract: An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors.

Abstract: A fuse area structure in a semiconductor device and a method of forming the same are provided. A ring-shaped guard ring which surrounds a fuse opening, for preventing moisture from seeping into the side surface of the exposed fuse opening, is included. The guard ring is integrally formed with a passivation film. In order to form the guard ring, a guard ring opening etching stop film is formed on a fuse line. A guard ring opening is formed using the etching stop film, and a contact hole is formed in a peripheral circuit. A conductive material layer for forming an upper interconnection layer is formed on the entire surface of a resultant structure on which the contact hole and the guard ring opening are formed. The conductive material layer formed on the guard ring opening is removed. The exposed etching stop film is removed. Finally, a passivation film is deposited on the entire surface of the resulting structure.

Abstract: A method for forming a novel thick oxide electrostatic discharge device using shallow trench isolation technology is described. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. The oxide within the trench is partially etched away leaving the oxide on the sidewalls and bottom of the trench. The oxide is polished away to the surface of the semiconductor substrate whereby oxide remains only on the sidewalls and bottom of the trench. A gate is formed within the trench whereby the gate is surrounded by the oxide. First ions are implanted into the semiconductor substrate adjacent to the trench to form N-wells. Second ions are implanted into the semiconductor substrate in a top portion of the N-wells to form source/drain regions. Third ions are implanted into the semiconductor substrate underlying the N-wells and underlying the trench to form electrostatic discharge trigger taps.

Abstract: Method and apparatus are disclosed for protection of a circuit against process-induced electrical discharge. The method includes forming a diode in close proximity to a charge collector structure capable of exhibiting the antenna effect, and connecting the diode to the charge collector structure by means of local interconnect techniques during intermediate processing steps. Additionally, the diode may be formed beneath a connecting pad to reduce or eliminate antenna effect problems without significant loss of die area.

Abstract: Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers—an overlying and underlying layer—on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: A fuse for use in an integrated circuit includes a dielectric layer into which a trench or void is etched defined by a top opening and a bottom floor. The trench includes at least one undercut which forms an overhang in the dielectric layer partially shielding the bottom floor. A second or barrier layer deposited onto the dielectric layer is interrupted or non-continuous at the undercut. A third, or electrically conductive layer, is electrically continuous over the fuse. A weak spot in the third layer exists in the lack of structural support by the second layer at the interruption. A further weak spot in the third layer exists in the electrical isolation of the conductor layer, i.e. no leakage current through the barrier layer, at the interruption.

Abstract: A sacrificial conductive path formed in an integrated circuit to temporarily couple together semiconductor structures of the integrated circuit. The sacrificial conductive path includes a sacrificial area that severs the electrical continuity when it is removed. The sacrificial conductive path may be used to protect the gate oxide of a capacitive structure from charge related damage during a plasma etch step. The sacrificial structure temporarily couples the conductive layer of the capacitor structure to the substrate to discharge any charge accumulation. The sacrificial area will be removed prior to operation of the integrated device to sever the connection between the gate and the substrate. The sacrificial conductive path may be formed by an interconnect, and the sacrificial area removed by a plasma etch step. The sacrificial conductive path may also be formed by a semiconductor fuse having a sacrificial area that is removed by laser trimming.

Abstract: A fuse for semiconductor devices, in accordance with the present invention, includes a cathode including a first dopant type, and an anode including a second dopant type where the second dopant type is opposite the first dopant type. A fuse link connects the cathode and the anode and includes the second dopant type. The fuse link and the cathode form a junction therebetween, and the junction is configured to be reverse biased relative to a cathode potential and an anode potential. A conductive layer is formed across the junction such that current flowing at the junction is diverted into the conductive layer to enhance material migration to program the fuse.

Abstract: A fuse link redundancy structure to implement redundant circuits within an integrated circuit has an insulating layer over a conductive layer of the fuse link is sufficiently thin and transparent to allow destruction of the conductive layer by an intense laser light. The redundancy structure has a fusible link formed of a layer of a conductive material deposited upon an insulating layer such as field oxide on the semiconductor substrate and connected between the redundant circuits and other circuits present on the integrated circuit. The layer of conductive material is either formed of a metal such as Aluminum or Tungsten, a heavily doped polycrystalline silicon, or an alloy of a metal such as Tungsten and a heavily doped polycrystalline silicon. A hard mask layer is placed upon the layer of conductive material during transistor processing to protect the layer of conductive material during formation of self-aligned sources and drains of transistors of the integrated circuit.

Abstract: An anti-fuse for programming a redundancy cell and a repair circuit having a programming apparatus are disclosed.

Abstract: A method of fabricating a salicide layer in an electrostatic discharge protection device. On a MOS transistor having a gate, a source region and a drain region, a salicide block layer is formed. The salicide layer is patterned to remaining covering the drain region only, and leaving the source region and other portions of the substrate exposed. The anti-reflection coating layer is then removed to expose the gate. A salicide layer is formed on the exposed source region, the gate and other exposed portion of the substrate, while the drain region is free from the salicide layer for being covered with the salicide block layer.

Abstract: A process of fabricating a sub-micron MOSFET device, featuring a high dielectric constant gate insulator layer, and a metal gate structure, has been developed. Processes performed at temperatures detrimental to the high dielectric, gate insulator layer, such as formation of spacers on the sides of subsequent gate structures, as well as formation of source/drain regions, are introduced prior to the formation of the high dielectric, gate insulator layer. This is accomplished via use of a dummy gate structure, comprised of silicon nitride, used as a mask to define the source/drain regions, and used as the structure in which sidewall spacers are formed on. After selective removal of the dummy gate structure, creating an opening in an interlevel dielectric layer exposing the MOSFET channel region, deposition of the high dielectric, gate insulator layer, on the surface of the MOSFET channel region, is performed.

Abstract: A protection device which is active during the manufacturing process of a semiconductor chip includes a protection transistor and an antenna. The protection transistor is connected between a metal line having devices to be protected electrically connected thereto and a ground supply, where the metal line is connected to devices to be protected. The antenna is formed of the same metal layer as the metal line and controls the operation of the protection transistor during the manufacturing process. The antenna is connected to a gate of the protection transistor. Optionally, there is a metal ring around the antenna which is connected to a drain of the protection transistor via the same metal layer as the metal line. During normal operation of the chip, the protection transistor is either active for other purposes or is turned off.

Abstract: An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.

Abstract: A method for forming a metal oxide semiconductor device having an improvement in its ESD ability and vertical BJT gain is disclosed. The method includes providing a semiconductor substrate, a well region, and isolation regions. The method also includes forming conducting electrodes by ion implantation to a first depth inside the well and then forming an inter-layer dielectric (ILD) overlying the overall surface of the resulting structure. The inter-layer dielectric is then patterned and etched to form contact windows and exposing the surfaces of the conducting electrodes. Subsequently, a plugging method is applied to implant impurity ions through the relevant contact windows into the respective conducting electrode to a second depth that is deeper than the first depth. Finally, the resulting structure is annealed to complete the overall procedure of the present invention.

Abstract: A first concave portion for the element isolation, a second concave portion for an aligning mark, and a third concave portion for an anti-fuse portion are formed simultaneously within a silicon substrate. After a silicon oxide film is formed on the entire surface, the silicon oxide film positioned within the second and third concave portions is removed. Then, a gate insulating film is formed on the entire surface, followed by forming a polysilicon film on the gate insulating film. Further, these polysilicon film and gate insulating film are selectively removed to form a gate electrode above an element region, an aligning mark portion in the second concave portion, and a gate electrode for an anti-fuse portion on the bottom surface of the third concave portion.

Abstract: A structure and method for making a cavity fuse over a gate conductor stack.

Abstract: An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.

Abstract: A structure and method of fabricating a metallization fuse line is disclosed. The structure can be formed on a semiconductor substrate, including an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper being thinner than the lower, the insulator structure having a plurality of openings of varying depth, and a metal structure inlaid in the insulator structure, the metal structure having first and second portions and a third portion there between that is substantially more resistive than the first and second portions, the third portion having a thickness substantially similar to the thickness of the upper layer of the insulator structure. The upper layer includes a nitride, the lower layer includes an oxide and the metal structure includes copper. The fuse structure allows formation of “easy to laser delete” thin metal fuses within segments of thick metal lines.

Abstract: A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.

Abstract: Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry are described. In one implementation, a first layer comprising a first conductive material is formed over a substrate. A second layer comprising a second conductive material different from the first conductive material is formed over the first layer and in conductive connection therewith. A fuse area is formed by removing at least a portion of one of the first and second layers. In a preferred aspect, an assembly of layers comprising one layer disposed intermediate two conductive layers is provided. At least a portion of the one layer is removed from between the two layers to provide a void therebetween. In another aspect, programming circuitry is provided over a substrate upon which the assembly of layers is provided.

Abstract: Described is a dynamic threshold field effect transistor (DTFET) that includes a gate-to-body contact structure within the gate. By forming the gate-to-body contact structure that can reduce the gate-to-body contact resistance and increase the device packing density, the DTFET can be used in silicon on insulator (SOI) technologies and take full advantages of the DT-CMOS performance benefit.

Abstract: A semiconductor device is provided without degrading the performance of an internal circuit, which has an SOI structure coexistingly having an SOI static electricity protection circuit to prevent an internal circuit from being damaged due to static electricity through an input/output pad. To achieve this, a structure is made by comprising a silicon substrate of a first conductivity type, a buried oxide film formed on the silicon substrate, a first silicon layer of the first conductivity type formed on the buried oxide film, a second silicon layer of the first conductivity type formed on the buried oxide film and having a thickness smaller than the first silicon layer of the first conductivity type, and an SOI static electricity protection circuit provided between an input/output pad and an internal circuit.

Abstract: A programmable fuse implements redundancy in semiconductor devices and enables the repair of defective elements. In an example embodiment, a fuse is built in the second-to-the-last metal interconnect layer used in the circuit. An opening to expose the fuse is incorporated into an existing mask of the last metal interconnect layer, typically the pad mask. The passivation layer on top of the bond pads is opened to expose the bonding pads. At the same time, a residual oxide window is defined over the fuse. The residual oxide covering the fuse provides for a reliable and reproducible fuse.

Abstract: Methods and arrangements that increase the process control during the fabrication of the control gate configuration in a non-volatile memory semiconductor device are provided. The methods and arrangements effectively prevent cracks from developing within a tungsten suicide layer that is part of a control gate structure within a non-volatile memory cell. Cracks within the tungsten silicide layer can affect the performance of the memory cell by increasing the resistance of the control gate configuration. The methods and arrangements prevent cracking of the tungsten silicide layer by minimizing the relative difference between temperatures associated with the deposition of the tungsten suicide layer and deposition of a subsequent overlying cap layer.

Abstract: A semiconductor nonvolatile storage that is an inter-gate insulating film breakdown type memory is configured by providing a field oxide film on a semiconductor substrate 1, a gate electrode on the field oxide film and a mask oxide film on the surface of the gate electrode, forming an opening m the mask oxide film and forming a memory oxide film on the gate electrode exposed thereat, providing a memory gate electrode of a size extending from over the memory oxide film to over the mask oxide film, and making the thickness of the memory oxide film thinner than the thickness of the mask oxide film.

Abstract: A semiconductor device has a plurality of fuse members (1a, 1b) composed of a metal that can be cut by laser light (4), disposed over a semiconductor substrate (5). The length L of the fuse members (1a, 1b) is smaller than a value obtained by subtracting an alignment error .alpha. of the laser light (4) from a spot diameter D of the laser light (4), i.e., the value (D-.alpha.). The fuse members (1a, 1b) are spaced a distance l larger than a value obtained by adding the alignment error .alpha. to the half of the spot diameter D, i.e., the value (D/2+.alpha.).

Abstract: A method of forming a grooved fuse (plug fuse) in the same step that via plugs are formed in the guard ring area 14 and in product device areas. A key point of the invention is to form fuses from the via plug layer, not from the metal layers. Also, key guard rings are formed around the plug guise. The invention can include the following: a semiconductor structure is provided having a fuse area, a guard ring area surrounding the fuse area; and a device area. First and second conductive strips are formed. First and second insulating layers are formed over the first and second conductive strips. Plug contacts and fuse plugs are formed through the first and second insulating layers to the first and second conductive strips. A third insulating layer is formed over the second insulating layer. Metal lines are formed over the third insulating layer in the device area. A fuse via opening is formed in the third insulating layer. A plug fuse is formed in the fuse via opening.