Recessed Oxide Formed By Localized Oxidation (i.e., Locos) Patents (Class 438/297)
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Patent number: 8080443Abstract: A method of making a device includes forming a first hard mask layer over an underlying layer, forming first features over the first hard mask layer, forming a first spacer layer over the first features, etching the first spacer layer to form a first spacer pattern and to expose top of the first features, removing the first features, patterning the first hard mask using the first spacer pattern as a mask to form first hard mask features, removing the first spacer pattern. The method also includes forming second features over the first hard mask features, forming a second spacer layer over the second features, etching the second spacer layer to form a second spacer pattern and to expose top of the second features, removing the second features, etching the first hard mask features using the second spacer pattern as a mask to form second hard mask features, and etching at least part of the underlying layer using the second hard mask features as a mask.Type: GrantFiled: October 27, 2008Date of Patent: December 20, 2011Assignee: SanDisk 3D LLCInventors: Yung-Tin Chen, Chun-Ming Wang, Steven J. Radigan
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Patent number: 8067293Abstract: A semiconductor device and a method of manufacturing the same. The method includes preparing a semiconductor substrate having high-voltage and low-voltage device regions, forming a field insulating layer in the high-voltage device region, forming a first gate oxide layer on the semiconductor substrate, exposing the semiconductor substrate in the low-voltage device region by etching part of the first gate oxide layer and also etching part of the field insulating layer to form a stepped field insulating layer, forming a second gate oxide layer on the first gate oxide layer in the high-voltage device region and on the exposed semiconductor substrate in the low-voltage device region, and forming a gate over the stepped field insulating layer and part of the second gate oxide layer in the high-voltage device region adjoining the field insulating layer.Type: GrantFiled: October 1, 2009Date of Patent: November 29, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Cho Eung Park
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Patent number: 8058129Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device and a method of manufacturing the same. A LDMOS device may include a high voltage well formed over a substrate, a reduced surface field region formed thereover which may be adjacent a body region, and/or an isolation layer. An isolation layer may include a predetermined area formed over a reduced surface field region, may be partially overlapped with a top surface of a substrate and/or may include an area formed adjacent a high voltage well. A low voltage well may be formed over a substrate. A gate electrode may extend from a predetermined top surface of a body region to a predetermined top surface of an isolation layer. A drain region may be formed over a low voltage well. A source region may be formed over a body region and may have at least a portion formed under a gate electrode.Type: GrantFiled: November 9, 2009Date of Patent: November 15, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Yong-Jun Lee
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Patent number: 8039359Abstract: In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.Type: GrantFiled: February 27, 2009Date of Patent: October 18, 2011Assignee: Semiconductor Components Industries, LLCInventors: Thomas Keena, Ki Chang, Francine Y. Robb, Mingjiao Liu, Ali Salih, John Michael Parsey, Jr., George Chang
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Patent number: 8003471Abstract: Systems and methods for raised source/drain with super steep retrograde channel. In accordance with a first embodiment of the present invention, in one embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments in accordance with one embodiment may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.Type: GrantFiled: March 1, 2010Date of Patent: August 23, 2011Inventors: James B. Burr, Archisman Bagchi, Jawad Nasrullah
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Publication number: 20110201169Abstract: The invention provides a method for activating impurity element added to a semiconductor and performing gettering process in shirt time, and a thermal treatment equipment enabling to perform such the heat-treating.Type: ApplicationFiled: January 28, 2011Publication date: August 18, 2011Inventor: Shunpei Yamazaki
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Patent number: 7998806Abstract: A method of manufacturing a semiconductor device includes forming an oxidation film over a first and a second device region, forming an first etching preventing film extending over a first and a second area, removing the first etching preventing film over the first area; removing the oxidation film over the first device region, forming a first gate insulating film over the first device region, removing the oxidation film over the second device region, forming a second gate insulating film over the second device region, forming a first gate electrode over the first gate insulating film, forming a second gate electrode over the second gate insulating film, forming first source and drain regions in the first device region at both sides of the first gate electrode, and forming second source and drain regions in the second device region at both sides of the second gate electrode.Type: GrantFiled: August 7, 2008Date of Patent: August 16, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Toru Anezaki
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Patent number: 7973333Abstract: A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a semi-conductor material of a second type of conductivity which is at least partially covered by a dielectric gate layer which also covers the semi-conductor material of the MOS-diode. The dielectric gate-layer comprises a first region of a first thickness and a second region of a second thickness. The first region covers the semi-conductor material of the MOS-diode and the second region is arranged on the drift region. A transition takes place from the first thickness to the second thickness such that an edge area of the drift region which is oriented towards the MOS-diode is arranged below the second area of the gate layer. The invention also relates to a method for the production of these types of DMOS-transistors.Type: GrantFiled: April 2, 2007Date of Patent: July 5, 2011Assignee: Telefunken Semiconductors GmbH & Co. KGInventors: Franz Dietz, Volker Dudek, Thomas Hoffmann, Michael Graf, Stefan Schwantes
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Publication number: 20110136311Abstract: A semiconductor device having a locally buried insulation layer and a method of manufacturing a semiconductor device having the same are provided, in which a gate electrode is formed on a substrate, and oxygen ions are implanted into an active region to form a locally buried insulation layer. An impurity layer is formed on the locally buried insulation layer to form a source/drain. A silicide layer is formed on the source/drain and on the gate electrode. The locally buried insulation layer can prevent junction leakage, decrease junction capacitance and prevent a critical voltage of an MOS transistor from increasing due to body bias, thereby to improve characteristics of the device.Type: ApplicationFiled: February 16, 2011Publication date: June 9, 2011Inventors: Dong-Suk SHIN, Ho Lee, Myung-Sun Kim
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Publication number: 20110084324Abstract: Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a bird's beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the bird's beak region and terminating at the inner edge of the bird's beak region, a gate crossing the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the guard region. A variation of a local oxidation of silicon process is used with an additional bird's beak implantation mask as well as minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density.Type: ApplicationFiled: October 9, 2009Publication date: April 14, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Emily Ann Donnelly, Byron Neville Burgess, Randolph W. Kahn, Todd Douglas Stubblefield
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Publication number: 20110081760Abstract: A method of manufacturing a lateral diffusion metal oxide semiconductor device includes following steps. First, a substrate having a first conductive type is provided. The substrate has a well, and the well has a second conductive type. Then, a body region is formed in the well, and a channel defining region is formed in the body region. The body region has the second conductive type, and the channel defining region has the first conductive type, so that the body region disposed between the channel defining region and the well and uncovered with the channel defining region forms a channel of the lateral diffusion metal oxide semiconductor device. Then, a gate structure is formed on the channel.Type: ApplicationFiled: October 1, 2009Publication date: April 7, 2011Inventor: Bo-Jui Huang
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Patent number: 7915110Abstract: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.Type: GrantFiled: March 27, 2009Date of Patent: March 29, 2011Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat à l'Energie AtomiqueInventors: Philippe Coronel, Claire Gallon, Claire Benouillet-Beranger
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Patent number: 7888234Abstract: A method for manufacturing a semiconductor body with a trench comprises the steps of etching the trench (11) in the semiconductor body (10) and forming a silicon oxide layer (12) on at least one side wall (14) of the trench (11) and on the bottom (15) of the trench (11) by means of thermal oxidation. Furthermore, the silicon oxide layer (12) on the bottom (15) of the trench (11) is removed and the trench (11) is filled with polysilicon that forms a polysilicon body (13).Type: GrantFiled: April 17, 2008Date of Patent: February 15, 2011Assignee: austriamicrosystems AGInventors: Martin Knaipp, Bernhard Löffler
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Patent number: 7883976Abstract: A semiconductor device and method for manufacturing the device with a planar halo profile is provided. The semiconductor device can be a MOSFET. The method of forming the structure includes forming an angled spacer adjacent a gate structure and implanting a halo implant at an angle to form a halo profile having low dopant concentration near a gate dielectric under the gate structure. The structure includes an underlying wafer or substrate and an angled gate spacer having an upper portion and an angled lower portion. The upper portion is structured to prevent halo dopants from penetrating an inversion layer of the structure. The structure further includes a low concentration halo dopant within a channel of a gate structure.Type: GrantFiled: December 13, 2007Date of Patent: February 8, 2011Assignee: International Business Machines CorporationInventors: Huilong Zhu, Jing Wang
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Patent number: 7871895Abstract: A method of forming shallow trench isolation (STI) regions for semiconductor devices, the method including defining STI trench openings within a semiconductor substrate; filling the STI trench openings with an initial trench fill material; defining a pattern of nano-scale openings over the substrate, at locations corresponding to the STI trench openings; transferring the pattern of nano-scale openings into the trench fill material so as to define a plurality of vertically oriented nano-scale openings in the trench fill material; and plugging upper portions of the nano-scale openings with additional trench fill material, thereby defining porous STI regions in the substrate.Type: GrantFiled: February 19, 2008Date of Patent: January 18, 2011Assignee: International Business Machines CorporationInventors: Ramachandra Divakaruni, Wai-Kin Li, Haining S. Yang
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Patent number: 7863077Abstract: An image sensor and method of manufacturing the same are disclosed. A semiconductor substrate can be prepared comprising a photodiode region, a transistor region, and a floating diffusion region. A gate dielectric can be disposed under a surface of the semiconductor substrate in the transistor region. A first dielectric pattern can be provided having a portion above and a portion below the surface of the semiconductor substrate in the photodiode and the floating diffusion regions. A second dielectric can be disposed under the gate dielectric. The second dielectric can extend the depth of the gate dielectric into the semiconductor substrate to space the movement path of photoelectrons from the photodiode region to the floating diffusion region.Type: GrantFiled: September 17, 2008Date of Patent: January 4, 2011Assignee: Dongbu Hitek Co., Ltd.Inventor: Dong Bin Park
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Patent number: 7863153Abstract: An efficient method is disclosed for creating different field oxide profiles in a local oxidation of silicon process (LOCOS process). The method comprises (1) forming a first portion of the field oxide with a first field oxide profile (e.g., an abrupt bird's beak profile) during a field oxide oxidation process, and (2) forming a second portion of the field oxide with a second field oxide profile (e.g., a graded bird's beak profile) during the field oxide oxidation process. A graded bird's beak profile enables higher breakdown voltages. An abrupt bird's beak profile enables higher packing densities. The method gives an integrated circuit designer the flexibility to create an appropriate field oxide profile at a desired location.Type: GrantFiled: July 13, 2006Date of Patent: January 4, 2011Assignee: National Semiconductor CorporationInventor: Richard W. Foote, Jr.
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Patent number: 7863145Abstract: A method for fabricating an LCOS device. The method includes providing a semiconductor substrate and forming a plurality of MOS transistor devices formed on a portion of the semiconductor substrate. The method includes forming a first dielectric layer overlying the plurality of transistor devices and forming a first metal layer overlying the first dielectric layer. The method includes forming a second dielectric layer overlying the first metal layer and forming a plurality of pixel regions made substantially of silver bearing material overlying the second dielectric layer. In a preferred embodiment, the silver bearing material has much higher reflectivity for wavelengths of 450 nanometers and greater.Type: GrantFiled: September 19, 2008Date of Patent: January 4, 2011Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Yanghui Oliver Xiang, Enlian Lu
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Patent number: 7863692Abstract: Embodiments relate to a semiconductor device in which a first oxide layer may be formed in a channel area under the gate electrode. An electric field loaded on the gate electrode may be reduced when electrons are implanted from the source to the drain, the acceleration of electrons may be reduced, and the electrons implanted in the second oxide layer may be restrained. This may improve the hot-carrier effect, resulting in the increased reliability of the semiconductor device.Type: GrantFiled: September 13, 2007Date of Patent: January 4, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Young-Suk Ko
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Patent number: 7855117Abstract: In a method of forming a thin layer (e.g., a charge trapping nitride layer) of a semiconductor device (e.g. a charge trapping type non-volatile memory device), the nitride layer may be formed on a first area of a substrate. A blocking layer may be formed on the nitride layer. An oxide layer may be formed on a second area of the substrate while preventing or reducing an oxidation of the nitride layer by a radical oxidation process in which oxygen radicals react with the second area of the substrate and the blocking layer in the first area of the substrate. The nitride layer may ensure sufficient charge trapping sites and may have a uniform thickness without oxidation thereof in the radical oxidation process.Type: GrantFiled: October 31, 2006Date of Patent: December 21, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Jun Jang, Ho-Min Son, Woong Lee, Yong-Woo Hyung, Jung-Geun Jee
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Patent number: 7847365Abstract: A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with a P+ source region and an N+ contact region. The first N-well surrounds the P+ source region and the N+ contact region. An N-type MOSFET includes a second N-well disposed in a P-type substrate, a second P-type region disposed in the second N-well, an N+drain region disposed in the second N-well, a second source electrode formed with an N+ source region and a P+ contact region. The second P-type region surrounds the N+ source region and the P+ contact region. A plurality of separated P-type regions is disposed in the P-type substrate to provide isolation for transistors.Type: GrantFiled: October 14, 2005Date of Patent: December 7, 2010Assignee: System General Corp.Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-Yu Lin, Ta-yung Yang
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Publication number: 20100270614Abstract: An embodiment method for forming a MOS transistor for power applications in a substrate of semiconductor material, said method being integrated in a process for manufacturing integrated circuits which uses an STI technique for forming the insulating regions. The method includes the phases of forming an insulating element on a top surface of the substrate and forming a control electrode on a free surface of the insulating element. The insulating element insulates the control electrode from the substrate. Said insulating element comprises a first portion and a second portion. The extension of the first portion along a first direction perpendicular to the top surface is lower than the extension of the second portion along such first direction. The phase of forming the insulating element comprises generating said second portion by locally oxidizing the top surface.Type: ApplicationFiled: April 22, 2010Publication date: October 28, 2010Applicant: STMICROELECTRONICS S.R.L.Inventors: Giuseppe CROCE, Paolo GATTARI, Andrea PALEARI, Alessandro DUNDULACHI
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Patent number: 7816206Abstract: The semiconductor device comprises a silicon substrate 14 having a step formed in the surface which makes the surface in a flash memory cell region 10 lower than the surface in a peripheral circuit region 12; a device isolation region 20a formed in a trench 18 in the flash memory cell region 10; a device isolation region 20c formed in a trench 24 deeper than the trench 18 in the peripheral circuit region 12; a flash memory cell 46 including a floating gate 32 and a control gate 40 formed on the device region defined by the device isolation region 20a; and transistors 62, 66 formed on the device regions defined by the device isolation region 20c.Type: GrantFiled: December 31, 2008Date of Patent: October 19, 2010Assignee: Fujitsu Semiconductor LimitedInventor: Jusuke Ogura
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Patent number: 7807518Abstract: The present invention provides a semiconductor memory device having a capacitor electrode of a MOS capacitor formed in polygon and slanting faces enlarged toward an insulating film are provided therearound. A floating gate electrode is provided which extends from over a channel region of a MOSEFT to over corners of ends on the MOSFET side, of the capacitor electrode and which is opposite to the channel region and the capacitor electrode with a gate insulating film interposed therebetween.Type: GrantFiled: April 18, 2008Date of Patent: October 5, 2010Assignee: Oki Semiconductor Co., Ltd.Inventor: Tomohiko Tatsumi
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Publication number: 20100197098Abstract: A method of fabricating a semiconductor device includes forming in the substrate a well region comprising a first type of dopant; forming in the well region a base region comprising a second type of dopant different from the first type of dopant; and forming in the substrate source and drain regions comprising the first type of dopant. The method further includes forming on the substrate a gate electrode interposed laterally between the source and drain regions; and forming on the substrate a gate spacer disposed laterally between the source region and the gate electrode adjacent a side of the gate electrode and having a conductive feature embedded therein. The well region surrounds the drain region and the base region, and the base region is disposed partially underlying the gate electrode surrounding the source region defining a channel under the gate electrode of having a length substantially less than half the length of the gate electrode.Type: ApplicationFiled: April 9, 2010Publication date: August 5, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu Wen Chen, Fu-Hsin Chen, Tsung-Yi Huang, Yt Tsai
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Patent number: 7759205Abstract: Methods for producing a semiconductor device are provided. In one embodiment, a method includes the steps of: (i) fabricating a partially-completed semiconductor device including a substrate, a source/drain region in the substrate, a gate stack overlaying the substrate, and a sidewall spacer adjacent the gate stack; (ii) utilizing an anisotropic etch to remove an upper portion of the sidewall spacer while leaving intact a lower portion of the sidewall spacer overlaying the substrate; (iii) implanting ions in the source/drain region; and (iv) annealing the semiconductor device to activate the implanted ions. The step of annealing is performed with the lower portion of the sidewall spacer intact to deter the ingress of oxygen into the substrate and minimize under-oxide regrowth proximate the gate stack.Type: GrantFiled: January 16, 2009Date of Patent: July 20, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Kingsuk Maitra, John Iacoponi
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Patent number: 7749831Abstract: Methods for fabricating CMOS image sensor devices are provided, wherein active pixel sensors are constructed with non-planar transistors having vertical gate electrodes and channels, which minimize the effects of image lag and dark current.Type: GrantFiled: March 6, 2008Date of Patent: July 6, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Jeong Ho Lyu
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Publication number: 20100163980Abstract: A semiconductor device includes an isolation layer formed on and/or over a semiconductor substrate to define an isolation layer, a drift area formed in an active area separated by the isolation layer, a pad nitride layer pattern formed in a form of a plate on the drift area, and a gate electrode having step difference between lateral sides thereof due to the pad nitride layer pattern.Type: ApplicationFiled: December 21, 2009Publication date: July 1, 2010Inventor: Hyun-Tae Kim
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Patent number: 7736963Abstract: In an embodiment, a method of forming a gate structure for a semiconductor device includes forming a preliminary gate structure on a semiconductor substrate. The preliminary gate structure includes a gate oxide pattern and a conductive pattern sequentially stacked on the substrate. Then, a re-oxidation process is performed to the substrate having the preliminary gate structure using an oxygen radical including at least one oxygen atom, so that an oxide layer is formed on a surface of the substrate and sidewalls of the preliminary gate structure to form the gate structure for a semiconductor device. The thickness of the gate oxide pattern is prevented from increasing, and the quality of the oxide layer is improved.Type: GrantFiled: July 5, 2005Date of Patent: June 15, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Woong Lee, Young-Sub You, Hun-Hyeoung Leam, Yong-Woo Hyung, Jai-Dong Lee, Ki-Su Na, Jung-Hwan Kim
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Patent number: 7709907Abstract: An IGFET that minimizes the effect of the dislocation at the edge of the device region by displacing the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation. This minimizes the lateral diffusion of the source and drain impurities and the formation of metal silicides into the dislocation region. The spacing of the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation region is produced by providing additional lateral opposed second gate regions or oxide barrier layer extending from the oxide layer into the adjacent regions of the substrate region and the first gate region extending therebetween. Both the first gate region and the two second gate regions or barrier layer are used in the self-aligned processing of the source and drain regions. The first gate region defines the length of the channel, while the two opposed second gate regions or barrier layer define the width of the channel region.Type: GrantFiled: November 7, 2005Date of Patent: May 4, 2010Assignee: Intersil Americas Inc.Inventors: Stephen Joseph Gaul, Michael D. Church, James Edwin Vinson
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Patent number: 7696049Abstract: A double diffused region (65), (75), (85) is formed in a semiconductor substrate or in an epitaxial layer (20) formed on the semiconductor substrate. The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to the hard bake process, a heavy implant species such as arsenic is implanted into the epitaxial layer. During subsequent processing, such as during LOCOS formation, a double diffused region is formed by a thermal anneal. A dielectric layer (120) is formed on the epitaxial layer (20) and gate structures (130), (135) are formed over the dielectric layer (120).Type: GrantFiled: October 24, 2006Date of Patent: April 13, 2010Assignee: Texas Instruments IncorporatedInventors: Binghua Hu, Howard S. Lee, Henry L. Edwards, John Lin, Vladimir N. Bolkhovsky
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Publication number: 20100078715Abstract: A LDMOS transistor and a method for fabricating the same. A LDMOS transistor may include a P-type body region formed over a N-well. A LDMOS transistor may include a source region and a source contact region formed over a P-type body region. A LDMOS transistor may include a drain region spaced a distance from a P-type body region. A LOCOS may be formed over a surface of a N-well between a P-type body region and a drain region. A LDMOS transistor may include a main gate electrode formed over at least a portion of a LOCOS and a N-well. A LDMOS transistor may include a sub-gate electrode formed between a source region and a source contact region. A method for fabricating a LDMOS transistor is described herein.Type: ApplicationFiled: September 29, 2009Publication date: April 1, 2010Inventor: Sang-Yong Lee
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Patent number: 7670954Abstract: Provided is a method of manufacturing a semiconductor device including at least two processes. Under an atmosphere comprising hydrogen and oxygen, a sacrificial oxide film is formed on a silicon substrate that is provided with at least one nitride region. Then, the sacrificial oxide film and the nitride region are removed from the silicon substrate.Type: GrantFiled: November 21, 2007Date of Patent: March 2, 2010Assignee: Elpida Memory, Inc.Inventor: Takuo Ohashi
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Patent number: 7666747Abstract: A method that suppresses etching damage without increasing a chip area of a semiconductor device. An integrated circuit including a MOS transistor is formed in a device area, and a discharge diffusion region is formed in a device area, and a discharge diffusion region is formed in a grid area. The discharge diffusion region is connected to a metal wiring of the integrated circuit via a contact hole. Therefore, when the metal wiring is formed by a dry etching method, an electric charge stored in the metal wiring is discharged to a semiconductor substrate through the discharge diffusion region. Thus, etching damage of the MOS transistor is reduced. Since the discharge diffusion region and the contact hole are formed within the grid area, they are cut off by a dicing process, thus causing no increase in chip area of the semiconductor device.Type: GrantFiled: August 25, 2006Date of Patent: February 23, 2010Assignee: Oki Semiconductor Co., Ltd.Inventors: Keisuke Oosawa, Hideyuki Ando
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Publication number: 20100038726Abstract: A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.Type: ApplicationFiled: February 18, 2009Publication date: February 18, 2010Applicant: INTERSIL AMERICAS INC.Inventors: Stephen J. GAUL, Michael D. Church, Brent R. Doyle
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Patent number: 7662720Abstract: In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.Type: GrantFiled: April 29, 2008Date of Patent: February 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Kim, Eun-Jung Yun, Dong-Won Kim, Jae-Man Yoon
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Patent number: 7645668Abstract: A memory device includes a charge trapping layer on a substrate, an insulating layer on the substrate adjacent to the charge trapping layer and exposing an upper surface of the charge trapping layer, a dielectric layer on the exposed charge trapping layer and on the insulating layer, and an electrode on the dielectric layer, the electrode corresponding to the charge trapping layer.Type: GrantFiled: November 9, 2006Date of Patent: January 12, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Seob Kim, Jeong-Lim Nam, Won-Jin Kim, Guk-Hyon Yon
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Patent number: 7638397Abstract: The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The method continues by forming a first nitride spacer mask upon the first oxide and by forming a first oxide spacer mask upon the first nitride spacer mask. Thereafter, the method continues by forming a second nitride spacer mask upon the first oxide spacer mask and by forming a plurality of channels in the substrate that are aligned to the second nitride spacer mask. A dielectric is formed upon the channel length and the method continues by forming a gate layer over the plurality of channels. Because of the inventive method and the starting scale, each of the plurality of channels is narrower than the mean free path of semiconductive electron flow therein.Type: GrantFiled: August 25, 2008Date of Patent: December 29, 2009Assignee: Intel CorporationInventor: Brian Doyle
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Patent number: 7625783Abstract: A method by which generation of leak current can be suppressed and also a fine element can be formed by performing element isolation at a temperature at which a glass substrate can be used is provided. The method includes a first step of forming a base film over a glass substrate; a second step of forming a semiconductor film over the base film; a third step of forming, over the semiconductor film, a film preventing oxidation or nitridation of the semiconductor film into a predetermined pattern; and a fourth step of performing element isolation by radical oxidation or radical nitridation of a region of the semiconductor film, which is not covered with the predetermined pattern, at a temperature of the glass substrate lower than a strain point thereof by 100° C. or more, where radical oxidation or radical nitridation is performed over a semiconductor film placed apart from a plasma generation region, in a plasma treatment chamber with an electron temperature within the range of 0.5 to 1.Type: GrantFiled: November 17, 2006Date of Patent: December 1, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Satoru Saito
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Patent number: 7608515Abstract: A diffusion layer for semiconductor devices is provided. In accordance with embodiments of the present invention, a semiconductor device, such as a transistor, comprises doped regions surrounded by a diffusion barrier. The diffusion barrier may be formed by recessing regions of the substrate and implanting fluorine or carbon ions. A silicon layer may be epitaxially grown over the diffusion barrier in the recessed regions. Thereafter, the recessed regions may be filled and doped with a semiconductor or semiconductor alloy material. In an embodiment, a semiconductor alloy material, such as silicon carbon, is selected to induce a tensile stress in the channel region for an NMOS device, and a semiconductor alloy material, such as silicon germanium, is selected to induce a compressive stress in the channel region for a PMOS device.Type: GrantFiled: February 14, 2006Date of Patent: October 27, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yu Chen, Shui-Ming Cheng
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Patent number: 7601597Abstract: A manufacturing method for a super-junction semiconductor device is disclosed. The method includes a first step of depositing, on a low-resistivity semiconductor substrate of one conductivity type, at least an epitaxial layer of the one conductivity type which is to become a drift layer; a second step of forming a base region(s) of the other conductivity type and source regions of the one conductivity type to be used for formation of MOS gate structures; a third step of forming, by anisotropic vapor-phase etching using an insulating film mask, trenches that penetrate through the base region(s) and reach the low-resistivity semiconductor substrate or its vicinity; and a fourth step of burying epitaxial layers of the other conductivity type in the respective trenches, the first to fourth steps being executed in this order.Type: GrantFiled: September 13, 2007Date of Patent: October 13, 2009Assignee: Fuji Electric Device Technology Co., Ltd.Inventor: Manabu Takei
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Patent number: 7577493Abstract: A temperature regulating method in a thermal processing system includes controlling a heating means by performing integral operation, differential operation and proportional operation by means of a heating control section in a manner a detection temperature by a temperature detecting means becomes a predetermined target temperature, determining a first output control pattern by patterning a first operation amount for the heating control section to control the heating means depending upon a detection temperature detected by a first temperature detecting means, in controlling the heating means controlling the heating means by means of the heating control section depending upon the first output control pattern determined, and determining a second output control pattern by patterning at least a part of a second operation amount for the heating control section to control the heating means depending upon a detection temperature detected by a second temperature detecting means, in controlling the heating means.Type: GrantFiled: November 28, 2005Date of Patent: August 18, 2009Assignee: Hitachi Kokusai Electric Inc.Inventors: Masashi Sugishita, Masaaki Ueno
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Publication number: 20090191671Abstract: The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film.Type: ApplicationFiled: April 1, 2009Publication date: July 30, 2009Applicant: SHARP KABUSHIKI KAISHAInventors: Yutaka Takafuji, Asumori Fukushima, Masao Moriguchi
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Patent number: 7566482Abstract: A method in which a SOI substrate structure is fabricated by oxidation of graded porous Si is provided. The graded porous Si is formed by first implanting a dopant (p- or n-type) into a Si-containing substrate, activating the dopant using an activation anneal step and then anodizing the implanted and activated dopant region in a HF-containing solution. The graded porous Si has a relatively coarse top layer and a fine porous layer that is buried beneath the top layer. Upon a subsequent oxidation step, the fine buried porous layer is converted into a buried oxide, while the coarse top layer coalesces into a solid Si-containing over-layer by surface migration of Si atoms.Type: GrantFiled: September 30, 2003Date of Patent: July 28, 2009Assignee: International Business Machines CorporationInventors: Kwang Su Choe, Keith E. Fogel, Devendra K. Sadana
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Patent number: 7564056Abstract: Embodiments relate to a method for manufacturing a semiconductor device. In embodiments, the method may include forming a gate electrode on the semiconductor substrate, forming a pattern having a groove at the edge of the gate electrode and performing an etching process using the pattern as a mask, so that a groove extending from the edge of the gate electrode to LDD is formed, forming an ion diffusion barrier on the substrate having the gate electrode and the groove obtained through the previous step, implanting low-density ions onto the diffusion barrier, forming a spacer at edge of the gate electrode, and implanting high-density ions onto the substrate using the spacer and the gate electrode. A problem that may be caused by ion-implantation or diffusion process may be solved so that the hot carrier effects are improved, thereby improving the reliability of the semiconductor device.Type: GrantFiled: December 26, 2006Date of Patent: July 21, 2009Assignee: Dongbu HiTek Co., Ltd.Inventor: Young Suk Ko
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Patent number: 7550355Abstract: A boron ion stream may be used to implant ions, such as boron ions, into the sidewalls of an active area, such as an NFET active area. The boron ion stream has both vertical tilt and horizontal rotation components relative to the sidewalls and/or the silicon device, to provide a better line of sight onto the sidewalls. This may allow components of the silicon device to be moved closer together without unduly reducing the effectiveness of boron doping of NFET active area sidewalls, and provides an improved line of sight of a boron ion stream onto the sidewalls of an NFET active area prior to filling the surrounding trench with STI material.Type: GrantFiled: August 29, 2005Date of Patent: June 23, 2009Assignee: Toshiba America Electronic Components, Inc.Inventor: Yusuke Kohyama
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Patent number: 7544574Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.Type: GrantFiled: February 10, 2006Date of Patent: June 9, 2009Assignee: Intermolecular, Inc.Inventors: Tony P. Chiang, David E. Lazovsky, Thomas R. Boussie, Alexander Gorer
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Publication number: 20090142893Abstract: Non-volatile memory cell structures are described that are formed by a method including forming a first oxide layer on a horizontal strained substrate, forming at least one first recess through the first oxide layer to the strained substrate, and forming at least one vertical epitaxial structure in the recess. A crystal lattice of the vertical epitaxial structure is aligned with a crystal lattice of the strained substrate.Type: ApplicationFiled: February 6, 2009Publication date: June 4, 2009Inventor: Lyle Jones
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Patent number: 7521314Abstract: A method for forming a semiconductor device includes forming a liner over a semiconductor material including a control electrode. The method further includes forming a first spacer adjacent to the control electrode, wherein the first spacer has a first width. The method further includes implanting current electrode dopants. The method further includes removing the first spacer. The method further includes forming a second spacer adjacent the control electrode, wherein the second spacer has a second width and wherein the second width is less than the first width. The method further includes using the second spacer as a protective mask to selectively remove the liner. The method further includes forming a stressor layer overlying the control electrode and current electrode regions.Type: GrantFiled: April 20, 2007Date of Patent: April 21, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Dharmesh Jawarani, Konstantin V. Loiko, Andrew G. Nagy
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Patent number: 7514332Abstract: A method for manufacturing a semiconductor device includes the steps of (a) forming a first region by selectively ion-implanting a second conductive type impurity into a first conductive type semiconductor layer without thermally diffusing an impurity, (b) forming a gate electrode including an edge vicinity region that is aligned with the first region in the horizontal position, and (c) forming a body layer including the first region and a second region that is formed adjacent to the first region and self-aligned with the first region and an edge of the gate electrode by forming the second region with a step of selectively ion-implanting a second conductive type impurity into the first conductive type semiconductor layer without thermally diffusing an impurity.Type: GrantFiled: March 6, 2006Date of Patent: April 7, 2009Assignee: Oki Semiconductor Co., Ltd.Inventor: Hiroyuki Tanaka