Abstract: A method for forming a dual gate of a semiconductor devices by etching the polysilicon layer as a multi-step, resulting in etching velocities and anisotropic etching profiles for doped polysilicon and undoped polysilicon that are consistent and, since there is no difference in etching selectivity in the following etching step, damage of gate oxide layer by excess etching is prevented.

Abstract: A semiconductor device includes a semiconductor substrate having a trench in its surface, an insulating film in the trench, a doped conductive layer on the insulating film, a gate insulation film and a gate electrode on the doped conductive layer over the trench, and source and drain impurity regions in the surface of the semiconductor substrate at sides of the gate electrode.

Abstract: A method of manufacturing a LDHOS transistor having a dielectric block under the gate electrode. A high voltage well, low voltage well (LV PW), and field oxide regions having bird beaks are provided in a substrate and overlay the high voltage well and the low voltage well. In a key step, a dielectric block is formed over the bird beaks of the field oxide regions. A gate is formed over the dielectric block. After this the LDMOS device is completed. The invention's dielectric block covers the bird's beaks of the field oxide regions and enhances the e-field tolerance. The invention's e-field enhancement dielectric block relieves the e-field near the bird's beak, thus increasing the breakdown voltage of the transistor.

Abstract: The present invention aims to provide a field effect transistor which inhibits an aggregation of silicon atoms attendant on heat treatment and has stable source/drain shapes. The field effect transistor according to the present invention is manufactured using a substrate on which a silicon layer, an buried oxide film (BOX film) and an SOI layer are stacked in order. The field effect transistor has an element isolation layer formed in the SOI layer and further includes visored portions provided so as to cover angular portions on the main surface side of an activation layer defined by the element isolation layer.

Abstract: A split-gate flash memory includes a first gate insulating layer formed on a semiconductor substrate; a floating gate formed on the first gate insulating layer; a first spacer surrounding the floating gate and a side wall; a first junction region formed on a predetermined portion of the semiconductor substrate between two adjacent floating gates and having an opposite conductivity to that of the semiconductor substrate; a first conductive line formed on the first junction region between two adjacent first spacers; a second gate insulating layer formed on both a predetermined portion of the semiconductor substrate and the side wall of the first spacer; a word line formed on the second gate insulating layer, and having a vertical side wall and a uniform width; a second spacer formed on the vertical side wall of the word line; a second junction region formed on a portion of the semiconductor substrate adjacent the second spacer and having the same conductivity as the first junction region; an interlayer insulato

Abstract: A semiconductor photomask set for producing wafer alignment accuracy in a semiconductor fabrication process. The photomask set produces an alignment mark that is accurate for subsequent fabrication after undergoing a dual field oxide (FOX) fabrication process. Prior arts methods have traditionally covered the alignment marks with layers of oxide material.

Abstract: A method for fabricating oxide layers with different thicknesses on a substrate is described. A field oxide layer is formed on the substrate to define a first active region and a second active region therebetween. A first oxide layer is formed over the first active region. A thin oxynitride layer is formed on the first oxide layer.

Abstract: A method of forming a field oxide or isolation region in a semiconductor die. A nitride layer (over an oxide layer disposed over a substrate) is patterned and subsequently etched so that the nitride layer has a nearly vertical sidewall. The oxide layer and the substrate in the isolation region are etched to form a recess in the substrate having a sloped surface with respect to the nearly vertical sidewall of the nitride layer. A field oxide is then grown in the recess using a high pressure, dry oxidizing atmosphere. The sloped sidewall of the substrate effectively moves the face of the exposed substrate away from the edge of the nitride layer sidewall. Compared to non-sloped techniques, the oxidation appears to start with a built-in offset from the patterned etch. This leads to a reduction of oxide encroachment and a nearly non-existent bird's beak.

Abstract: A semiconductor device capable of controlling an electric potential of an electric conductor to reduce both a leakage caused by a punch-through and a junction leakage in a trench isolating structure having the electric conductor in a trench portion. In a trench isolating structure, an insulating film is disposed on an inner surface of a trench provided in a silicon substrate and doped polysilicon doped with phosphorus in a concentration of approximately 1×1020/cm3, for example, is buried as an electric conductor in a lower side of a trench space defined by the insulating film. In addition, a silicon oxide is buried as an insulator in an upper side of the trench space. For the silicon oxide to be used, a TEOS oxide film, a HDP oxide film or a SiOF film having a small dielectric constant may be buried.

Abstract: A semiconductor device having two or more types of separation oxide film are formed on the substrate of the semiconductor device by different methods so as to correspond with element types formed on the same semiconductor substrate. The method for producing the semiconductor device comprises a first separation oxide film formation process, and a second separation oxide film formation process. In the first separation oxide film formation process, a first mask layer is formed on the semiconductor substrate, the first mask layer of the element separation region of the logic element is selectively removed and the semiconductor substrate in the region area selectively oxidized. In second separation oxide film formation process, the remaining first mask layer is removed, a second mask layer is formed, the second mask layer of the element separation region of DRAM elements is then selectively removed, and the semiconductor substrate of the region is selectively oxidized.

Abstract: Oxidation methods and resulting structures comprising providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.

Abstract: The method for fabricating a nonvolatile semiconductor memory device comprises the step of forming an insulation film 14 on a semiconductor substrate 10; the step of introducing an impurity into the semiconductor substrate through the insulation film 14 to form a source/drain diffused region 20 and a pocket layer 18; the step of removing the insulation film 14; the step of forming a charge storage layer 28 on the semiconductor substrate 10; and forming gate electrode 40 on the charge storage layer 28 between the source/drain diffused layer 20. Whereby damage due to the ion implantation is not introduced into the charge storage layer. Thus, deterioration of cycling characteristics and data retention characteristics of the nonvolatile semiconductor memory device can be prevented.

Abstract: There is provided a method for manufacturing a nonvolatile memory device using a self-aligned source (SAS) process. The method has the steps of forming a field oxide film on a semiconductor substrate, thus defining an active region on the substrate; sequentially forming a tunnel oxide film, the first conductive layer, an interpoly dielectric layer and the second conductive layer on the substrate; forming a stacked gate of the first and second conductive layers on the active region; forming source/drain regions of first concentration by ion-implanting first impurity on the active region exposed by the stacked gate; removing the exposed field oxide film by using the word line as an etching mask; and exposing the source region of each cell and a portion of the word line and ion-implanting second impurity by using the exposed word line as a mask.

Abstract: A method of forming isolation structures in semiconductor substrates comprising exposing a region of the semiconductor simultaneously to a transforming agent and to a viscosity reducing agent so that the transforming agent transforms a portion of the substrate into an isolation structure and the viscosity reducing agent reduces the viscosity of the isolation structure during formation. In one embodiment, a silicon substrate is exposed to oxygen in the presence of fluorine so that a silicon oxide isolation region is formed. The fluorine reduces the viscosity of the silicon oxide isolation region during formation which results in less lateral, bird's beak encroachment under adjacent masking stacks and also results in lower internal stress in the isolation region during formation. The lower internal stress and the lessened lateral encroachment result in thicker and improved isolation regions.

Abstract: A method of forming an isolation structure includes the steps of: providing a silicon substrate; forming an upper pad oxide layer superjacent a top surface of the substrate, and a lower pad oxide layer subjacent a bottom surface of the substrate; forming a nitride masking layer superjacent the upper pad oxide layer, and a lower pad silicon nitride layer subjacent the lower pad oxide layer; patterning and etching the nitride masking layer to expose a portion of the upper pad oxide layer; applying a first etching solution to the exposed portion of the upper pad oxide layer to expose a portion of the substrate substantially defining the boundaries of an active area, and simultaneously forming an undercut cavity by removing a portion of the upper pad oxide layer under the exposed edges of the nitride masking layer surrounding the exposed portion of the substrate; performing an oxidation process to form an etching stop layer over the exposed portion of the substrate and in the undercut cavity, the oxidation proces

Abstract: A silicon germanium layer is deposited over a semi-conductor substrate with a gate insulating film interposed between the substrate and the silicon germanium layer. Then, an upper silicon layer in an amorphous state is deposited on the silicon germanium layer. Thereafter, a gate electrode is formed by patterning the silicon germanium layer and the upper silicon layer.

Abstract: A semiconductor device having a current mirror circuit composed of a first transistor element Q11 and a second transistor element Q12 is used as a single transistor TD. A plurality of transistor elements for composing the first transistor element Q11 on the current referring side and a plurality of transistor elements for composing the second transistor element Q12 on the current reference side are dispersedly disposed to provide a uniform distribution density on a semiconductor substrate possibly.

Abstract: A method of forming a semiconductor device, includes forming a layer of oxide on a semiconductor substrate, forming a layer of silicon nitride on the oxide layer, forming isolation regions in the substrate using the oxide layer and the nitride layer, removing the silicon nitride layer, ion implanting dopant ions using the original oxide layer as a screen, into the substrate, and removing the oxide layer and forming a gate oxide layer over the substrate. Another method of forming an active area of a semiconductor device, includes using a pad oxide, remaining after removing a film layer thereover of an oxide/film mask stack, for a screen layer for well implants formed in the substrate, removing the oxide layer and forming a gate oxide over the substrate, following defining the well implants, without using a sacrificial oxide.

Abstract: A RESURF LDMOS transistor (64) includes a RESURF region (42) that is self-aligned to a LOCOS field oxide region (44). The self-alignment produces a stable breakdown voltage BVdss by eliminating degradation associated with geometric misalignment and process tolerance variation.

Abstract: A process for fabricating a VLSI device comprising trench isolation regions. The trench isolation regions of a VLSI device is fabricated by a process comprising the following steps: Depositing and patterning pad layers on a substrate to form active regions separated from pad-layer-covered regions; forming side walls at each active region to cover portions of the active region other than its central portion; depositing a first oxide at the space surrounded by the side walls and the central portion of the active region; removing the side walls to form trenches at the active region; and depositing a second oxide on the substrate to fill the trenches and cover the first oxide, the second oxide and the first oxide together forming an oxide trench isolation region.

Abstract: To enable the reduction of ON-state resistance in a state in which the withstand voltage is secured, a semiconductor device according to the invention is provided with a gate electrode formed so that the gate electrode ranges from a gate oxide film formed on an N-type well region formed in a P-type semiconductor substrate to a selective oxide film, a P-type source region formed so that the source region is adjacent to the gate electrode, a P-type drain region formed in a position apart from the gate electrode and a P-type drift region (an LP layer) formed so that the drift region surrounds the drain region, and is characterized in that a P-type impurities layer (an FP layer) is formed so that the impurities layer is adjacent to the drain region.

Abstract: A process for forming an isolation region while substantially eliminating weak oxide effects, comprising the steps of obtaining a semiconductor substrate patterned with a plurality of mesas with sidewalls, each of the mesas comprising at least a first insulator layer and a second different insulated layer thereover, forming a trench between the mesas into the semiconductor substrate, removing a lateral portion of the first insulator layer exposed at the sidewalls of the mesas to thereby undercut the second insulator layer at its sidewall edges, forming an oxide layer on exposed areas of the semiconductor substrate below the undercut of the second insulator layer, and filling the trench with an insulator material.

Abstract: A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing an oxygen ion implantation step to create a stable defect region; a low energy implantation step to create an amorphous layer adjacent to the stable defect region, wherein the low energy implantation steps uses at least one ion other than oxygen; oxidation and, optionally, annealing, is provided. Silicon-on-insulator (SOI) materials comprising a semiconductor substrate having a DIBOX region in patterned or unpatterned forms is also provided herein.

Abstract: An isolation structure having both deep and shallow components is formed in a semiconductor workpiece by etching the workpiece to define raised precursor active device regions separated by sunken precursor isolation regions. An oxidation mask is formed to expose the precursor isolation regions, and the unmasked precursor isolation regions are exposed to oxidizing conditions to grow field oxides as the deep isolation component. Thermal growth of these field oxides creates topography which includes shallow recesses adjacent to the raised precursor active device regions. Deposition of conformal dielectric material such as high density plasma (HDP) deposited silicon oxide over the entire surface and within the recesses creates the shallow isolation component. Following planarization of the conformal dielectric material, fabrication of the device is completed by introducing conductivity-altering dopant into raised precursor active device regions.

Abstract: A method for achieving improved piezoelectric films for use in a resonator device is disclosed. The method is based on applicant's recognition that the texture of a piezoelectric film (e.g., as used in a piezoelectric resonator) is directly affected by the surface morphology of the underlying electrode, and additionally, the surface morphology of the electrode is affected by the surface morphology of the underlying oxide layer or Bragg stack. Accordingly, the invention comprises a method of making a device having a piezoelectric film and electrode comprising controlling the deposition and surface roughness of the electrode and optionally, the Bragg stack.

Abstract: Memory integrated circuitry includes an array of memory cells formed over a semiconductive substrate and occupying area thereover, at least some memory cells of the array being formed in lines of active area formed within the semiconductive substrate which are continuous between adjacent memory cells, said adjacent memory cells being isolated from one another relative to the continuous active area formed therebetween by a conductive line formed over said continuous active area between said adjacent memory cells. At least some adjacent lines of continuous active area within the array are isolated from one another by LOCOS field oxide formed therebetween. The respective area consumed by individual of said adjacent memory cells is ideally equal to less than 8F2, where “F” is no greater than 0.

Abstract: The present invention provides a method of forming a doped region with a DDD on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a pad oxide layer, and a silicon nitride layer that is used to define an active area. A lithographic process is performed to define a position of the DDD. Then a first ion implantation process is performed to implant a specific dosage of dopants into the silicon substrate. The photoresist layer is then removed completely. A thermal oxidation process is performed to form a field oxide layer in the region not covered by the silicon nitride layer, and to simultaneously drive the dopants into the silicon substrate so as to form a doped region. The silicon nitride layer and the pad oxide layer are removed. Then a poly gate and a spacer are formed. A second ion implantation process is performed to implant ions into the silicon substrate so as to form the doped region with a DDD structure in the N-type MOS transistor.

Abstract: Source and drain regions of field effect transistors are fabricated with an electrically insulating layer formed thereunder so as to reduce junction capacitance between each and a semiconductor body in which the regions are formed. Shallow trench isolation partially surrounds each transistor so as to further electrically isolate the source and drain regions from the semiconductor body. Typically for a single transistor only one surface of each drain and source region make direct contact to the semiconductor body and these surfaces are on opposite sides of a channel region of each transistor. One method of fabrication of the source and drain regions is to form an isolating isolation region around active areas in which a transistor is to be formed in a semiconductor body. Trenches separated by portions of the body are then formed in the active areas in which transistors are to be formed. On bottom surfaces of the trenches are formed an electrically insulating layer.

Abstract: A method for fabricating a high voltage transistor includes the steps of: forming a plurality of drift regions on a semiconductor substrate of a first conductive type; implanting drift ions of a second conductive type into surfaces of the drift regions of the semiconductor substrate at a first depth; implanting drift ions of the second conductive type into the surfaces of the drift regions of the semiconductor substrate at a second depth deeper than the first depth; implanting first conductive channel stop ions into the semiconductor substrate thereby forming a space between the semiconductor substrate and the drift regions; forming a device isolation film on a surface of the semiconductor substrate into which the channel stop ions are implanted; forming a gate electrode by inserting a gate insulating film on the semiconductor substrate between the drift regions; and forming a source/drain impurity diffusion region of a second conductive type in the surface of the semiconductor substrate at both sides of the

Abstract: On the surface of a field oxide film (3 of FIG. 2e) formed-on a substrate region where the effective thickness in the vertical direction of a substrate is diminished due to the presence of a crystal defect (2 of FIG. 1a), the field oxide film is etched by a predetermined thickness until a recess (4 of FIG. 2f) ascribable to the presence of the defect is exposed (step of FIG. 2f). A new oxide film then is formed in an amount corresponding to the above-mentioned thickness on the field oxide film (step of FIG. 3g) to diminish the depth of the recess ascribable to the presence of the defect. To provide a semiconductor device in which leakage between elements can be eliminated with a thin LOCOS oxide film thickness remaining unchanged.

Abstract: A method for embedded flash cell fabrication beyond 0.35 &Xgr;m generation. First, a relatively thick field oxide layer is formed on the P-type substrate to separate the flash cell areas and logic cell area. The flash cell areas are divided into tunnel oxide window and capacitor coupling area. Next, a conventional photolithogrpahy and etching method is used to formed a patterned photoresist on the substrate and expose flash cell areas. Then N-type conductive dopants are implanted into the substrate. For 0.35 &mgr;m generation, the concentration of dopant is increased to 5El7˜1El9 atoms/cm3. Next, the patterned photoresist layer are removed and thicker tunnel oxide and thinner gate oxide layer are formed in one processing step. Next, a doped polysilicon layer is deposited by using a conventional chemical vapor deposition over the tunnel oxide layer to serve as the floating gate of the flash cell.

Abstract: A method for manufacturing a nonvolatile memory device is provided. After forming an etching damage prevention layer on the entire surface of a stacked gate structure and on the entire surface of a semiconductor substrate, a self-aligned source etching process is performed. Thus, damage to side walls of the stacked gate structure and an active region can be prevented during the self-aligned source etching process.

Abstract: A method of forming integrated circuitry includes forming a field effect transistor gate over a substrate. The gate comprises semiconductive material conductively doped with a conductivity enhancing impurity of a first type and a conductive diffusion barrier layer to diffusion of first or second type conductivity enhancing impurity received thereover. An insulative layer is formed over the gate. An opening is formed into the insulative layer to a conductive portion of the gate. Semiconductive material conductively doped with a conductivity enhancing impurity of a second type is formed within the opening in electrical connection with the conductive portion, with the conductive diffusion barrier layer of the gate being received between the semiconductive material of the gate and the semiconductive material within the opening. Other aspects are disclosed and claimed.

Abstract: The present invention provides a method of forming a dual local oxidation structure (LOCOS) of a memory circuit in a semiconductor wafer. The semiconductor wafer comprises a silicon substrate and non-overlapping first and second areas defined on the surface of the silicon substrate. The first area is used for forming a memory array of the memory circuit and the second area is used for forming a peripheral circuit of the memory circuit for controlling the operation of the memory array. Using this method, a pad oxide layer and a silicon nitride layer are first formed on the silicon substrate. The silicon nitride layer has a plurality of recesses extending down to the surface of the silicon substrate. The widths of the recesses in the first area are narrower than the widths of the recesses in the second area. Then, a high temperature oxidation process is performed to form a field oxide layer on the surface of the silicon substrate within each of the recesses.

Abstract: A new method is established to form different silicide layers over the top of the gate electrode and the surface of the source/drain regions. A thin layer of TiSi2 is formed over the source/drain regions by depositing a layer of titanium and annealing this layer with the silicon substrate. The gate electrode is created as a recessed electrode, in the top recession of the electrode a layer of CoSi2 is formed by depositing a layer of cobalt over the gate electrode. This layer of COSi2 serves as the electrical gate contact point.

Abstract: In a method of manufacturing a semiconductor device, after performing ion-implantation and before forming an oxide film, a silicon substrate is disposed within a furnace to undergo a heat treatment at a temperature equal to or higher than 950° C. for a specific time period (equal to or longer than 15 minutes). When performing the heat treatment and when raising a temperature up to the heat treatment temperature, oxygen is supplied together with nitrogen gas (inert gas). A supply amount of oxygen is controlled to be equal to or less than 5% when raising the temperature up to the heat treatment temperature, and to be equal to or less than 2% when performing the heat treatment. After the heat treatment, the oxidation film is formed. As a result, crystal defects (OSFs) are prevented from being produced on the silicon substrate surface.

Abstract: The present invention is directed to a method of forming a transistor having very shallow junctions and a reduced channel length, and a transistor incorporating same. In general, the method comprises forming a first process layer above a semiconducting substrate, and forming a second process layer comprised of an oxidation resistant material above the first process layer. The method continues with the formation of an opening in the first and second process layers and oxidation of the substrate lying within the opening to form a third process layer. Next, a second opening is formed in the third process layer, and a plurality of sidewall spacers are formed in the second opening. The method concludes with the formation of a gate dielectric above the substrate and between the sidewall spacers, the formation of a gate conductor above the gate dielectric, and the formation of a plurality of source and drain regions in the substrate.

Abstract: A method of forming a semiconductor device includes forming a moat stack outwardly from a substrate, the moat stack comprising a dielectric pad disposed outwardly from the substrate, a silicon buffer structure disposed outwardly from the dielectric pad, and a protective dielectric cap disposed outwardly from the silicon buffer structure. The method further comprises forming a protective sidewall structure outwardly from at least a sidewall of the silicon buffer structure, forming an isolation dielectric region adjacent to the moat stack, after formation of the isolation dielectric region, removing the protective dielectric cap, and forming a conductive gate comprising the silicon buffer structure.

Abstract: A semiconductor device structure with differential field oxide thicknesses. A single field oxidation step produces a nitrided field oxide region (322) that is thinner than a non-nitrided field oxide region (324). The bird's beak (326) of the nitrided field oxide (322) encroaches less into the active cell region than the bird's beak (328) of the thicker non-nitrided field oxide (324). The differential field oxide thicknesses allow isolation of multi-voltage integrated circuit devices, such as flash memory devices, while increasing available active cell area for a given design rule.

Abstract: A method of fabricating a semiconductor device and the device which includes initially providing a layer of silicon having a thin oxide layer thereon and a patterned layer of a masking material not permeable to at least selected oxygen-bearing species and having a sidewall disposed over said oxide layer to provide an exposed intersection of the masking material and the oxide layer. An oxygen-bearing species conductive path is then formed on the sidewall of the masking material extending to the exposed intersection for conducting the selected oxygen-bearing species. A sidewall layer of a material different from the conductive path is formed on the conductive path. An oxygen-bearing species is then applied to the exposed intersection through the path and a thick oxide surrounding the masking material is fabricated concurrently or as a separate step. The masking material is preferably silicon nitride, the path is preferably silicon oxide and the sidewall layer is preferably silicon nitride.

Abstract: A method is described for manufacturing a high voltage mixed-mode device. The method comprises the steps of providing a substrate, wherein the substrate comprises an isolation region, a first active region and a second active region. A first oxide layer is formed on the first active region and the second active region, wherein the thickness of the first oxide layer on the second active region is thicker than that on the first active region. A first conductive layer is formed on the first oxide layer and the isolation region. A patterned second oxide layer is formed on the first conductive layer. A patterned second conductive layer is formed on the second oxide layer and the first conductive layer. The first conductive layer is patterned to form a low-voltage transistor gate on the first active region a high voltage transistor gate on the second active region and a capacitor on the isolation region.

Abstract: A method of making a semiconductor device such as a diode or MOSFET provided in a thin semiconductor film on a thin buried oxide is disclosed, in which the lateral semiconductor device structure includes at least two semiconductor regions separated by a lateral drift region. A top oxide insulating layer is provided over the thin semiconductor film and a conductive field plate is provided on the top oxide insulating layer. In order to provide enhanced device performance, a portion of the top oxide layer increases in thickness in a substantially continuous manner, while a portion of the lateral drift region beneath the top oxide layer decreases in thickness in a substantially continuous manner, both over a distance which is at least about a factor of five greater than the maximum thickness of the thin semiconductor film.

Abstract: A method of fabricating high density mask-type read only memory (ROM) devices that utilize a thick gate oxide to form non-programable cells and that can be easily integrated into standard CMOS manufacturing. The method includes forming a thick oxide over a semiconductor substrate, removing portions of the thick oxide layer, ion implanting dopants to form buried bit lines, patterning to form coding openings, forming a gate oxide within the coding openings, and forming a plurality of polysilicon gate electrodes constituting word lines of the mask ROM.

Abstract: When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.

Abstract: A nitride layer is deposited over a field oxide layer used to separate transistors formed in a substrate, the nitride layer serving to decrease transistor current leakage. The nitride layer has a dense lattice, effectively blocking H+ and Na+ penetration from overlying layers into the field oxide. Positive ions such as H+ and Na+ penetrating into the field oxide layer cause a p-substrate under the field oxide layer to become inverted or act like an n-type substrate, creating leakage current between source and drain regions of transistors which the field oxide layer separates. When high transistor threshold voltages such as 12 volts or more are desired, the nitride layer provides a significant reduction in current leakage.

Abstract: A method for fabricating a CMOS device on a SOI, comprising the steps of: providing a SOI wafer having a stack structure of a base substrate, a buried oxide layer and a semiconductor layer; forming a field oxide film in the semiconductor layer to define an active region in which a PMOS device and a NMOS device are to be formed in the semiconductor layer of the SOI wafer, wherein the field oxide film is formed by performing thermal oxidation process so as to apply a compressive stress to the semiconductor layer that the PMOS device is to be formed; and forming the PMOS device and NMOS device in the active region defined by the field oxide film.

Abstract: A method for making an integrated circuit includes the steps of forming a plurality of spaced apart isolation regions in a substrate to define active regions therebetween, forming a first mask, and using the first mask for performing at least one implant in the active regions for defining high voltage active regions for the high voltage transistors. The method further includes the steps of removing the first mask and forming a second mask, and using the second mask for performing only one implant for converting at least one high voltage active region into a low voltage active region for a low voltage transistor. All of the implants needed to define the high voltage transistors are first performed throughout the active regions using the first mask. A separate single implant is then performed using the second mask to convert at least one of the high voltage active regions to a low voltage active region.

Abstract: A method for forming spacers for preventing formation of parasitic corner devices in transistors includes etching trenches into a semiconductor substrate to form an active area region, lining the trenches and the active area region with a first dielectric material and forming shallow trench isolation regions adjacent to the active area region by filling the trenches with a second dielectric material. The first dielectric material is removed from the active area region, and a gate oxide is formed over the active area region wherein divots form between the active area region and the shallow trench isolation regions. Dopants are implanted into the active area region to form a source and drain of the transistor. After the step of implanting, a spacer layer formed from a third dielectric material is deposited over the gate oxide layer to fill the divots.

Abstract: A new method is provided for the formation of Lightly Doped Drain (LDD) regions in MOS devices. The body of the gate electrode is formed including the self-aligned LDD regions. After the LDD regions have been formed, an oxide implant is performed under an angle into the surface of the substrate on which the MOS device is being formed. This oxide implant forms an oxide layer around the interface between the source/drain regions and the surrounding silicon. The spacers for the gate electrode are formed, the source/drain region implant is completed. This implanted oxygen junction is subjected to a thermal treatment thereby forming an oxide layer around the source/drain regions. This oxide layer eliminates the leakage current across the interface between the source/drain regions and the surrounding silicon further forcing the saturation current between these regions to flow along the surface of the silicon substrate.

Abstract: A method of fabricating an integrated circuit on a wafer includes forming a gate electrode stack over a gate dielectric and forming nitride spacers along sidewalls of the gate electrode stack other than along lowermost portions of the sidewalls. Subsequently, a reoxidation process is performed with respect to the gate dielectric. By providing the nitride spacers along exposed surfaces of conductive barrier and metal layers of the word line stack, those surfaces can be passivated, thereby preventing or reducing the conversion of those layers to non-conductive compounds during the reoxidation process. At the same time, the nitride spacers can be formed so that they do not interfere with the subsequent reoxidation of the gate dielectric. An integrated circuit having a gate electrode stack with nitride spacers extending along sidewalls of the gate electrode stack other than along lowermost portions of the sidewalls is also disclosed.