Abstract: A semiconductor device having a thin film resistor which comprises at least chromium, silicon and nitrogen, and formed on a substrate with having a special ratio of the chemical composition, the semiconductor device having a characteristic such that variations of the resistance value thereof due to temperature variations can be effectively suppressed.

Abstract: A process is revealed whereby resistors can be manufactured integral with the printed circuit board by plating the resistors onto the insulative substrate. Uniformization of the insulative substrate through etching and oxidation of the plated resistor are revealed as techniques for improving the uniformity and consistency of the plated resistors.

Abstract: After an insulating layer made of BPSG is formed on a diffusion layer, a contact hole is formed to expose the diffusion layer. Then, a first aluminum layer is formed in the contact hole. Then, first and second TEOS layers are formed. Thereafter, a thin film resistor is formed on the second TEOS layer by photo-lithography and etching treatments. In this process, the other parts are covered with the second TEOS layer to prevent being damaged. As a result, occurrence of a leak current at the diffusion layer and the like can be prevented. Further, a third TEOS layer is formed on the thin film resistor, and then a second aluminum layer is formed to be electrically connected to the thin film resistor through a contact hole by an ECR dry etching treatment. In this etching treatment, the thin film resistor is not damaged due to the third TEOS layer.

Abstract: The present invention relates, in one embodiment, to an integrated circuit including a first circuit structure, a first conductive bonding pad coupled to the first circuit structure, a second circuit structure, and a second conductive bonding pad coupled to the second circuit structure. The first conductive bonding pad is arranged to be separated from the second bonding pad by a gap having a gap dimension. The gap dimension is configured to be bridged by a wire bond, thereby permitting the wire bond to electrically couple the first conductive bonding pad with the second conductive bonding pad when the wire bond is coupled to the first bonding pad and the second bonding pad at the gap.

Abstract: A method of forming an integrated circuit device including at least one polysilicon resistor 10 is disclosed herein. A polysilicon layer 24 is formed, possibly over a field oxide 12. The polysilicon layer 24 is then doped to achieve a selected sheet resistance. An insulating layer 18 (e.g., an oxide, a nitride, or a combination thereof) is then formed over the polysilicon layer 24. The insulating layer 18 is patterned and etched to define a resistor body 14 in the underlying polysilicon layer 24. The polysilicon layer 24 is then patterned and etched to define first and second resistor heads 16 abutting the resistor body 14 while simultaneously at least one polysilicon element 28 of a second electronic device is formed. Other systems and methods are also disclosed.

Abstract: A method of fabricating a load resistor for an SRAM. A substrate has a polysilicon layer formed thereon through a buried contact process. An inter-layer dielectric layer is formed over the substrate and then patterned to form an opening that exposes the polysilicon layer. A poly via is then formed in the opening to serve as a load resistor. The inter-layer dielectric layer is patterned to form a contact window, which is then filled with a conductive layer to form a contact.

Abstract: A method of manufacturing a on-chip temperature controller by co-implanting P-type and N-type ions into poly load resistors. The N and P type implant dose can be selected to create the desired cut-off temperature. First, a polysilicon layer 30 is formed on a first insulation layer 20. The polysilicon layer 30 is patterning to form a first poly-load resistor 30A and a second poly-load resistor 30B. The first and the second poly-load resistors are connected to a temperature sensor circuit 12. Both p-type and n-type impurity ions are implanted into the polysilicon layer 30. An insulating dielectric layer 40 is formed over the polysilicon layer 30 and the first insulating layer 20. The polysilicon layer is annealed. The contact openings 44 are formed through the ILD dielectric layer 40 exposing portions of the polysilicon layer 30. Contacts 50 to the polysilicon layer 30 thereby forming a first and second poly-load resistors which are used a temperature on-chip sensors.

Abstract: A semiconductor device, in a circuit configuration on a semiconductor substrate, is disclosed which comprises: a boosting circuit for boosting an external power supply voltage to a plus voltage and a minus voltage; and a detecting circuit having a resistor formed of an impurity diffused layer so that the plus voltage and the minus voltage boosted by the boosting circuit is connected to the resistor, respectively to detect a potential at a prescribed point so as to verify if or not the boosting circuit has generated a desired potential.

Abstract: A semiconductor device is disclosed including a first insulating film having a contact hole and being formed on a substrate. A first impurity region is formed in the active layer on the bottom of the contact hole, and a second impurity region is formed in the active layer on the first insulating film outside the contact hole. In addition, a semiconductor region is formed in the active layer on the sidewall of the contact hole, and a second insulating film is formed on the first impurity region in the contact hole. A gate electrode is formed on the second insulating film.

Abstract: An SRAM semiconductor device is disclosed in which an access transistor is an nMOS TFT to thereby reduce cell size and to improve low Vcc characteristics. The semiconductor device comprises a gate electrode of a drive transistor formed on the semiconductor substrate, with a first gate insulating film therebetween. A first impurity region is formed on the substrate on opposite sides of the gate electrode of the drive transistor. An insulating film is formed on the entire surface of the substrate and has a contact hole exposing part of the gate electrode of the drive transistor. A semiconductor layer is formed on the insulating film in connection with the gate electrode of the drive transistor through the contact hole; a second gate insulating film is formed on the semiconductor layer; and a gate electrode of an access transistor is formed on the second gate insulating film. Further, a second impurity region is formed in the semiconductor layer on opposite sides of the access transistor gate electrode.

Abstract: A new method of forming a polysilicon resistor having precisely controlled resistance by using a thin silicon nitride cap over the polysilicon resistor is described. A dielectric layer is provided on a semiconductor substrate. A polysilicon layer is deposited overlying the dielectric layer and patterned to form a polysilicon resistor. A silicon nitride capping layer having a thickness of not more than 100 Angstroms is deposited overlying the polysilicon resistor and dielectric layer. An interlevel dielectric layer is deposited overlying the silicon nitride capping layer. The substrate is annealed thereby densifying the silicon nitride capping layer. A self-aligned contact opening may be made through the interlevel dielectric layer, the silicon nitride capping layer, and the dielectric layer to underlying device structures. The capping silicon nitride layer is thin enough not to act as an etch stop in the self-aligned contact etching. The contact opening is filled with a conducting layer.

Abstract: A method for manufacturing a nonvolatile memory device is provided. A first conductive layer is formed on a semiconductor substrate. The first conductive layer is patterned such that an isolated resistor pattern is formed on a predetermined region of a peripheral circuit region. A dielectric layer and a second conductive layer are sequentially formed on the semiconductor substrate. The second conductive layer is patterned to form a second conductive layer pattern exposing the entire dielectric layer of a resistor region in the peripheral circuit region and a predetermined region of the dielectric layer of a MOS transistor region. The second conductive layer pattern, the dielectric layer, and the first conductive layer pattern are sequentially patterned to simultaneously form a gate pattern of a cell transistor and a gate pattern of the MOS transistor. The gate pattern of the MOS transistor includes a predetermined region of the dielectric layer exposed during forming of the second conductive layer pattern.

Abstract: A method of fabricating thin film transistor. A thin oxide layer is formed as a protection layer for a thin film transistor. Since the oxide layer does not affect the fabrication process of a barrier layer, the thin oxide layer can be formed as the protection layer to protect the thin-film resist layer formed subsequently from being damaged by ions produced during dry etching process.

Abstract: The present invention provides a method of forming a thin-film resistor with a stable electric resistance on a dielectric layer of a semiconductor wafer. The method involves: 1. forming a resistance layer and a protective layer in a predetermined area of the dielectric layer, the protective layer being positioned on the resistance layer, 2. forming an insulating layer on the upper and side surfaces of the protective layer and the side surface of the resistance layer in the predetermined area, and on the surface of the dielectric layer outside the predetermined area, 3. performing a dry-etching process on the insulating layer within the predetermined area to form two openings extending down to the protective layer, the protective layer being used for preventing the resistance layer from plasma damage caused by the dry-etching process, 4. performing a wet-etching process on the protective layer through the two openings of the insulating layer to form two openings extending down to the resistance layer, 5.

Abstract: In a method for manufacturing a semiconductor device having a mixture of a MOSFET and a low-resistance resistive element, after etching a tungsten silicide film which will serve as the resistive element to achieve a prescribed shape, thermal processing is performed for the purpose of activating a diffusion layer of the MOSFET, thereby achieving a low-resistance tungsten silicide film.

Abstract: A method of providing a semiconductor device with a selectively deposited inorganic electrically insulative layer, the device having exposed semiconductor surfaces and electrically conductive metal end terminations, in which the device is saturated in a phosphoric acid solution to form a phosphate layer on the exposed surfaces of the semiconductor but not on the metal end terminations. The device is thereafter plated by a conventional plating process and the plating is provided only on the end terminations.

Abstract: A method for forming a thin-film resistor, which is composed of silicon, carbon, and chromium, is disclosed. The resistivity of the thin-film resistor, and therefore the resistance and temperature coefficient of resistance (TCR) of the resistor, are tailored to have specific values by varying the elemental composition of the silicon, carbon, and chromium used to form the resistor.

Abstract: A new method of forming polysilicon resistors having differing resistances using a dual polysilicon process is described. A first polysilicon layer is deposited over a dielectric layer on a semiconductor substrate. The first polysilicon layer is etched away where it is not covered by a mask. Thereafter, a second polysilicon layer is deposited overlying the first polysilicon layer and the dielectric layer. The first and second polysilicon layers are patterned to form a first polysilicon structure comprising the first and second polysilicon layers over the dielectric layer and a second polysilicon structure comprising the second polysilicon layer overlying the dielectric layer. The first and second polysilicon structures are doped to form the first polysilicon structure having a first resistance and the second polysilicon structure having a second resistance wherein the first resistance is lower than the second resistance.

Abstract: The present invention provides a thin-film resistor positioned on a semiconductor wafer and its method of formation. The thin-film resistor comprises a dielectric layer, a resistance layer, a protective layer, an insulating layer and two conductive layers. The dielectric layer is positioned on the semiconductor wafer. The resistance layer is positioned in a predetermined area of the dielectric layer. The protective layer positioned on the resistance layer comprises two openings formed above two ends of the resistance layer by using the wet-etching process. The insulating layer positioned on the protective layer comprises two openings on the two openings of the protective layer by using the dry-etching process. The two conductive layers are separately positioned in the two openings of the protective layer and the insulating layer to connect two ends of the resistance layer and function as two electrical terminals.

Abstract: The present invention provides stable and reliable extremely high resistance polysilicon resistors for use as SRAM load elements, and methods for their fabrication. In an embodiment, a resistor element of a semiconductor device includes at least one polysilicon layer, and a silicon nitride layer deposited directly onto this polysilicon layer. The silicon nitride layer prevents contamination of the polysilicon layer during subsequent fabrication process steps. A method of fabricating a polysilicon resistor on a semiconductor substrate is also provided. The method includes the step of depositing a layer of polysilicon on the substrate, followed by depositing a layer of protective material over the polysilicon layer to form a protected polysilicon layer. After deposition of the protective layer, resistors are formed by implanting dopants into the polysilicon layer, and patterning through lithography, and etching the nitride and the polysilicon layer.

Abstract: In a method of manufacturing a semiconductor device, a polysilicon resistance film is directly or indirectly formed on a semiconductor substrate. A first insulating film is formed on the polysilicon resistance film, and a second insulating film is formed on the first insulating film. An opening portion is formed to pass through the first insulating film and the second insulating film to expose the polysilicon resistance film. The first insulating film has an etching rate equal to or smaller than ⅛ of an etching rate of the second insulating film.

Abstract: A process for increasing the sheet resistance and lowering the temperature coefficient of resistance of a thin film resistor deposited on a wafer, the process comprising ramping the temperature of the wafer to an annealing temperature above the decomposition temperature of the thin film resistor using a radiant heat source such that the wafer reaches the annealing temperature within a ramp up time of from about 5 to 10 seconds, and annealing the wafer at the annealing temperature for an annealing period of from about 50 to 85 seconds.

Abstract: A stable, high-value polysilicon resistor is achieved by using a silicide layer that prevents diffusion of hydrogen into the resistor. The resistor can also be integrated into a salicide process for making FETs without increasing process complexity. A polysilicon layer with a cap oxide is patterned to form FET gate electrodes and the polysilicon resistor. The lightly doped source/drains, insulating sidewall spacers, and source/drain contacts are formed for the FETs. The cap oxide is patterned to expose one end of the resistor, and the cap oxide is removed from the gate electrodes. A refractory metal is deposited and annealed to form the salicide FETs and concurrently to form a silicide on the end of the resistor. The unreacted metal is etched. An interlevel dielectric layer is deposited and contact holes with metal plugs are formed to both ends of the resistor. A metal is deposited to form the first level of metal interconnections, which also provides contacts to both ends of the resistor.

Abstract: After a CrSiN film and a TiW film are formed on a substrate through an intermediate insulating layer, a mask pattern is formed on the TiW film. Then a two-step dry etching treatment is performed to etch the TiW film and the CrSiN film into a specific shape. Specifically, first the TiW film is selectively etched under conditions including a large content of fluorine radicals. Then the CrSiN film is selectively etched under conditions including a large content of oxygen radicals. Accordingly, a thin film resistor can be formed with high accuracy with respect to the mask pattern.

Abstract: An integrated circuit structure comprises a conductor film that serves as a passive element or an interconnection, and a silicon substrate. A cavity is disposed between the substrate and the conductor film and thus underneath the conductor film. The substrate is formed by forming an island of oxide film in a surface of the substrate, and then wet etching the island from the surface of the substrate thereby forming the cavity.

Abstract: A silicon nitride layer on a ground wire is used for an etching stopping layer so as to form a trench, after which a high-resistance load element is formed so as to extend the length of the resistance by the amount of the step of the trench, and by forming the high-resistance load element in two layers, the resistance length is made large.

Abstract: A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars.

Abstract: Provided is a high resistance value vertically-integrated semiconductor interconnect, and a process to make such highly resistive interconnects together with low resistive interconnects in a precisely controllable manner. In addition, provided is an SRAM cell with highly resistive contact processing for a pull-up resistor.

Abstract: An integrated circuit resistor (18) has a layout in which a first parasitic capacitance (26) exists between first portions of the resistor (18) and a first integrated circuit feature (34), and a second parasitic capacitance (28) exists between second portions of the resistor and a second integrated circuit feature (32). The resistor (18) may have, for example, a zigzag or serpentine configuration, with portions of each leg of the zigzag configuration overlying the first and second integrated circuit features (34,32). The first and second integrated circuit features (34,32) are configured to produce substantially canceling charges on the first and second parasitic capacitances (26,28). The resistor may be defined by a doped semiconductor material, such as a polysilicon layer. The resistor may be used in many applications, such as a feedback resistor of an optoelectronic current-to-voltage converter (12).

Abstract: An integrated circuit inverted thin film resistor structure and method of manufacture having interconnect defining resistor contacts and leads resident within and coplanar with a supporting layer, resistive material uniformly overlaying the supporting layer and contacts, the resistive material diffused into the resistor/interconnect contact region.

Abstract: A method of making a self-aligned, integrated resistor load on ultrathin silicon on sapphire film, with the method being used to manufacture an FET and a resistor load. While the film can be used, for example, to manufacture a four transistor SRAM, it is not limited to such applications. The method encompasses an integral resistor load which can be integrated with analog components or formed as part of an integrated circuit for electrostatic discharge (ESD) circuitry, or the like. The resistor load can be integrally formed from the same silicon island which forms a corresponding transistor. Because the resistor load can be made from, and integral with, the ultra thin silicon material, it can be automatically self-aligned to the transistor. The self-aligned, integrated resistor loads are comprised of an insulating substrate, with a layer of silicon formed on the insulating substrate.

Abstract: An SRAM cell and method for fabricating the same including first and second access transistors, first and second drive transistors, and first and second load resistors. A first terminal of the first access transistor, a gate terminal of the second drive transistor, and a first load resistor terminal are connected to one another to form a first cell node terminal. A first terminal of the second access transistor, a gate terminal of the first drive transistor, and a second load resistor terminal are connected to one another to form a second cell node terminal. The SRAM cell includes a gate electrode of each of the first and second drive transistors arranged over a semiconductor substrate in a first direction, and a gate electrode of each of the first and second access transistors arranged in the first direction overlapped with portions of the gate electrodes of the first and second drive transistors.

Abstract: The present invention provides a method of inter-poly oxide (IPO) layer underlying a polysilicon resistor in a memory product. The IPO layer 15 is formed by a modified low pressure SACVD-O.sub.3 -TEOS process that gives the IPO layer a smoother surface and good planarization. This IPO layer gives the overlying polysilicon resistors a more uniform resistance. The method begins by providing a semiconductor structure 10. Next, in an important step, an inter-poly oxide (IPO) layer 11 is formed using low pressure ozone assisted sub-atmospheric chemical vapor deposition (SACVD O.sub.3 -TEOS) process at a pressure between about 20 and 150 torr. A polysilicon resistor 15 is then formed on said inter-poly oxide (IPO) layer. The memory device is completed by forming passivation and conductive layers thereover.

Abstract: The present invention is a method for preventing backside polysilicon peeling in 4T+2R SRAM process. This invention utilizes forming oxide cap layer on the backside of the wafer to protect the backside polysilicon. Thus, the backside polysilicon is free from peeling and damage.

Abstract: The present invention provides a new method for making a load resistor in a semiconductor chip. According to the new method, a linear-shaped doped polysilicon layer is formed onto the surface of the semiconductor chip that comprises a Si substrate and an NSG layer. This layer functions as a conductive path. A slot is formed in this layer by removing a section from the conductive path. This slot reaches down to the NSG layer effectively cutting off the polysilicon layer. Then, a rugged polysilicon layer is evenly deposited onto the surface of the slot for connection of the conductive path. The polysilicon layer over the slot and the doped polysilicon layer defines the load resistor. The result is a high resistance value with usage of only a small space.

Abstract: In a method of manufacturing a static memory device, a patterning process is performed to a lamination film composed of a first insulating layer, a first conductive layer, a second insulating layer and a second conductive layer with regions for load resistors. A lamination section of the first insulating layer and the first conductive layer are separated through the first and second patterning processes into first to fourth portions. The first and second portions respectively functioning as parts of the word line which are connected to each other and as the gates of the transfer MOS transistors, and the third and fourth portions respectively functioning as gates of the drive MOS transistors. The second conductive layer is separated through the second patterning process into fifth and sixth portions, and the fifth and sixth portions respectively functioning as parts of the power supply line which are connected to each other and as the load resistors connected to the parts of the power supply line.

Abstract: Even when a contact hole is formed before thin-film resistor formation, a contact area exposed in the contact hole is prevented from damaging. A semiconductor element is formed in a silicon semiconductor substrate and an oxide film is formed on the surface of the semiconductor substrate. Then, a contact hole is formed on the oxide film and moreover, a CrSiN film serving as a thin-film resistor and a TiW film serving as a barrier metal are formed on the oxide film. The TiW film is patterned by a mask and the CrSiN film is patterned through chemical dry etching. Finally, an Al electrode is formed on the semiconductor element and the CrSiN film through the contact hole and moreover a protective film is formed thereon.

Abstract: The present invention is related to a high load resistance (HLR) type static random access memory (SRAM) which is small enough to have a profit in device integration. The present invention also provides an SRAM cell, which is easy to convert the thin film transistor (TFT) type SRAM cell into the HLR type SRAM as occasion calls. A high load resistance type static random access memory cell according to the present invention has four polysilicon layers and two metal lines, this is similar to a conventional TFT type SRAM cell. One layer of the four polysilicon layers is used for a high load resistance element and a power line according to the amount of the impurity implanted in the polysilicon layer.

Abstract: An integrated circuit, including a resistor having multiple, series-connected resistor segments formed over multiple tubs of semiconductor material of a first polarity in a semiconductor substrate of the opposite polarity. The resistor is implemented with multiple bootstrapping in the sense that all tubs are coupled to a node of the circuit whose potential changes, in response to a changing input signal, in a direction so as to pull the potential at one end of the resistor in a desired direction. Each resistor segment can be formed over a different one of the tubs, or there are more segments than tubs (e.g., more than one segment formed over one of the tubs or at least one segment having no tub under it). In preferred embodiments, the circuit is a high-speed cascode amplifier (or other amplifier), the resistor is a gain-setting resistor coupled to the top rail, and the tubs are coupled to the amplifier's output.

Abstract: FIG. 5b shows a first thin film resistor 14 formed by direct etching or lift off on a first dielectric layer 12 that covers an integrated circuit (not shown) in a silicon substrate 10. A patterned layer of photoresist covers a portion of the second thin film resistor material 30. The second thin film resistor material 30 is different from the first thin film resistor material 14. The exposed portion of the second thin film resistor material 30 is removed to leave first and second thin film resistors on the first dielectric layer 12.

Abstract: The present invention provides a structure and method of forming a butting contact having protective spacers 50A that prevent shorting between a second polysilicon layer 60 and the substrate in a hole 20A in a isolation region 20. The following are provide: a isolation region 20, a first conductive line 30B over portions of the isolation region 20, and an inter-poly insulating layer 40. The protective spacers prevent shorts when the first conductive line 30B is misaligned and exposes a first portion of the isolation region 20 in a butt contact opening. A first photoresist layer 44 having a butt contact photoresist opening 44A over the first doped region 26 and over a first portion of the isolation is formed. The inter-poly insulating layer 40 is etched through the butt contact photoresist opening 44A and etches the first portion of the isolation region forming an isolation hole 20A. In an important step, protective spacers 50A are formed on the sidewalls of the isolation hole 20A.

Abstract: An EEPROM semiconductor structure is produced with a resistor, a thin-film transistor, a capacitor, and a transistor. The individual implantation steps are utilized to create various structures and, as a result, the production process is substantially simplified.

Abstract: High-resistance polysilicon layers applied in 4T SRAM memory cells serving as loads, are manufactured by a simple method according to the invention. In the small-scale 4T SRAM memory cell process, it is not possible to fabricate traditional polysilicon loads manufactured by the prior art with a desired high degree of resistance. As a result, the miniaturization of 4T SRAM memory cells has been limited. However, in the method according to the invention, the lengths of polysilicon loads are greatly increased without increasing the sizes of corresponding memory cells, thereby efficiently increasing the resistance of the polysilicon loads. Therefore, this method according to invention can completely eliminate any limitation to the small-scale 4T SRAM memory cell process caused by the manufacture of the polysilicon loads as described above.

Abstract: A method of manufacturing a semiconductor device by forming first and second resistor layers of polycrystalline silicon including impurities on a first insulation film with a predetermined distance therebetween. The resistor layer have a resistance ratio set to a predetermined value. A second insulation film is formed on the first and second resistor layers and has an opening in a predetermined region. A metal layer electrically connected to the first and second resistor layers is formed in the opening and extends onto the second insulation film. The metal layer is patterned to form a first metal interconnection layer electrically connected to the first resistor layer and a second metal interconnection layer electrically connected to the second resistor layer. The first metal interconnection layer partially covers the first resistor layer. The second metal interconnection layer partially covers the second resistor layer.

Abstract: After the formation of a gate oxide layer, a polysilicon layer is formed right away. The polysilicon layer is used for patterning the gate oxide layer. The photolithography and etching processes of forming the buried contact window are combined with the step of removing the gate oxide layer at the periphery circuit region. Then, after the formation of the gate oxide layer at the memory cell region, one thermal oxidation process is performed to form the gate oxide layer at the periphery circuit region.

Abstract: A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars.

Abstract: According to the preferred embodiment of the present invention, an improved resistor and method of fabrication is provided. The method for fabricating a resistive element into an integrated circuit semiconductor device comprises the steps of: depositing a dielectric film, such as silicon nitride; depositing a titanium film upon the dielectric film; and annealing the titanium and dielectric films. This causes titanium to be diffused into the dielectric film. This creates a resistive element having a relatively high resistivity. The preferred embodiment method has the advantage of being easily integrated into conventional integrated circuit fabrication techniques.

Abstract: The inventive SRAM cell has a poly-load resistor which comprises a thick supply voltage (Vcc) interconnect, a thick driver interconnect on a thin load resistance region which is electrically connected to both interconnects. The novel poly-load resistor overcomes the problem of lateral diffusion from the interconnect regions into the load region. The resulting SRAM cell has a low Vcc interconnect resistance.

Abstract: The device hereof provides an integrated circuit resistor (34) comprising amorphous or noncrystalline semiconducting material. Further advantages can be gained in area by forming the noncrystalline semiconductor resistor in a non-planar fashion (i. e. with a vertical construction) wherein a first electrical contact is made to the resistor on its bottom surface and a second electrical contact is made to the resistor on its top surface.Other devices, systems and methods are also disclosed.

Abstract: A method of forming an SRAM transistor cell on a doped semiconductor substrate with a halo region in transistors thereof by the steps including well formation, field isolation formation, threshold voltage implant, gate oxidation; deposition of polysilicon and patterning thereof into gate electrode; post etching anneal; N type LDD photolithography and ion implanting NMOS transistor devices; ion implant halo regions in a transistor; P type LDD photolithography and ion implanting PMOS transistor devices; spacer formation; N+ source/drain photolithography and ion implanting; and P+ source/drain photolithography and ion implanting.