Abstract: A method for making a thin film device on integrated circuits including the steps of applying a first photoresist layer to a first surface, and patterning the first photoresist layer to have at least a first opening that exposes the first surface. A film is deposited onto the first photoresist layer, wherein a portion of the deposited film is deposited onto the exposed first surface. A second photoresist layer is applied onto the deposited layer, wherein the second photoresist layer is applied to the portion of the deposited film within the first opening and covers a second portion of the deposited layer, wherein the first photoresist layer and the second photoresist layer assist in the defining of the deposited layer. The deposited layer, first photoresist layer, and second photoresist layer are selectively removed, therein exposing the first surface and the second portion of the deposited layer.

Abstract: The invention relates to a semiconductor component with a WSiN layer as thin-film resistor with high temperature coefficient for use as thermistor in bolometers. The production method comprises thermal decoupling by means of thermistors that are free-standing or disposed on an insulation layer.

Abstract: A method is provided of forming a low resistance contact between a poly-silicon resistor of an integrated circuit and a conducting material, the method comprising the steps of: a) covering the resistor with an insulating layer; b) etching at least one contact opening in the insulating layer; c) cleaning the insulating layer to remove any residues from the etching process; d) applying phosphoric acid; and e) depositing a conducting layer which forms an electrical contact with said resistor.

Abstract: A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the oxide film is formed by a plasma CVD process with a reduced plasma power such that the H2O content in the oxide film is less than about 2.4 wt %.

Abstract: The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor device. The resistor includes first and second crystalline layers which may or may not differ from one another. One of the first and second crystalline layers comprises doped silicon/germanium, and the other comprises doped silicon. The transistor device and resistor can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). The invention also includes processes of forming semiconductor constructions, and in particular aspects, includes processes of forming resistor constructions.

Abstract: In a method for fabricating a thin film transistor array substrate, a glass substrate undergoes an oxygen plasma treatment. A silver or silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a gate line assembly proceeding in the horizontal direction. The gate line assembly includes gate lines, gate electrodes, and gate pads. Thereafter, a silicon nitride-based gate insulating layer is deposited onto the substrate, and a semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. The semiconductor layer and the ohmic contact layer are HF-treated. A silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a data line assembly. The data line assembly includes data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads.

Abstract: The thin film transistor formed of polycrystalline silicon is positioned adjacent a heat reaction chamber. The gate electrode for the transistor is formed within a silicon substrate and a gate dielectric is positioned over the gate electrode. A pass transistor is coupled to the gate electrode, the pass transistor having a source/drain region in the same semiconductor substrate and positioned adjacent to the gate electrode of the thin film heating transistor. When the pass transistor is enabled, a voltage is applied to the gate electrode which causes the current to flow from the drain to the source of the thin film transistor. The current flow passes through a highly resistive region which generates heat that is transmitted to the heat reaction chamber.

Abstract: An a-Si film is patterned into a linear shape (ribbon shape) or island shape on a glass substrate. The upper surface of the a-Si film or the lower surface of the glass substrate is irradiated and scanned with an energy beam output continuously along the time axis from a CW laser in a direction indicated by an arrow, thereby crystallizing the a-Si film. This implements a TFT in which the transistor characteristics of the TFT are made uniform at high level, and the mobility is high particularly in a peripheral circuit region to enable high-speed driving in applications to a system-on glass and the like.

Abstract: An a-Si film (12) formed on an insulating substrate (10) is irradiated with a laser so that the a-Si film (12) is fused and recrystallized to form a p-Si film (13). Projections (100) generated on the p-Si film (13) at this stage are eliminated by irradiation of ion beams at the incident angle of 60° to 90° using an ion milling method to planarize the surface of the p-Si film (13), thereby creating sufficient insulation between the p-Si film (13) and gate electrodes (15).

Abstract: Low cross talk resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises a bit formed using a perovskite material interposed at a cross point of an upper electrode and lower electrode. Each bit has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit, decrease the resistivity of the bit, or determine the resistivity of the bit. Memory circuits are provided to aid in the programming and read out of the bit region.

Abstract: A photoresist (6) is formed on an element isolation insulating film (2) so as to cover the upper and side surfaces of a polysilicon film (4R) which functions as a resistance element. With the photoresist (6) as an implantation mask, n-type impurities (7) such as phosphorus are ion-implanted from a direction substantially normal to the upper surface of a silicon substrate (1). The dose is in the order of 1013/cm2. Through this processing, an LDD region (8) of MOSFET is formed inside the upper surface of the silicon substrate (1) within a transistor forming region. The impurities (7) are also implanted in a polysilicon film (4G). On the other hand, as the polysilicon film (4R) is covered by the photoresist (6), the impurities (7) are not implanted into the polysilicon film (4R).

Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

Abstract: A thin film resistor that has a substantially zero TCR is provided as well as a method for fabricating the same. The thin film resistor includes at least two resistor materials located over one another. Each resistor material has a different temperature coefficient of resistivity such that the effective temperature coefficient of resistivity of the thin film resistor is substantially 0 ppm/° C. The thin film resistor may be integrated into a interconnect structure or it may be integrated with a metal-insulator-metal capacitor (MIMCAP).

Abstract: A semiconductor device and a method of making a semiconductor device. A damascene metal layer (16) is formed in an insulating dielectric layer (12), which is in direct electrical communication with a substrate (10). A layer of a passive element, such as first capacitor electrode layer (20) is disposed on metal layer (16) and preferably is offset relative to metal layer (16) to allow a direct electrical interconnect through a via (36) to metal layer (16). In one embodiment a capacitor and a resistor are formed as passive elements in the device. In another embodiment, the passive element includes at least one resistor (28) and optionally a second resistor (32). In yet another embodiment, metal layer (16) is a damascene copper layer.

Abstract: A semiconductor memory device and a method of manufacturing same, wherein landing pads are formed to contact source/drain regions of an access transistor in a memory cell array area and a first resistor device is formed in the peripheral circuit area, by depositing a first conductive layer on a semiconductor substrate having an access transistor formed thereon and patterning the first conductive layer. An interlayer insulation layer is deposited on the resultant structure, and a lower electrode and a dielectric layer having a high dielectric constant of a capacitor are formed to contact the source/drain region of the access transistor. By depositing a second conductive layer on the resultant structure having the dielectric layer and patterning the dielectric layer, a capacitor upper electrode is formed in the memory cell array area and a second resistor device is formed in the peripheral circuit area.

Abstract: A resistive structure formed overlying a semiconductor substrate is masked with a silicide block layer to define a portion of the resistive structure that is to be unsilicided and a portion of the resistive structure to be silicided. The silicide block layer is changed to facilitate different processes.

Abstract: A semiconductor manufacturing apparatus emits an energy beam for crystallizing a semiconductor film formed on a substrate. The apparatus can output a plurality of energy beams continuously in relation to time and move the energy beams to scan a target to be irradiated. The output instability of the energy beam is smaller than ±1%/h. The noise (optical noise) indicating the instability of the energy beam can be not more than 0.1 rms %.

Abstract: The invention is to obtain a resistor element having high resistance, a low temperature coefficient, and high uniformity of sheet resistance in a wafer. A field oxide film is formed on a semiconductor substrate. On the field oxide film a non-doped silicon film is formed by a LPCVD method. The silicon film is made of an amorphous silicon film or a polysilicon film. BF2+ is ion implanted in this silicon film. Then, either before or after this ion implantation, N2 annealing is performed at low temperature between 650 and 750° C.

Abstract: The present invention describes a method of forming a thin film on a substrate arranged in a deposition system comprising the step of introducing a pre-determined amount of an impurity in a confined volume in the deposition system. One or more gases are introduced into the deposition system for forming the thin film. The impurity is removed from the confined volume in a gas phase during formation of the thin film. The impurity in the gas phase is incorporated into the thin film.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filed with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The structure of a semiconductor device includes gate electrodes having a T-shaped structure comprised of first and second gate electrodes having low gate resistance and low parasitic capacitance and a halo ion-implanted region in which a short channel effect can be effectively suppressed. The method for manufacturing the device is capable of performing high angle ion implantation without extending gate-to-gate space.

Abstract: A method of fabricating a thin film transistor, includes the steps of (a) forming a gate electrode on an electrically insulating substrate, (b) forming a gate insulating film on the electrically insulating substrate, covering the gate electrode therewith, (c) forming a semiconductor layer on the gate insulating film above the gate electrode, (d) forming source and drain electrodes both making electrical contact with the semiconductor layer, (e) patterning the semiconductor layer into a channel, (f) applying first plasma to the semiconductor layer through the use of a first gas, and (g) applying second plasma to the semiconductor layer through the use of a second gas, and (h) forming an electrically insulating film covering the semiconductor layer therewith.

Abstract: The present invention provides a method for fabricating a capacitor constituted with double hafnium oxide layers through a plasma enhanced chemical vapor deposition (PECVD) process and a low pressure chemical vapor deposition (LPCVD) process. The method for fabricating the capacitor constituted with the double hafnium oxide layers includes: forming a lower electrode layer over a semiconductor substrate; performing a heat treatment with the lower electrode; forming a first HfO2 layer over the first HfO2 layer by using a plasma enhanced chemical vapor deposition (PECVD) method; forming a second HfO2 layer over the first HfO2 layer by using a low pressure chemical vapor deposition (LPCVD) method; and performing a plasma treatment process at a high temperature; and forming an upper electrode over the second HfO2 layer.

Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract: A method of fabricating a ferroelectric thin film resistor includes preparing a substrate; depositing a bottom electrode; depositing a layer of ferroelectric material; depositing a top electrode; and completing the resistor; wherein, the ferroelectric resistor is programmed using a programming voltage; and wherein the ferroelectric resistor is non-destructively read by a sensing method taken from the group of sensing methods consisting of constant voltage sensing and constant current sensing.

Abstract: A method for integrating a thin film resistor into an interconnect process flow where one of the metal layers is used as a hardmask. After a via (42) etch and fill, the thin film resistor material (62) is deposited. The metal interconnect layer (76) is then deposited, including any barrier layers desired. The metal leads (70) are then etched together with the shape of the thin film resistor (60). The metal (76) over the thin film resistor (60) is then removed.

Abstract: A method for forming a resistor includes causing a semiconductor layer to have a first resistance, forming a first mask on the semiconductor layer, causing portions of the semiconductor layer left exposed by the first mask to have a second resistance that is lower than the first resistance, forming a second mask on the first mask and on the semiconductor layer, removing portions of the first mask and the semiconductor layer left exposed by the second mask, removing the second mask, and causing portions of the semiconductor layer exposed by the removing of the second mask to have a third resistance that is lower than the second resistance. Because a resistor formed by such a process can include an aligned body and contact, it often occupies a smaller area than prior integrated resistors having a similar resistance value.

Abstract: A CMOS device includes a reverse electric conduction type well (2) formed on a monoelectric conduction type semiconductor substrate (1), a first MOS transistor (3) of a reverse electric conduction type channel formed on a surface of the semiconductor substrate, and a second MOS transistor (4) of monoelectric conduction type channel is formed on a surface of the well. In the present invention, resistance elements (8R, 7R, 2R) are formed in the semiconductor substrate on a lower side of a thick field oxide film (9) covering a surface of the semiconductor substrate. Further, a second resistance element (11R) composed of a polycrystal silicon layer is formed on an upper side of the field oxide film.

Abstract: A thin film resistor (55) is formed over an etch stop layer 40. Contact pads (65) are formed n the thin film resistor (55) and a dielectric layer (80) is formed over the thin film resistor (55). Metal structures (120 are formed above the thin film resistor (55) and metal (110) is used to fill a trench and via formed in the dielectric layer (80).

Abstract: A method for processing a partially fabricated semiconductor wafer having a layer of nichrome resistor material patterned to form a plurality of nichrome resistors on a surface of the wafer includes performing a wet pre-metallization cleaning step on the wafer surface, performing an RF argon plasma sputter etching process on the wafer surface, advancing the wafer into a second reactor without breaking a vacuum in either reactor, depositing a layer of metal on the surface, patterning the metal to form a predetermined metal interconnection pattern thereof, performing a stabilization bake cycles on the wafer, measuring the TCR of the nichrome resistor material, and rejecting the wafer if the measured TCR is greater than a predetermined value.

Abstract: An improved process for fabricating simultaneously high capacitance, less than 0.13 micron metal-insulator-metal capacitors, metal resistors and metal interconnects, has been developed using single or dual damascene processing. The key advantage is the use of only one additional mask reticle to form both MIM capacitor and resistor, simultaneously. Several current obstacles that exist in BEOL, back end of line, are overcome, namely: (a) the use of two or more photo-masks to make <0.13 um MIM capacitors, (b) undulated copper surfaces, when dielectrics are deposited directly upon it, (c) particles generation concerns during etching, when attempting an etch stop on the bottom MIM plate layers, and finally, (d) dishing during CMP occurs when large copper MIM plates are required, with subsequent capacitance matching problems. The integrated method overcomes the above obstacles and simultaneously forms MIM capacitors, metal resistors and metal interconnects using damascene processing.

Abstract: Method for manufacturing a plurality of pyroelectric sensors by forming a thin pyroelectric film or layer on one face of a silicon wafer or substrate, wherein electric polarization of this film is provided between lower and upper electrodes defining pixels forming these sensors. In order to protect the wafer in the event of a short-circuit between two electrodes of a pixel, resistors are arranged in series with the lower or upper electrodes by connecting these electrodes to each other by subsets in order to carry out the electric polarization. Once this polarization has been carried out, the electric connections connecting the upper or lower electrodes are removed to allow each pixel to supply an elementary electric signal when the sensor is operating. In order to minimize the risk of short-circuits and in order to reduce the stray capacity of the electrodes, the upper and lower electrodes of the pixels are structured.

Abstract: A method of fabricating a self-aligned cross-point memory array includes preparing a substrate, including forming any supporting electronic structures; forming a p-well area on the substrate; implanting ions to form a deep N+ region; implanting ions to form a shallow P+ region on the N+ region to form a P+/N junction; depositing a barrier metal layer on the P+ region; depositing a bottom electrode layer on the barrier metal layer; depositing a sacrificial layer or silicon nitride layer on the bottom electrode layer; patterning and etching the structure to remove portions of the sacrificial layer, the bottom electrode layer, the barrier metal layer, the P+ region and the N+ region to form a trench; depositing oxide to fill the trench; patterning and etching the sacrificial layer; depositing a PCMO layer which is self-aligned with the remaining bottom electrode layer; depositing a top electrode layer; patterning and etching the top electrode layer; and completing the memory ar

Abstract: A method includes forming a first damascene interconnect layer in a first dielectric. A first dielectric film is deposited on the first dielectric and on the first damascene interconnect layer. A conductor layer is deposited on the first dielectric film. The conductor layer is patterned, via a single mask, to form a first conductor and a second conductor. The first damascene interconnect level, the first dielectric film, and the first conductor form a capacitor and the second conductor forms a resistor.

Abstract: A method and structure for controlling the surface properties in the dielectric layers in a thin film component can be provided for improving the trimming process of thin film element. A metal fill is configured with a uniform fill pattern beneath an array of thin film resistors, and can comprise a plurality of smaller features or peaks providing a finer fill pattern that improves the control of the topology of the dielectric layers. The fill pattern can be configured in various manners, such as fill patterns parallel to the thin film resistor, fill patterns perpendicular to the thin film resistor, or fill patterns comprising a checkerboard-like configuration.

Abstract: A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.

Abstract: The present invention provides a thin film resistor and method of manufacture therefor. The thin film resistor comprises a resistive layer located on a first dielectric layer, first and second contact pads located on the resistive layer, and a second dielectric layer located over the resistive layer and the first and second contact pads. In an illustrative embodiment, the thin film resistor further includes a first interconnect that contacts the first contact pad and a second interconnect that contacts the second contact pad.

Abstract: The present invention provides a high dopant concentration diffused resistor, a method of manufacture therefor, and an integrated circuit including the same. In one embodiment of the invention, the high dopant concentration diffused resistor includes a doped tub located over a semiconductor substrate and a doped resistor region located in the doped tub, the doped resistor region forming a junction within the doped tub. In a related embodiment, the high dopant concentration diffused resistor further includes first and second terminals each contacting the doped tub and the doped resistor region, wherein the first and second terminals cause the doped tub and doped resistor region to have a zero potential difference at any point across the junction when a voltage is applied to the first and second terminals.

Abstract: A process for integrating the fabrication of a thick, copper inductor structure, with the fabrication of narrow channel length CMOS devices, has been developed. The integrated process features the use of only one additional photolithographic masking step, used to form the opening in an IMD layer, that will accommodate the subsequent inductor structure. After forming damascene type openings in the same IMD layer, in the CMOS region, copper is deposited and then defined, to result in a thick, copper inductor structure, in the opening in the IMD layer, in a first region of a semiconductor substrate, as well as to result in copper interconnect structures, in the damascene type openings located in a second region of the semiconductor structure, used for the narrow channel length CMOS devices. The use of a thick, copper inductor structure, equal to the thickness of the IMD layer, results in increased inductance, or an increased quality factor, when compared to counterparts formed with thinner metal inductors.

Abstract: A process for high resolution patterning of noble metals, such as platinum, for forming various semiconductor devices, such as capacitors or wiring patterns, is disclosed. A layer of noble metal, which will form an upper electrode of a capacitor, is formed over a dielectric layer. A mask layer is then formed over the noble metal layer and patterned to leave a portion of the noble metal layer exposed. The portion of the exposed noble metal is subsequently converted to its silicide, the noble metal silicide is then etched and the dielectric layer is removed, leaving the noble metal layer patterned in an upper electrode of an IC capacitor.

Abstract: A thin film resistor maintains its resistance value when stress is applied so that it may be used in a high precision bleeder resistor circuit to maintain an accurate voltage dividing ratio. The thin film resistor has a P-type thin film resistor formed of a P-type semiconductor thin film and an N-type thin film resistor formed of an N-type semiconductor thin film overlapping the P-type thin film resistor with an insulating layer interposed therebetween, so that a change in resistance value when stress is applied is prevented. In a bleeder resistor circuit, a resistance value of one unit is regulated by a resistance value formed by a combination of the P-type thin film resistor and the N-type thin film resistor so that an accurate voltage dividing ratio can be maintained when stress is applied.

Abstract: A regulating resistor network includes a plurality of resistors connected in parallel to each other. Each of these resistors is cuttable by being irradiated with light, and a resistance value of the regulating resistor network is adjustable by cutting at least one of the resistors off.

Abstract: When a barrier metal disposed on a thin film resistor material is wet-etched to expose the underlying thin film resistor material as a thin film resistor, the wet etching is performed at first and second steps. The first step is performed using H2O2/NH4OH solution, and is stopped before the thin film resistor material is exposed. Then, the second step is performed using H2O2/H2O solution until the thin film resistor material is exposed with a desired length, thereby forming the thin film resistor.

Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).

Abstract: A resistor layer (5) is formed on an isolation insulating film (4) selectively formed in a major surface (1S) of a semiconductor substrate (1). An interlayer insulation film (7) covering the resistor layer (5) has first and second plugs (9, 19) buried therein in the form of buried interconnections. The first and second plugs (9, 19) provide connection not only between an end portion of the resistor layer (5) and first and second interconnection layers (8, 18) but also between the end portion of the resistor layer (5) and the major surface (1S) of the semiconductor substrate (1).

Abstract: There is provided a manufacturing method using a structure capable of realizing a power management semiconductor device and an analog semiconductor device, in which low costs, short manufacturing periods, and low voltage operation are possible, which have low consumption power, high drive power, high grade function, and high accuracy. With respect to the power management semiconductor device and the analog semiconductor device which each include a CMOS transistor and a resistor, the manufacturing method is a method of obtaining a P-type polycide structure as a laminate structure of a P-type polycrystalline silicon film and a high melting point metallic silicide film for respective gate electrodes of an NMOS transistor and a PMOS transistor as divided by a conductivity type thereof in a CMOS transistor.

Abstract: A method of forming a thin film resistor contact incorporates an etch-stop material to protect the underlying thin film resistor from a subsequent dry etching process to form a contact opening to the thin film resistor. More specifically, the method includes forming a thin film resistor, forming a first dielectric layer over the thin film resistor, forming a first opening through the first dielectric layer to expose an underlying portion of the thin film resistor, forming an etch-stop within the first opening of the first dielectric layer, forming a second dielectric layer over the etch-stop and the first dielectric layer, forming a second opening through the second dielectric layer to expose the underlying portion of the etch-stop, and forming a metal plug within the second contact opening, wherein the metal plug is in electrical contact with the thin film resistor by way of the etch-stop.

Abstract: The present invention discloses a method of manufacturing a semiconductor device having an upper capacitor electrode and a node resistor, including depositing a thin film at a first deposition rate on an edge portion of a wafer and at a second deposition rate on a central portion of the wafer to form the upper capacitor electrode and the node resistor, thereby improving step coverage of the upper capacitor electrode while simultaneously improving resistance distribution of the node resistor.

Abstract: A thick film circuit with a perimeter anchored thick film pad is provided. The thick film circuit includes a base substrate, a thick film bonding pad, and a solder mask layer. The thick film bonding pad is formed on the surface of the base substrate. The solder mask layer is also formed on the surface of the base substrate, and overlaps a portion of the thick film bonding pad in order to improve adhesion between the thick film bonding pad and the base substrate.

Abstract: A substrate for forming a semiconducting layer is provided to grow the semiconducting layer on a major surface thereof, wherein the substrate comprises a single crystal of a chemical formula of XB2 where X contains one of Ti and Zr and the major surface may preferably be substantially parallel to plane (0001) of the single crystal because the plane (0001) of the boride substrate is highly coherent to the lattices of GaN and AlN layers grown eptaxially on the substrate. The single crystal of the substrate may be a solid solution containing impurities of not more than 5%, wherein at least one of the impurities is one selected from Cr, Hf, V, Ta and Nb. Further, a semiconductor device includes the substrate of a single crystal of a chemical formula of XB2 and at least one semiconducting layer which is grown epitaxially on the substrate, the semiconducting layer including a nitride semiconductor of a chemical formula of ZN where Z is one of gallium, aluminum and indium and boron.