Abstract: A memory device comprising a access circuits, an electrode layer over the access circuits, an array of phase change memory bridges over the electrode layer, and a plurality of bit lines over the array of phase change memory bridges. The electrode layer includes electrode pairs. Electrode pairs include a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. A bridge of memory material crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member.

Abstract: A programmable multiple data state memory cell including a first electrode layer formed from a first conductive material, a second electrode layer formed from a second conductive material, and a first layer of a metal-doped chalcogenide material disposed between the first and second electrode layers. The first layer providing a medium in which a conductive growth can be formed to electrically couple together the first and second electrode layers. The memory cell further includes a third electrode layer formed from a third conductive material, and a second layer of a metal-doped chalcogenide material disposed between the second and third electrode layers, the second layer providing a medium in which a conductive growth can be formed to electrically couple together the second and third electrode layers.

Abstract: A semiconductor device and methods thereof. The semiconductor device includes a first layer formed on a substrate, the first layer having a higher conductivity. The semiconductor device further includes a second layer formed on the first layer, the second layer including a hole exposing a portion of the first layer, the exposed portion of the first layer having a lower conductivity. The method includes forming a first layer on a substrate, the first layer having a higher conductivity, forming a second layer on the first layer, exposing a portion of the first layer by forming a hole in the second layer, performing a process on at least the exposed portion of the first layer, the process decreasing the conductivity of the exposed portion. The exposed portion including the lower conductivity or higher resistivity may block heat from conducting in the first layer.

Abstract: A method for fabricating a variable-resistance element, the resistance of a material layer being variable in accordance with an electric current or voltage applied across first and second electrodes, the method including: (1) a first electrode production step; (2) a step of forming the material layer on the first electrode, wherein the material layer comprises an oxide semiconductor having a perovskite structure represented by the chemical formula RMCoO3, wherein R is a rare-earth element and M is an alkaline-earth element; (3) an oxygen treatment step of heating the material layer in an oxygen atmosphere; (4) a step of forming the second electrode on the material layer that was subjected to the oxygen treatment step; and (5) a hydrogen treatment step of heating the material layer in a reducing atmosphere containing hydrogen.

Abstract: Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked on top of each other such that the dielectric layers separate the adjacent conductive layers. The electronic devices may be passive devices such as resistors. The resistors are formed by depositing metal onto the dielectric layer and then implanting the metal with oxygen. The conductive layer may be formed of materials such as copper and aluminum.

Abstract: A resistor for a semiconductor device is provided. The resistor can include a first polysilicon layer formed on a semiconductor substrate; an insulating layer formed on regions of the first polysilicon layer; a second polysilicon layer formed on the insulating layer; and a contact electrically connected to the first polysilicon layer and the second polysilicon layer. The portions of the first polysilicon layer that do not have the insulating layer formed thereupon have a higher impurity ion concentration than that of the regions on which the insulating layer is formed.

Abstract: An electrically tunable resistor and related methods are disclosed. In one embodiment, the resistor includes a first resistive layer, at least one second resistive layer, and an intermediate interdiffused layer of the first resistive layer and the at least one second resistive layer. One method may include providing a first plurality of layers of different materials surrounded by at least one insulating layer, and passing a current pulse through the first plurality of layers to affect a conductivity structure of the first plurality of layers in order to obtain a first predetermined resistance value for the resistor.

Abstract: A resistor device structure and method of manufacture therefore, wherein the resistor device structure invention includes a plurality of alternating conductive film and insulative film layers, at least two of the conductive film layers being electrically connected in parallel to provide for high current flow through the resistor device at high frequencies with increased temperature and mechanical stability. The alternating conductive film and insulative film layers may be of a planar or non-planar geometric spatial orientation. The alternating conductive film and insulative film layers may include lateral and vertical portions designed to enable a uniform current density flow within the structure itself through a self-ballasting effect within the physical resistor.

Abstract: In a phase changeable memory device and a method of formation thereof, the phase changeable memory device comprises: a lower electrode pattern on an interlayer insulating layer; an insulating pattern located on the lower electrode pattern; a phase changeable pattern penetrating the insulating pattern and the lower electrode pattern to contact the lower electrode pattern and the interlayer insulating layer; and an upper electrode on the phase changeable pattern.

Abstract: A memory device includes a lower electrode layer formed over a substrate, a resistance layer including a metal nitride layer formed over the lower electrode layer, and an upper electrode layer formed over the resistance layer.

Abstract: Methods of adjusting a resistance of a buried resistor in a semiconductor are disclosed. In one aspect, the method includes using a silicidation blocking mask to define the buried resistor in the semiconductor; adjusting a size of the silicidation blocking mask to adjust a resistance of the buried resistor based on test data from a previous processing lot including a substantially similar buried resistor; and forming silicide on an area not covered by the silicidation blocking mask. The adjustment may be made by balancing the amount of the resistor that is covered with silicide versus un-silicided semiconductor to achieve the desired total resistance. The adjustment may be made according to an algorithm.

Abstract: The present invention relates to a memory cell comprising: a resistive structure; at least two electrodes coupled to the resistive structure, and at least one hydrogen reservoir structure, wherein the application of an electrical signal to one of the at least two electrodes causes the electrical resistance of the resistive structure to be modified by altering a hydrogen-ion concentration in the resistive structure.

Abstract: Storage cells for a phase change memory device and phase change memory devices are provided that include a first phase change material pattern and a first high-resist phase change material pattern on the first phase change material pattern. The first high-resist phase change material pattern has a higher resistance than the first phase change material pattern. Methods of fabricating such storage cells and/or memory devices are also provided.

Abstract: Where the silicon active layer of an SOI substrate is used as a resistor, it is difficult to form small wells densely in a semiconductor support substrate portion under the resistor because of the presence of a buried insulation film. It is also difficult to control the potential division of the wells. Therefore, there is the problem that the resistance value is varied by potential variations. Island-like silicon active layer and buried insulation film are formed by etching. Side spacers made of polycrystalline silicon are formed on the sidewalls of step portions of the island-like silicon active layer, buried insulation film, and semiconductor support substrate. The potentials at the side spacers are controlled. Thus, resistance value variations due to variations in the potential difference between the semiconductor support substrate and the resistor can be suppressed. Furthermore, accurate potential division owing to each resistor is facilitated.

Abstract: A method for manufacturing a resistor random access memory with a self-aligned air gap insulator. A high density plasma deposition on the stack of post-patterned layers produces a hard mask that is substantially near the center and overlying the cap layer of the stack of post-patterned layers. The high density plasma deposition is performed with small critical dimensions so that a small triangle is generated over the cap layer and located near the center of the cap layer. The hard mask serves to prevent the area directly underneath the base of the hard mask from etching, while the hard mask provides a self-aligned technique for etching the left and right sections of the stack of post-patterned layers because the hard mask overlies and positions near the center of the stack of post-patterned layers.

Abstract: A method of manufacturing a coil for a micro-actuator. The method of manufacturing a coil for a micro-actuator includes preparing a substrate, forming a plurality of trenches for forming a coil on the substrate, covering portions on the substrate with a masking layer except for the plurality of trenches, electroplating the plurality of trenches with a conductive material, and forming a passivation layer on the substrate. Consistent with the method, variations in sections of a coil can be reduced by minimizing bending and warping of a wafer, and therefore a driving current applied to a coil and power consumption can be reduced.

Abstract: A method and structure for increasing an electrical resistance of a resistor that is within a semiconductor structure, by oxidizing or nitridizing a fraction of a surface layer of the resistor with oxygen/nitrogen (i.e., oxygen or nitrogen) particles, respectively. The semiconductor structure may include a semiconductor wafer, a semiconductor chip, and an integrated circuit. The method and structure comprises five embodiments. The first embodiment comprises heating an interior of a heating chamber that includes the oxygen/nitrogen particles as gaseous oxygen/nitrogen-comprising molecules (e.g., molecular oxygen/nitrogen). The second embodiment comprises heating the fraction of the surface layer by a beam of radiation (e.g., laser radiation), or a beam of particles, such that the semiconductor structure is within a chamber that includes the oxygen/particles as gaseous oxygen/nitrogen-comprising molecules (e.g., molecular oxygen/nitrogen).

Abstract: A multi-resistive state element that uses a treated interface is provided. A memory plug includes at least two electrodes that sandwich a multi-resistive state element. Using different treatments on both electrode/multi-resistive state element interfaces improves the memory properties of the entire memory device.

Abstract: Provided is a non-volatile memory device including a variable resistance material and method of fabricating the same. The non-volatile memory device may include a lower electrode, an intermediate layer on the lower electrode including one material selected from the group consisting of HfO, ZnO, InZnO, and ITO, a variable resistance material layer on the intermediate layer, and an upper electrode on the variable resistance material layer. A memory device having multi-level bipolar switching characteristics based upon the size of the device may be provided.

Abstract: A metal resistor and resistor material and method of forming the metal resistor are disclosed. The metal resistor may include an infused metal selected from the group consisting of: copper (Cu) infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W), and aluminum infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W). The method is less complex than conventional processes, allows control of the resistance by the amount of infusion material infused, and is compatible with conventional BEOL processes.

Abstract: In manufacturing a chip resistor by dividing a chip resistance substrate which includes an insulator, resistance film formed on a surface of the insulator, and a plurality of conductive strips disposed on the resistance film at fixed intervals, grooves are formed by removing a predetermined width of the resistance film including at least second prescribed severing lines. After forming the grooves, the chip resistance substrate is severed in longitudinal and lateral directions along first prescribed severing lines for dividing the conductive strips into two parts and the second prescribed severing lines perpendicular to the first prescribed severing lines so as to produce discrete chip resistors.

Abstract: A phase change random access memory PCRAM device is described suitable for use in large-scale integrated circuits. An exemplary memory device has a pipe-shaped first electrode formed from a first electrode layer on a sidewall of a sidewall support structure. A sidewall spacer insulating member is formed from a first oxide layer and a second, “L-shaped,” electrode is formed on the insulating member. An electrical contact is connected to the horizontal portion of the second electrode. A bridge of memory material extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall spacer insulating member.

Abstract: Provided is a semiconductor device manufacturing method including a field oxide insulation film forming step including forming a field oxide insulation film (12) so that, in an active region (13), a portion (13a), which corresponds to a side surface portion of the active region (13) opposing a rotation center (O) in spin-coating on the surface of the semiconductor substrate (11) in a centrifugal force acting direction (F) along the surface of the semiconductor substrate (11) and located in a forward side of the centrifugal force acting direction (F), has a curved surface convex to the forward side of the centrifugal force acting direction (F) when the semiconductor substrate (11) is seen in a plan view.

Abstract: A method for forming a temperature-compensated resistor on a semiconductor substrate is provided. A resistor element is formed on the semiconductor substrate. Terminal contacts are formed on the ends of the resistor element. A temperature-compensating configuration is formed, and is selected from an enlarged transverse portion in the resistor element intermediate and spaced from the terminal contacts, and at least one contact pattern along and in contact with the resistor element intermediate and spaced from the terminal contacts.

Abstract: In one disclosed embodiment a layer is formed over a transistor gate and a field oxide region. For example, a polycrystalline silicon layer can be deposited over a PFET gate oxide and a silicon dioxide isolation region on the same chip. The layer is then doped over the transistor gate without doping the layer over the field oxide. A photoresist layer can be used as a barrier to implant doping, for example, to block N+ doping over the field oxide region. The entire layer is then doped, for example, with P type dopant after removal of the doping barrier. The second doping results in formation of a high resistivity resistor over the field oxide region, without affecting the transistor gate. Contact regions are then formed of a silicide, for example, for connecting the resistor to other devices.

Abstract: A programmable multiple data state memory cell including a first electrode layer formed from a first conductive material, a second electrode layer formed from a second conductive material, and a first layer of a metal-doped chalcogenide material disposed between the first and second electrode layers. The first layer providing a medium in which a conductive growth can be formed to electrically couple together the first and second electrode layers. The memory cell further includes a third electrode layer formed from a third conductive material, and a second layer of a metal-doped chalcogenide material disposed between the second and third electrode layers, the second layer providing a medium in which a conductive growth can be formed to electrically couple together the second and third electrode layers.

Abstract: A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in contact with the multi-resistive state element's bottom face and the bottom face of the top electrode is in contact with the multi-resistive state element's top face. The bottom electrode, the top electrode and the multi-resistive state element all have sides that are adjacent to their faces. Furthermore, the sides are at least partially covered by a sidewall layer.

Abstract: A semiconductor device comprises a semiconductor substrate, an N-channel MISFET and a P-channel MISFET provided on the semiconductor substrate, each of the N- and P-channel MISFETs being isolated by an isolation region and having a gate insulating film, a first gate electrode film provided on the gate insulating film of the N-channel MISFET and composed of a first metal silicide, a second gate electrode film provided on the gate insulating film of the P-channel MISFET and composed of a second metal silicide made of a second metal material different from a first metal material composing the first metal silicide, and a work function of the first gate electrode film being lower than that of the second gate electrode film.

Abstract: A method for producing an electronic component is provided. The method includes providing at least one die on a wafer, the at least one die having at least one sensor-technologically active and/or emitting device on at least a first side; producing at least one patterned support having at least one structure which is functional for the at least one sensor-technologically active and/or emitting device; joining the wafer with the at least one patterned support so that the first side faces the at least one patterned support; and separating the at least one die from the wafer.

Abstract: The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor device. The resistor includes first and second crystalline layers which may or may not differ from one another. One of the first and second crystalline layers comprises doped silicon/germanium, and the other comprises doped silicon. The transistor device and resistor can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). The invention also includes processes of forming semiconductor constructions, and in particular aspects, includes processes of forming resistor constructions.

Abstract: A silicon oxide film as an insulating film is accumulated so as to cover a whole surface of a silicon substrate including a surface of a resistance element by, for example, a thermal CVD method, just after a resist pattern is removed. This silicon oxide film is processed to form a silicide block on the resistance element, and side wall spacers at both side surfaces of gate electrodes, and so on, of respective transistors, at the same time.

Abstract: The present invention provides a semiconductor acceleration sensor wherein a semiconductor element is prevented from being damaged even when at least part of a weight is disposed in an internal space of a semiconductor sensor element and the mass of a weight is accordingly increased. An inner peripheral surface of a support portion 9 is constituted by four trapezoidal inclined surfaces 13 of a substantially identical shape which are annularly combined so as to define an outer peripheral surface of a frust-pyramidal space. A weight 3 is so constructed as to have an abutting portion including a linear portion 3d which abuts against the inclined surfaces 13 constituting the inner peripheral surface of the support portion 9 when the weight 3 makes a maximum displacement in a direction where a diaphragm portion 11 is located. The abutting portion 3d has a circular outline shape as seen from a side where a weight fixing portion 7 is located.

Abstract: Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked on top of each other such that the dielectric layers separate the adjacent conductive layers. The electronic devices may be passive devices such as resistors. The resistors are formed by depositing metal onto the dielectric layer and then implanting the metal with oxygen. The conductive layer may be formed of materials such as copper and aluminum.

Abstract: A method of forming PrXCa1-xMnO3 thin films having a PMO/CMO super lattice structure using metalorganic chemical vapor deposition includes preparing organometallic compounds and solvents and mixing organometallic compounds and solvents to form PMO and CMO precursors. The precursors for PMO and CMO are injected into a MOCVD chamber vaporizer. Deposition parameters are selected to form a nano-sized PCMO thin film or a crystalline PCMO thin film from the injection of PMO and CMO precursors, wherein the PMO and CMO precursors are alternately injected into the MOCVD chamber vaporizer. The selected deposition parameters are maintained to deposit the PCMO thin film species having a desired Pr:Ca concentration ratio in a specific portion of the PCMO thin film. The resultant PCMO thin film is annealed at a selected temperature for a selected time period.

Abstract: The present invention relates to a method for forming a thin film resistor and a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a portion of the gate structure. A layer of titanium nitride is deposited using a chemical vapor deposition process. A rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure. A metal layer is deposited and patterned to form an interconnect structure that electrically couples the titanium oxynitride structure to other circuitry.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: A method of fabricating a capacitor is described. A dielectric layer is formed over a substrate. An upper electrode having multiple openings therein is formed over the dielectric layer. Then, a doping step is performed to the substrate through the openings to form a single doped region as a lower electrode in the substrate under the upper electrode.

Abstract: A multi-resistive state material that uses dopants is provided. A multi-resistive state material can be used in a memory cell to store information. However, a multi-resistive state material may not have electrical properties that are appropriate for a memory device. Intentionally doping a multi-resistive state material to modify the electrical properties can, therefore, be desirable.

Abstract: PrCaMnO (PCMO) thin films with predetermined memory-resistance characteristics and associated formation processes have been provided. In one aspect the method comprises: forming a Pr3+1?xCa2+xMnO thin film composition, where 0.1<x<0.6; in response to the selection of x, varying the ratio of Mn and O ions as follows: O2?(3±20%); Mn3+((1?x)±20%); and, Mn4+(x±20%). When the PCMO thin film has a Pr3+0.70Ca2+0.30Mn3+0.78Mn4+0.22O2?2.96 composition, the ratio of Mn and O ions varies as follows: O2?(2.96); Mn3+((1?x)+8%); and, Mn4+(x?8%). In another aspect, the method creates a density in the PCMO film, responsive to the crystallographic orientation. For example, if the PCMO film has a (110) orientation, a density is created in the range of 5 to 6.76 Mn atoms per 100 ?2 in a plane perpendicular to the (110) orientation.

Abstract: A method of fabricating a doped-PCMO thin film layer includes preparing a PCMO precursor solution having a transition metal additive therein; and spin-coating the doped-PCMO spin-coating solution onto a wafer.

Abstract: A method for fabricating a semiconductor device comprises the steps of forming a polysilicon film 32 on a silicon substrate 10, implanting a dopant into a region of the polysilicon film 32 for a resistance element to be formed in, patterning the polysilicon film 32 to from the resistance element 46 of the polysilicon film 32 with the dopant inplanted in and gate electrodes 44a, 44b of the polysilicon film 32 with the dopant not implanted in. Accordingly, resistance element can be formed while suppressing influences on characteristics of the transistor formed on one and the same substrate concurrently with forming the resistance element.

Abstract: A method of controlling characteristics of a compound semiconductor device, whereby the compound semiconductor device is formed so as to include a plurality of resistors having the same ratio of a difference between a surface area of a corresponding resistivity region and the combined overlapping surface area of a corresponding pair of electrodes to the combined overlapping surface area of the corresponding pair of electrodes. In this manner, a resistivity of a resistor is precisely controlled.

Abstract: Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions. The resistive cross-point memory device is formed by doping lines within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes.

Abstract: This invention is directed to the reduction of voltage dependence and thus allows easy design of integrated semiconductor circuits. The device is equipped with a P? type resistance layer, in which a first voltage is applied to one end and a second voltage is applied to the other end and which is formed on the surface of an N-well region on the semiconductor substrate, a thin oxide film on the resistance layer, and a resistance bias electrode which includes the silicon layer formed on the thin oxide film. By adjusting the voltage applied to the resistance bias electrode, the voltage dependence of the resistance of the resistance layer is reduced.

Abstract: A photoresist (6) is formed on an element isolation insulating film (2) so as to cover the upper and side surfaces of a polysilicon film (4R) which functions as a resistance element. With the photoresist (6) as an implantation mask, n-type impurities (7) such as phosphorus are ion-implanted from a direction substantially normal to the upper surface of a silicon substrate (1). The dose is in the order of 1013/cm2. Through this processing, an LDD region (8) of MOSFET is formed inside the upper surface of the silicon substrate (1) within a transistor forming region. The impurities (7) are also implanted in a polysilicon film (4G). On the other hand, as the polysilicon film (4R) is covered by the photoresist (6), the impurities (7) are not implanted into the polysilicon film (4R).

Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

Abstract: A low temperature coefficient resistor(TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor.

Abstract: The invention is to obtain a resistor element having high resistance, a low temperature coefficient, and high uniformity of sheet resistance in a wafer. A field oxide film is formed on a semiconductor substrate. On the field oxide film a non-doped silicon film is formed by a LPCVD method. The silicon film is made of an amorphous silicon film or a polysilicon film. BF2+ is ion implanted in this silicon film. Then, either before or after this ion implantation, N2 annealing is performed at low temperature between 650 and 750° C.

Abstract: A semiconductor structure that includes at least one circuit element of a fuse, a diffusion barrier or a capacitor that is formed by refractory metal-silicon-nitrogen is disclosed. A method for fabricating such semiconductor structure that includes a fuse element, a diffusion barrier, a resistor or a capacitor by a refractory metal-silicon-nitrogen material is further disclosed. A suitable refractory metal-silicon-nitrogen material to be used is TaSiN which provides a wide range of resistivity by changing the ratio of Ta:Si:N. The invention provides the benefit that the various components of diffusion barriers, fuses, capacitors and resistors may be formed by a single deposition process of a TaSiN layer, the various components are then selectively masked and treated by either heat-treating or ion-implantation to vary their resistivity selectively while keeping the other shielded elements at the same resistivity.

Abstract: A method of applying a PCMO thin film on an iridium substrate for use in a RRAM device, includes preparing a substrate; depositing a barrier layer on the substrate; depositing a layer of iridium on the barrier layer; spin coating a layer of PCMO on the iridium; baking the PCMO and substrate in a three-step baking process; post-bake annealing the substrate and the PCMO in a RTP chamber; repeating said spin coating, baking and annealing steps until the PCMO has a desired thickness; annealing the substrate and PCMO; depositing a top electrode; and completing the RRAM device.