Abstract: A fabrication process and an integrated MOS device having multi-crystal silicon resisters are described. The process includes depositing a multi-crystal silicon layer on top of a single-crystal silicon body; forming silicon oxide regions on top of the multi-crystal silicon layer in zones where resistors are to be produced; depositing a metal silicide layer on top of and in contact with the multi-crystal silicon layer so as to form a double conductive layer; and shaping the conductive layer to form gate regions, of MOS transistors. During etching of the double conductive layer, the metal silicide layer on top of the silicon oxide regions is removed and the silicon oxide regions form masking regions for the multi-crystal silicon underneath, so as to form resistive regions having a greater resistivity than the gate regions.

Abstract: A method of forming a high polysilicon resistor over a dielectric layer, comprising the following steps. A polysilicon resistor over a semiconductor structure is provided. The polysilicon resistor has a doped polysilicon layer having a first voltage coefficient of resistance and grain boundaries having a first trapping density. A to a first level of DC current is provided for a predetermined duration through the doped polysilicon layer to stress the doped polysilicon layer to partially melt the doped polysilicon layer without causing breakdown of the doped polysilicon layer. The to a first level of DC current is removed to allow recrystallization of the melted doped polysilicon layer, whereby the recrystallized doped polysilicon layer has a second voltage coefficient of resistance less than the first voltage coefficient of resistance and grain boundaries having a second trapping density that is less than the first trapping density. This makes the Rs of the polysilicon to be stable and saturated.

Abstract: A spiral inductor fabricated above a semiconductor substrate provides a large inductance while occupying only a small surface area. Including a layer of magnetic material above and below the inductor increases the inductance of the inductor. The magnetic material also acts as barrier that confines electronic noise generated in the spiral inductor to the area occupied by the spiral inductor. Inductance in a pair of stacked spiral inductors is increased by including a layer of magnetic material between the stacked spiral inductors.

Abstract: A fabrication process and an integrated MOS device having multi-crystal silicon resisters are described. The process includes depositing a multi-crystal silicon layer on top of a single-crystal silicon body; forming silicon oxide regions on top of the multi-crystal silicon layer in zones where resistors are to be produced; depositing a metal silicide layer on top of and in contact with the multi-crystal silicon layer so as to form a double conductive layer; and shaping the conductive layer to form gate regions, of MOS transistors. During etching of the double conductive layer, the metal silicide layer on top of the silicon oxide regions is removed and the silicon oxide regions form masking regions for the multi-crystal silicon underneath, so as to form resistive regions having a greater resistivity than the gate regions.

Abstract: A resistive area 7 is formed selectively on a semi-insulating substrate 1, and ohmic electrodes 10 are formed on both ends of the resistive area. Then a photo resist 14 having an opening 13 between the electrodes 10 is so formed as not completely across the resistive area 7. A desirable resistance value is thus obtained by removing the resistance area 7 by etching through the opening 13 gradually.

Abstract: A method of fabricating a load resistor for an SRAM. A substrate has a polysilicon layer formed thereon through a buried contact process. An inter-layer dielectric layer is formed over the substrate and then patterned to form an opening that exposes the polysilicon layer. A poly via is then formed in the opening to serve as a load resistor. The inter-layer dielectric layer is patterned to form a contact window, which is then filled with a conductive layer to form a contact.

Abstract: A multilayer wiring substrate has a passive circuit element disposed on an insulating base substrate, and an insulating layer is disposed on the insulating base substrate with the passive circuit element interposed therebetween. The insulating layer is formed to have via holes for exposing specific portions of the passive circuit element, and a terminal electrodes are disposed in the via holes. Accordingly, the entire area of the multilayer wiring substrate can be reduced, and cracks caused by residual stress produced by a firing step can be prevented.

Abstract: This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the otherwise excessive negative TCR of low doped polysilicon load resistors in sub-micron, NMOS based, 4 transistor SRAM cells. The problem with a high negative TCR is that cell failures can occur as operating currents drop down too close to device leakage currents, when operating at cold temperatures. The key to this invention is a novel PN junction approach which causes polysilicon resistors to become electrically thicker at colder temperatures. A vertical PN junction is formed along the entire length of a polysilicon resistor and the temperature dependent space charge region of the PN junction is used for modulating the effective electrical thickness of the resistor. Consequently, the undesirable tendency for thermally activated grain boundary conduction to decrease with cold temperatures is partially compensated by a slight concurrent increase in resistor thickness.

Abstract: A new method of forming a polysilicon resistor having precisely controlled resistance by using a thin silicon nitride cap over the polysilicon resistor is described. A dielectric layer is provided on a semiconductor substrate. A polysilicon layer is deposited overlying the dielectric layer and patterned to form a polysilicon resistor. A silicon nitride capping layer having a thickness of not more than 100 Angstroms is deposited overlying the polysilicon resistor and dielectric layer. An interlevel dielectric layer is deposited overlying the silicon nitride capping layer. The substrate is annealed thereby densifying the silicon nitride capping layer. A self-aligned contact opening may be made through the interlevel dielectric layer, the silicon nitride capping layer, and the dielectric layer to underlying device structures. The capping silicon nitride layer is thin enough not to act as an etch stop in the self-aligned contact etching. The contact opening is filled with a conducting layer.

Abstract: A method for switching properties of perovskite thin film materials, including the colossal magnetoresitive (CMR) and high temperature superconducting (HTSC) materials, is provided. Short electrical pulses are applied to the materials in thin films to change both reversibly and non-reversibly the electrical, thermal, mechanical and magnetic properties of the material. Reversible resistance changes of over a factor of 10 are induced in CMR materials at room temperature and in zero external magnetic field by electrical pulsing. Applications of the method and materials to form memory devices, resistors in electronic circuits which can be varied in resistance and other applications are disclosed.

Abstract: The present invention provides stable and reliable extremely high resistance polysilicon resistors for use as SRAM load elements, and methods for their fabrication. In an embodiment, a resistor element of a semiconductor device includes at least one polysilicon layer, and a silicon nitride layer deposited directly onto this polysilicon layer. The silicon nitride layer prevents contamination of the polysilicon layer during subsequent fabrication process steps. A method of fabricating a polysilicon resistor on a semiconductor substrate is also provided. The method includes the step of depositing a layer of polysilicon on the substrate, followed by depositing a layer of protective material over the polysilicon layer to form a protected polysilicon layer. After deposition of the protective layer, resistors are formed by implanting dopants into the polysilicon layer, and patterning through lithography, and etching the nitride and the polysilicon layer.

Abstract: A process for increasing the sheet resistance and lowering the temperature coefficient of resistance of a thin film resistor deposited on a wafer, the process comprising ramping the temperature of the wafer to an annealing temperature above the decomposition temperature of the thin film resistor using a radiant heat source such that the wafer reaches the annealing temperature within a ramp up time of from about 5 to 10 seconds, and annealing the wafer at the annealing temperature for an annealing period of from about 50 to 85 seconds.

Abstract: A method of fabricating a static random access memory. A substrate having a gate is provided. A source/drain region is formed in the substrate beside the gate. A metal silicide layer is formed on the source/drain region and the gate region. A conductive line which is electrically coupled to the metal silicide layer on the source/drain region is formed over the substrate. A dielectric layer having a via is formed over the substrate. A portion of the conductive line is exposed by the via. A polysilicon conductive line is formed conformably to the via and the dielectric layer. The polysilicon conductive line is electrically coupled to the conductive line. An ion implantation is performed to form a poly load of the static random access memory.

Abstract: A method of fabricating a load resistor. The load resistor is often applied in a static random access memory. The interconnect between different conductive regions such as gate and source/drain region is formed by applying a hydrogen treatment to a refractory metal oxide layer, while the load resistors are formed by applying a hydrogen treatment with different parameters as the former one. The insulation is formed by the refractory metal oxide layer which is not to be covered.

Abstract: A method of fabricating a static random access memory. A gate oxide layer is formed on a substrate having active regions of an access transistor and a drive transistor. A Polysilicon layer is formed on the gate oxide layer. A germanium implantation is performed on the polysilicon layer of the active region of the drive region to form a polysilicon germanium layer. Thereafter, the polysilicon layer and the polysilicon germanium layer are patterned to form a poly gate and a polysilicon germanium gate on the active regions of the access transistor and the drive transistor. A lightly doped region is formed in the substrate beside the gates. A spacer is then formed on the sidewall of the gates. A heavily doped region is formed in the substrate beside the spacer.

Abstract: A method of making a semiconductor device having a thin film resistor, the method comprising the steps of: forming a first polysilicon layer on an upper surface of a field oxide layer formed on a semiconductor substrate; forming a first dielectric layer on a resultant material; ion-implanting an impurity for forming a resistor in the first polysilicon layer through the first dielectric layer; forming a second dielectric layer on an upper surface of the first dielectric layer; selectively etching the first and second dielectric layers and the first polysilicon layer to form a resistor poly (RPOLY) lower electrode; forming a second polysilicon layer on an upper surface of a resultant material; and forming a gate poly (GPOLY) by selectively etching the second polysilicon layer.

Abstract: An integrated circuit inverted thin film resistor structure and method of manufacture having interconnect defining resistor contacts and leads resident within and coplanar with a supporting layer, resistive material uniformly overlaying the supporting layer and contacts, the resistive material diffused into the resistor/interconnect contact region.

Abstract: An integrated circuit resistor (18) has a layout in which a first parasitic capacitance (26) exists between first portions of the resistor (18) and a first integrated circuit feature (34), and a second parasitic capacitance (28) exists between second portions of the resistor and a second integrated circuit feature (32). The resistor (18) may have, for example, a zigzag or serpentine configuration, with portions of each leg of the zigzag configuration overlying the first and second integrated circuit features (34,32). The first and second integrated circuit features (34,32) are configured to produce substantially canceling charges on the first and second parasitic capacitances (26,28). The resistor may be defined by a doped semiconductor material, such as a polysilicon layer. The resistor may be used in many applications, such as a feedback resistor of an optoelectronic current-to-voltage converter (12).

Abstract: A static random access memory device includes: a semiconductor substrate divided into a cell array portion and a periphery circuit portion; a first insulating layer for insulating devices formed on the substrate from a thin-film transistor; a conductive layer formed on the first insulating layer in the cell array portion, for supplying power; a buffer layer formed on the conductive layer in the cell array portion; a second insulating layer formed on the buffer layer in the cell array portion and on the first insulating layer of the periphery circuit portion; and a metal wiring pattern formed on the second insulating layer. A first portion of the metal wiring pattern connects to the conductive layer via a first contact hole which is formed passing through the second insulating layer and the buffer layer, thus exposing the conductive layer in the cell array portion.

Abstract: A new method of forming a polysilicon resistor having reduced resistance variations by using an LPCVD silicon nitride cap over the polysilicon resistor is described. A field oxide layer is provided overlying a semiconductor substrate. A polysilicon layer is deposited overlying the field oxide layer and etched away where it is not covered by a mask to form a polysilicon resistor. The polysilicon resistor is oxidized to form an oxide layer on all surfaces of the polysilicon resistor. A silicon nitride barrier layer is deposited overlying the oxide layer. An interlevel dielectric layer is dpeosited overlying the silicon nitride barrier layer. Contact openings are etched through the interlevel dielectric layer, silicon nitride barrier layer, and oxide layer to the polysilicon resistor. The contact openings are filled with a metal layer which is patterned.

Abstract: A high-sheet-resistance polysilicon resistor for integrated circuits is achieved by using a two-layer polysilicon process. After forming FET gate electrodes and capacitor bottom electrodes from a polycide layer, a thin interpolysilicon oxide (IPO) layer is deposited to form the capacitor interelectrode dielectric. A doped polysilicon layer and an undoped polysilicon layer are deposited and patterned to form the resistor. The doped polysilicon layer is in-situ doped to minimize the temperature and voltage coefficients of resistivity. Since the undoped polysilicon layer has a very high resistance (infinite), the resistance is predominantly determined by the doped polysilicon layer.

Abstract: A method of forming an SRAM cell includes, a) providing a pair of pull-down gates having associated transistor diffusion regions operatively adjacent thereto, one of the diffusion regions of each pull-down gate being electrically connected to the other pull-down gate; b) providing a pair of pull-up resistor nodes for electrical connection with a pair of respective pull-up resistors, the pull-up nodes being in respective electrical connection with one of the pull-down gate diffusion regions and the other pull-down gate; c) providing a first electrical insulating layer outwardly of the resistor nodes; d) providing a pair of contact openings, with respective widths, through the first insulating layer to the pair of resistor nodes; e) providing a second electrical insulating layer over the first layer and to within the pair of contact openings to a thickness which is less than one-half the open widths; f) anisotropically etching the second electrical insulating layer to define respective electrical insulating ann

Abstract: The present invention is a method for preventing backside polysilicon peeling in 4T+2R SRAM process. This invention utilizes forming oxide cap layer on the backside of the wafer to protect the backside polysilicon. Thus, the backside polysilicon is free from peeling and damage.

Abstract: A method of producing a semiconducting material comprises reacting one or more of halogenosilanes with an alkali metal and/or an alkaline earth metal in an inert solvent to give a condensate and thermally decomposing the condensate. The condensate is dissolved in a suitable solvent such as toluene and tetrahydrofuran and applied by casting to a suitable substrate. The resulting semiconductor material in its film form has an optical band-gap (EO) of usually 0.1-4.0 eV.

Abstract: FIG. 5b shows a first thin film resistor 14 formed by direct etching or lift off on a first dielectric layer 12 that covers an integrated circuit (not shown) in a silicon substrate 10. A patterned layer of photoresist covers a portion of the second thin film resistor material 30. The second thin film resistor material 30 is different from the first thin film resistor material 14. The exposed portion of the second thin film resistor material 30 is removed to leave first and second thin film resistors on the first dielectric layer 12.

Abstract: A method of fabricating an interconnect structure having improved electromigration resistance. Two conductive lines are formed over a substrate and isolated by a dielectric layer. A contact/via array including a plurality of row contact/vias and column contact/vias are formed within the dielectric layer and electrically connect to the two conductive lines. The load resistors are respectively inserted into the two conductive lines close to the contact/via array. The load resistors are parallel to each other and disposed to its corresponding contact/via array. The load resistors having various resistances are formed by a plurality of slots with various lengths, which are filled with dielectrics. Accordingly, the current paths from one conductive line to the other conductive line through the contact/vias and the load resistors corresponding to the two conductive lines have identical equivalent resistance.

Abstract: A structure of a conductive line. The structure of a conductive line comprises a substrate with two conductive lines formed thereon. These two conductive lines are isolated by the formation of a dielectric layer. The conductive lines are electrically connected by a contact/via array. The contact/via array further comprises contact/via columns and contact/via rows made up of contacts/vias. Each contact/via column and contact/via row are added with a load resistor, so that the equivalent resistance of each contact/via is identical.

Abstract: A polysilicon load structure and its manufacturing method for static random access memory, comprising the steps of first providing a semiconductor substrate, and then forming a first insulating layer over the substrate. Next, a trench is etched out from the insulating layer forming a step structure. Thereafter, a polysilicon layer is formed over the first insulating layer, and then a global ion implantation operation is performed. Next, a photoresist layer is formed over the polysilicon layer, and then a connector pattern is defined using a microlithographic process. Thereafter, the polysilicon layer is anisotropically etched to form a spacer on the sidewall of the trench. Subsequently, a second ion implantation is performed to adjust the resistance of the connector. Finally, microlithographic and etching processes are used to remove the unwanted portions of the polysilicon spacer and exposing the polysilicon spacer structure and the polysilicon connector structure.

Abstract: A static metal oxide semiconductor random access memory (SRAM) having NMOS and thin film transistors (TFTs) formed from a single polysilicon layer, and a method for forming the same. The SRAM cell comprises a plurality of NMOS transistors and TFTs that are interconnected by a local interconnect structure. The single layer of poly is used to define the TFT bodies and gates of NMOS transistors in the SRAM cell. Each TFT comprises a single polysilicon layer comprising source gate and drain regions. During the fabrication process, exposed portions of the TFT polysilicon body and exposed regions of NMOS transistors react with a refractory metal silicide to form polycide and silicide regions, respectively. An amorphous silicon pattern also reacts with the refractory metal silicide to form a local interconnect structure connecting the silicided portions of the thin film transistors and the MOS transistors.

Abstract: According to the preferred embodiment of the present invention, an improved resistor and method of fabrication is provided. The method for fabricating a resistive element into an integrated circuit semiconductor device comprises the steps of: depositing a dielectric film, such as silicon nitride; depositing a titanium film upon the dielectric film; and annealing the titanium and dielectric films. This causes titanium to be diffused into the dielectric film. This creates a resistive element having a relatively high resistivity. The preferred embodiment method has the advantage of being easily integrated into conventional integrated circuit fabrication techniques.

Abstract: The inventive SRAM cell has a poly-load resistor which comprises a thick supply voltage (Vcc) interconnect, a thick driver interconnect on a thin load resistance region which is electrically connected to both interconnects. The novel poly-load resistor overcomes the problem of lateral diffusion from the interconnect regions into the load region. The resulting SRAM cell has a low Vcc interconnect resistance.

Abstract: The device hereof provides an integrated circuit resistor (34) comprising amorphous or noncrystalline semiconducting material. Further advantages can be gained in area by forming the noncrystalline semiconductor resistor in a non-planar fashion (i. e. with a vertical construction) wherein a first electrical contact is made to the resistor on its bottom surface and a second electrical contact is made to the resistor on its top surface.Other devices, systems and methods are also disclosed.

Abstract: A method for fabricating SRAM polyloads that allows device dimension reduction yet maintains overall product functionality which includes the following steps: forming an insulating layer above a semiconductor substrate having a conductive gate device and a conductive voltage source line device already formed in it; etching the insulating layer selectively, and forming a first contact window and a second contact window on the surfaces of the conductive gate device and the conductive voltage source line device respectively; forming a polysilicon layer above the insulating layer, and filling up the first and the second contact windows at the same time; forming a silicide layer above the polysilicon layer; etching the silicide layer and the polysilicon layer to form a conductive wire linking the first contact window with the second contact window; and etching selectively section of the silicide layer on the conductive wire to expose the polysilicon layer below, and forming a polyload in the exposed polysilicon la

Abstract: The present invention relates to a semiconductor apparatus adapted to a ultrahigh density integration process.A semiconductor apparatus of the present invention is characterized by including a high concentration impurity layer with the same type of conductivity as that of a semiconductor wafer provided on the back of the semiconductor wafer, and at least one layer of a low resistance electrode provided on said high concentration impurity layer.

Abstract: A method for stabilizing a polysilicon resistor. Formed through a conventional method upon a semiconductor substrate is a polysilicon resistor. The polysilicon resistor is treated with a nitrogen plasma. After treatment with the nitrogen plasma, the polysilicon resistor exhibits a high and stable resistance having minimal susceptibility to variation due to intrusion of hydrogen or other reactive species into the polysilicon resistor.

Abstract: A method for fabricating polysilicon load resistors, with increased resistance values, for use in SRAM cells, has been developed. An underlying, raised grid topography is used to allow the overlying polysilicon load resistor to traverse the severe topography, resulting in an increase in resistor length, while still maintaining the allotted design space, overlying a MOSFET device. The formation of back to back diodes in the polysilicon load resistor also results in an increase in resistance. The back to back diodes are created via N type, ion implantation into only flat regions of an intrinsic, or P type doped, polysilicon load resistor, regions in which the polysilicon load resistor overlaid the flat regions of the underlying raised grid topography, leaving regions of the polysilicon load resistor, located on the sides of the underlying raised grid topography, P type.

Abstract: A process for fabricating MOSFET devices, for a SRAM cell, using a polycide contact structure, self-aligned to an underlying source and drain region, has been developed. This process features the use of a RTCVD procedure, featuring loading of wafers, as well as evacuation procedures, both performed at room temperature, in a first RTCVD chamber, followed by the deposition of polysilicon and tungsten silicide layers, performed in the same RTCVD chamber. The in situ, room temperature load and evacuation processes, followed by polysilicon and tungsten depositions, results in polycide interfaces with minimal levels of native oxide, thus improving device characteristics, and SRAM performance.

Abstract: A process for fabricating a protective shield for polysilicon loads in SRAM devices is disclosed. The protective shield enables to protect the polyloads from resistance characteristics degradation during the subsequent plasma-based processing steps in the fabrication of the memory device after the polyloads are formed. The polyloads are formed in a photolithography procedure by utilizing a photomask defining the resistive and conductive portions of the polyloads. The process comprises the steps of forming a shield silicon oxide layer over the surface of the memory device in process, including the polyloads, and forming a shield silicon nitride layer on the top of the shield silicon oxide layer. The protective shield is then formed by etching in the shield silicon oxide and nitride layers utilizing a protective photomask. The protective photomask is the same photomask utilized in the formation of the polyloads in the previous photolithography procedural step of the fabrication of the memory device.

Abstract: The present invention is a method of manufacturing a high/low resistance on a mix-mode product. The method includes forming a polysilicon layer over a wafer. A blanket ion implantation is performed to implant ions into the entire polysilicon layer. The polysilicon layer is then separated into a high resistance area and a low resistance area. The low resistance area top surface is raised higher than the high resistance area. A photoresist is then formed on the polysilicon areas. The photoresist is subsequently etched back to the top surface of the low resistance areas. A second implant is done on the low resistance area.

Abstract: A method for fabricating polysilicon load resistors, with increased resistance values, for use in SRAM cells, has been developed. An underlying, raised grid topography is used to allow the overlying polysilicon load resistor to traverse the severe topography, resulting in an increase in resistor length, while still maintaining the allotted design space, overlying a MOSFET device. The formation of back to back diodes in the polysilicon load resistor also results in an increase in resistance. The back to back diodes are created via N type, ion implantation into only flat regions of an intrinsic, or P type doped, polysilicon load resistor, regions in which the polysilicon load resistor overlaid the flat regions of the underlying raised grid topography, leaving regions of the polysilicon load resistor, located on the sides of the underlying raised grid topography, P type.

Abstract: A polysilicon resistor (40) includes a field oxide layer (12) and a polysilicon layer (20) that covers a portion of field oxide layer (12). The polysilicon layer (20) possesses a predetermined electrical resistance value. Nitride/oxide stack (42) covers a predetermined portion of the polysilicon layer (20) and forms at least one exposed location of polysilicon layer (20) on which not to implant a dopant to achieve a predetermined resistance value. Silicide layer (34) covers exposed location.

Abstract: A semiconductor device at least including a region which contains a first impurity constituted by a group V element and a second impurity constituted by an element of high electronegativity or a halogen element such as Ti, Cl, O, Br, S, I or N in amorphous silicon, polycrystalline silicon, single crystal silicon, a refractory metal such as Ti, Mo, W, Ta, Pt, Pd and Zr or a silicide of such refractory metal. The semiconductor device is manufactured by introducing the second impurity before, after or during introduction of the first impurity, for example, by ion implantation into amorphous, polycrystalline or single crystal silicon, a refractory metal, or a silicide thereof and then annealing to form an N-type impurity region.

Abstract: A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) providing an exposed vertical sidewall in the first electrically insulative material outwardly of the node; d) providing a second electrically insulative material outwardly of the first material and over the first material vertical sidewall, the first and second materials being selectively etchable relative to one another; e) anisotropically etching the second material selectively relative to the first material to form a substantially vertically extending sidewall spacer over the first material vertical sidewall and to outwardly expose the first material adjacent the sidewall spacer, the spacer having an inner surface and an outer surface; f) etching the first material selectively relative to the second material to outwardly expose at least a portion of the s

Abstract: In a semiconductor strain sensor, for example, using resistors of a polycrystalline semiconductor material such as polycrystalline silicon as strain gauges, the sum of the temperature coefficient of resistance (TCR) of the resistor and the temperature coefficient of strain sensitivity (TCK) is adjusted not by controlling the impurity carrier concentration but by controlling the resistivity, thereby an output fluctuation due to a change in the temperature can be suppressed.

Abstract: A method is provided for manufacturing a polysilicon load resistor of a semiconductor memory cell. The semiconductor memory cell is formed with at least one transistor and has a semiconductor substrate with a gate dielectric layer on a portion thereof, and a gate electrode layer over the gate dielectric layer.

Abstract: A sensor for use in read/writing the magnetic pattern stored in a magnetic storage disk uses a Corbino structure comprising inner and outer electrodes enclosing a magnetoresistive element. The sensor is formed at the front surface of a stack of superposed layers of which the first and fifth are of a high resistivity semiconductive material, the second and fourth are of a magnetoresistive material and the third of a metal or composite structure. The second and fourth layers form a loop around the third layer, the first and fifth form a loop around the second and fourth layers. A dopant is diffused into the front surface of the stack to convert edge portions of the first and fifth layers to low resistivity to form a conductive loop that serves as the outer electrode of the Corbino disk, the third electrode serving as the inner electrode.

Abstract: A method for fabricating a semiconductor device having a high-resistance polysilicon and low-resistance polysilicon on the surface of a substrate comprises forming a gate oxide film on the substrate, forming a polysilicon film on the gate oxide film, and simultaneously forming a resistance, a wire, and a gate electrode from the polysilicon film by etching using a resist as a mask. Impurities are introduced into the polysilicon for controlling a resistance value thereof to form the high-resistance polysilicon resistance through ion implantation. Impurities are also introduced into the polysilicon to form the low-resistance polysilicon wire through ion implantation. N-type impurities are introduced into the gate electrode of a PMOS transistor and the source and drain regions of the PMOS transistor through ion implantation. P-type impurities are introduced into the gate electrode of an NMOS transistor and the source and drain regions of the NMOS transistor through ion implantation.