Abstract: Methods and structure for a semiconductor device is disclosed, which provides a semiconductor device that includes an integral semiconductor fin structure having a middle section defining a channel region of the semiconductor device. The middle section includes an embedded root portion protruding from an insulating surface on a substrate and a suspended overhead portion arranged above the root portion, which is separated from the overhead portion by a predetermined distance. The root portion and the overhead portion respectively define a substantially identical channel direction. The device further includes a gate structure disposed over the fin structure at the middle section. The gate structure wraps around a cross-section of the overhead portion and caps over the protruded portion of the root portion.

Abstract: A semiconductor device includes an inter-layer dielectric (ILD) layer over a substrate; and a first gate feature in the ILD layer, the first gate feature comprising a first gate material and having a first resistance, wherein the first gate material comprises a first conductive material. The semiconductor device further includes a second gate feature in the ILD layer, the second gate feature comprising a second gate material and having a second resistance higher than the first resistance, wherein the second material comprises at least 50% by volume silicon oxide.

Abstract: A method is provided for fabricating a flash memory device. The method includes providing a semiconductor substrate; and forming a first polysilicon layer. The method also includes forming a hard mask layer; and forming a plurality of first openings exposing the first polysilicon layer in the hard mask layer and the first polysilicon layer. Further, the method includes forming a plurality of grooves by etching the semiconductor substrate along the first openings; and forming liner oxide layers by oxidizing the first polysilicon layer. Further, the method also includes forming shallow trench isolation structures by filling the first openings; and forming second openings by removing the hard mask layer and the non-oxidized first polysilicon layer. Further, the method also includes forming a tunnel oxide layer on a bottom of the second opening; and forming a floating gate on each of the tunnel oxide layers.

Abstract: In a semiconductor device according to the present invention, an electrode layer and a recessed part are formed on a surface of a semiconductor substrate. Further, in the semiconductor substrate, a RESURF layer that is in contact with a bottom surface of the recessed part and the electrode layer is formed. In addition, an insulating film is formed on an upper surface of the semiconductor substrate so as to fill the recessed part. Moreover, a field plate electrode is formed on the insulating film above the recessed part.

Abstract: Exemplary methods for fabricating a metal gate electrode include forming a dielectric layer on a substrate, and forming a first trench having a first width and a second trench having a second width in the dielectric layer where the first width is less than the second width. Also included is depositing a work-function metal layer over the dielectric layer and into the first and second trenches where the deposited work-function layer is in direct contact with the top surface of the dielectric layer. A first signal metal layer is deposited over the work-function metal layer filling the second trench and a second signal metal layer is deposited filling the first trench.

Abstract: A method for forming a cell contact. A substrate having first and second protruding structures is prepared. An etch stop layer is deposited over the substrate. A sacrificial layer is deposited on the etch stop layer. The sacrificial layer is recessed. Spacers are formed on the top surface of the sacrificial layer. A portion of the sacrificial layer not covered by the spacers is etched away, thereby forming a recess. A gap filling material layer is deposited into the recess. An upper portion of the gap filling material layer and the spacers are removed to expose the top surface of the sacrificial layer. The sacrificial layer is removed to form contact holes. A punch etching process is performed to remove the etch stop layer from bottoms of the contact holes. The contact holes is filled up with a conductive material layer.

Abstract: A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG trench and a pFET RMG trench; forming a first Ti layer in the nFET and pFET RMG trenches; implanting N2 in the first Ti layer vertically at a 0° implant angle in the pFET RMG trench; annealing the N2 implanted first Ti layer to form a TiN layer in the pFET RMG trench; stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting Al or C in the second Ti layer vertically at 0°; annealing the Al or C implanted second Ti layer to form TiAl or TiC at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or W.

Abstract: A method for filling a trench in a substrate includes partially filling the trench with a first silicon dioxide layer. An amorphous silicon layer is deposited on the silicon dioxide layer. The trench is filled with a second silicon dioxide layer. An oxidation treatment is performed on the substrate to oxidize the amorphous silicon layer.

Abstract: The disclosure relates to a method for forming a nanoscale structure by forming a pattern on a selectively etched layer located on top of a substrate using lithography, wherein the pattern results a gap having sidewalls, performing RIE on the gap having sidewalls, wherein RIE results in the formation of a self-aligned mask on the bottom wall of the gap with unprotected regions on the bottom wall of the gap near the junctions with the sidewalls, and wet etching the gap having a self-aligned mask and unprotected regions to remove the substrate under the unprotected regions to form a nanoscale structure in the substrate. The disclosure also relates to a nanoscale structure array including a plurality of nanotrenches, nanochannels or nanofins having a width of 50 nm or less and an average variation in width of 5% or less along the entire length of each nanotrench, nanochannel or nanofin.

Abstract: A bulk finFET with partial dielectric isolation is disclosed. The dielectric isolation is disposed underneath the channel, and essentially bounded by the channel, such that it does not extend laterally beyond the channel under the source and drain regions. This allows increased volume of SiGe source and drain stressor regions placed adjacent to the channel, allowing for a more strained channel, which improves carrier mobility. An N+ doped silicon region is disposed below the dielectric isolation and extends laterally beyond the channel and underneath the stressor source and drain regions, forming a reverse-biased p/n junction with the P+ doped source and drain SiGe stressor to minimize leakage currents from under the insulator.

Abstract: A method is provided, along with a corresponding apparatus, for filling a high aspect ratio hole without voids or for producing high aspect ratio structures without voids. A beam having a diameter smaller than the diameter of the hole is directed into the hole to induced deposition beginning in the center region of the hole bottom. After an elongated structure is formed in the hole by the beam-induced deposition, a beam can then be scanned in a pattern at least as large as the hole diameter to fill the remainder of the hole. The high aspect ratio hole can then be cross-sectioned using an ion beam for observation without creating artefacts. When electron-beam-induced deposition is used, the electrons preferably have a high energy to reach the bottom of the hole, and the beam has a low current, to reduce spurious deposition by beam tails.

Abstract: A CMOS circuit is provided that includes a PMOS transistor, an NMOS transistor adjacent the PMOS transistor in a channel width direction, a compressive stress liner overlying the PMOS transistor, and a tensile stress liner overlying the NMOS transistor. A portion of the compressive stress liner and a portion of the tensile stress liner are in a stacked configuration, and an overlap region of the compressive stress liner and the tensile stress liner is sufficient to result in an enhanced transverse stress in the compressive stress liner or the tensile stress liner.

Abstract: Disclosed is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure comprises a first portion of a trench extending through the top semiconductor layer and through a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a second portion of the trench, having sloped sidewalls, extends into the handle wafer. The sloped sidewalls are amorphized by an implant, for example, Xenon or Argon, to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer.

Abstract: The use of two different materials for shallow trench isolation and deep structural trenches with a dielectric material therein (e.g., flowable oxide and a HARP oxide, respectively) causes non-uniform heights of exposed portions of raised semiconductor structures for non-planar semiconductor devices, due to the different etch rates of the materials. Non-uniform openings adjacent the exposed portions of the raised structures from recessing the isolation and dielectric materials are filled with additional dielectric material to create a uniform top layer of one material (the dielectric material), which can then be uniformly recessed to expose uniform portions of the raised structures.

Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Each gate is formed over the gate dielectric and a base that extends horizontally at least partially between adjacent pillars. The base is formed with notches filled with the gate dielectric. The select device is fabricated using a conformally deposited base dielectric material and conformal hard mask layer that is formed with a larger bottom thickness than horizontal thickness. The base thickness is defined by the deposition thickness, rather than an uncontrolled etch back.

Abstract: A semiconductor die including strain relief for through substrate vias (TSVs). A method for strain relief of TSVs includes defining a through substrate via cavity in a substrate. The method also includes depositing an isolation layer in the cavity. The method further includes filling the cavity with a conductive material. The method also includes removing a portion of the isolation layer to create a recessed portion.

Abstract: At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for the memory cells that can be programmed based on the directions of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a resistive element coupled to the P terminal of the first diode and to the N terminal of a second diode. The diodes can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diodes. By applying a high voltage to a resistive element and switching the N terminal of the first diode to a low voltage while disabling the second diode, a current flows through the memory cell can change the resistance into one state. Similarly, by applying a low voltage to a resistive element and switching the P terminal of the second diode to a high voltage while disabling the first diode, a current flows through the memory cell can change the resistance into another state.

Abstract: Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a material layer is formed over a workpiece. The workpiece includes a first portion, a second portion, and a hard mask disposed between the first portion and the second portion. The material layer is patterned, and first spacers are formed on sidewalls of the patterned material layer. The patterned material layer is removed, and the second portion of the workpiece is patterned using the first spacers as an etch mask. The first spacers are removed, and second spacers are formed on sidewalls of the patterned second portion of the workpiece. The patterned second portion of the workpiece is removed, and the hard mask of the workpiece is patterned using the second spacers as an etch mask. The first portion of the workpiece is patterned using the hard mask as an etch mask.

Abstract: A mobile station (MS) performs a measurement of cells on a plurality of downlink frequencies used for a connection with a base station apparatus. The MS also detects a first indication or a second indication, based on the measurement of each cell designated by the base station apparatus, the first indication indicating a measurement result of a cell becomes lower than a first threshold and the second indication indicating a measurement result of a cell becomes higher than a second threshold. In addition, the MS, in a case where a reconnection procedure is started by expiring a timer corresponding to the each cell, selects a cell, and initiates a random access procedure for requesting a reconnection in the selected cell. Further, the timer is started if the first indication is indicated consecutively for a certain number of times.

Abstract: A method for manufacturing a semiconductor device may include the following steps: providing a composite structure that includes a gate material layer, a first mask material layer, and a sacrificial layer; partially removing, through a first mask, the sacrificial layer to form a sacrificial members; providing a second mask material layer on the sacrificial members; partially removing the second mask material layer to form mask units that contact sides of the sacrificial members; removing the sacrificial members; providing a third mask material layer between two of the mask units for forming a second mask; partially removing, through the second mask, the first mask material layer to form a third mask; and partially removing, through the third mask, the gate material layer to form a control gate and a select gate.

Abstract: Low leakage, high frequency devices and methods of manufacture are disclosed. The method of forming a device includes implanting a lateral diffusion drain implant in a substrate by a blanket implantation process. The method further includes forming a self-aligned tapered gate structure on the lateral diffusion drain implant. The method further includes forming a halo implant in the lateral diffusion drain implant, adjacent to the self-aligned tapered gate structure and at least partially under a source region of the self-aligned tapered gate structure.

Abstract: A semiconductor device includes a bulk substrate having a plurality of trenches formed therein. The trenches define a plurality of semiconductor fins that are integral with the bulk semiconductor substrate. A local dielectric material is disposed in each trench and between each pair of semiconductor fins among the plurality of semiconductor fins. The semiconductor device further includes an etch resistant layer formed on the local dielectric material.

Abstract: Methods of forming resist features, resist patterns, and arrays of aligned, elongate resist features are disclosed. The methods include addition of a compound, e.g., an acid or a base, to at least a lower surface of a resist to alter acidity of at least a segment of one of an exposed, acidic resist region and an unexposed, basic resist region. The alteration, e.g., increase or decrease, in the acidity shifts an acid-base equilibrium to either encourage or discourage development of the segment. Such “chemical proximity correction” techniques may be used to enhance the acidity of an exposed, acidic resist segment, to enhance the basicity of an unexposed, basic resist segment, or to effectively convert an exposed, acidic resist segment to an unexposed, basic resist segment or vice versa. Thus, unwanted line breaks, line merges, or misalignments may be avoided.

Abstract: MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment. The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET.

Abstract: A semiconductor device which includes a first gate structure on a substrate and a second gate structure on the substrate is provided. The semiconductor device further includes an inter-level dielectric (ILD) layer on the substrate between the first gate structure and the second gate structure, wherein a top portion of the ILD layer has a different etch selectivity than a bottom portion of the ILD layer.

Abstract: A process for fabricating an integrated circuit includes, in a stack of layers including a silicon substrate overlaid with a buried insulating layer overlaid with a silicon layer, etching first trenches into the silicon substrate, depositing a silicon nitride layer on the silicon layer to fill the first trenches and form first trench isolations, forming a mask on the silicon nitride layer, etching second trenches into the silicon substrate, in a pattern defined by the mask, to a depth greater than a depth of the first trenches, filling the second trenches with an electrical insulator to form second trench isolations, carrying out a chemical etch until the silicon layer is exposed, and forming a FET by forming a channel, a source, and a drain of the field effect transistor in the silicon layer.

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of first and second fins that are made of different semiconductor materials that may be selectively etched relative to one another, forming a first insulating material between the plurality of first and second fins, forming an etch mask above the first and second fins that exposes a portion of at least one first fin and exposes a portion of at least one second fin, performing an etching process to remove the exposed portion of the at least one first fin selectively to the first insulating material and the exposed portion of the at least one second fin so as to thereby define at least one removed fin cavity in the first insulating material, removing the patterned etch mask, and forming a second insulating material in the at least one removed fin cavity.

Abstract: A process for manufacturing a writer main pole for a perpendicular magnetic recording system is provided. The writer pole may have a constant sidewall angle from the ABS to yoke and may be formed out of an insulating material and a magnetic material. The sidewall angle of the yoke region may be adjusted during manufacture. The ABS region may correspond to the magnetic material and the yoke region may correspond to the insulating material. The insulating material may comprise Alumina. The magnetic material may comprise a NiFe alloy.

Abstract: Isolation structures for isolating semiconductor devices from a substrate include floor isolation regions buried within the substrate and one or more trenches extending from a surface of the substrate to the buried floor isolation region.

Abstract: A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin.

Abstract: A method of fabricating a fin field effect transistor (FinFET) device and the device are described. The method includes forming a deep STI region adjacent to a first side of an end fin among a plurality of fins and lining the deep STI region, including the first side of the end fin, with a passivation layer. The method also includes depositing an STI oxide into the deep STI region, the passivation layer separating the STI oxide and the first side of the end fin, etching back the passivation layer separating the STI oxide and the first side of the end fin to a specified depth to create a gap, and depositing gate material, the gate material covering the gap.

Abstract: A method and apparatus for conditioning an oxide surface during a semiconductor device formation process is provided herein. One or more plasma processing operations are performed on a substrate having a fin structure and shallow trench isolation structure (STI) formed thereon. An oxygen containing plasma process may modify surfaces of the STI structure in preparation for an argon containing plasma process. The argon containing plasma process may form a first layer on the fin structure and STI structure and an ammonia fluoride containing plasma process may form a second layer on the first layer. The first and second layers may be removed from the substrate during a subsequent heating process to provide a cleaned fin structure suitable for subsequent processing operations.

Abstract: A semiconductor device and a method for forming a device are presented. A wafer substrate having first and second regions is provided. The second region includes an inner region of the substrate while the first region includes an outer peripheral region from an edge of the substrate towards the inner region. A protection unit is provided above the substrate. The protection unit includes a region having a total width WT defined by outer and inner rings of the protection unit. The substrate is etched to form at least a trench in the second region of the substrate. The WT of the protection unit is sufficiently wide to protect the first region of the wafer substrate such that the first region is devoid of trench.

Abstract: A semiconductor device is manufactured by etching a semiconductor substrate including an active region, forming a bit line contact hole from which the active region is protruded, forming a first spacer exposing a top of the active region at each of an inner wall and a bottom of the bit line contact hole, forming a bit line contact plug and a bit line over the exposed active region, and forming a second spacer over the semiconductor substrate including not only the bit line contact plug but also the bit line.

Abstract: A method of manufacturing a semiconductor device includes forming trench isolation structures, exposing some of the trench isolation structures 28 to leave others 30 masked, and then selectively etching a buried layer to form a cavity 32 under an active device region 34. The active device region 34 is supported by support regions in the exposed trenches 28. The buried layer may be a SiGe layer on a Si substrate.

Abstract: A 3D IC based mobile system including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a plurality of thermal paths between the second mono-crystallized transistors and a heat removal apparatus, where at least one of the plurality of thermal paths includes a thermal contact adapted to conduct heat and not conduct electricity; and a heat spreader layer between the second layer and the at least one metal layer.

Abstract: A method for manufacturing a silicon-oxide-nitride-oxide-silicon non-volatile memory cell includes following steps. An implant region is formed in a substrate. A first oxide layer, a nitride layer, and a second oxide layer are formed and stacked on the substrate. A density of the second oxide layer is higher than a density of the first oxide layer. A first photoresist pattern is formed on the second oxide layer and corresponding to the implant region. A first wet etching process is then performed to form an oxide hard mask. A second wet etching process is performed to remove the nitride layer exposed by the oxide hard mask to form a nitride pattern. A cleaning process is then performed to remove the oxide hard mask and the first oxide layer exposed by the nitride pattern, and a gate oxide layer is then formed on the nitride pattern.

Abstract: An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.

Abstract: Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. Additionally, the active devices may have a two-step gate oxide, wherein a lower portion of the gate oxide has a thickness T2 that is larger than the thickness T1 of an upper portion of the gate oxide. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A nonvolatile memory device includes a substrate, an elongate isolation region including a field insulation film disposed in a trench in the substrate, and a word line crossing the insulation region and including a tunneling insulation layer on an active region of the substrate adjacent the isolation region, a charge storage layer on the tunneling insulation layer and a blocking insulation layer on the charge storage layer. A first plane index of a bottom surface of the trench has a first interface trap density and a second plane index of a sidewall of the trench has a second interface trap density equal to or less than the first interface trap density. In some embodiments, the first plane index may be (100) and the second plane index may be (100) or (310).

Abstract: A method for forming a modified low-k SiOCH film on a substrate, includes: providing a low-k SiOCH film formed on a substrate by flowable CVD; exposing the low-k SiOCH film to a gas containing a Si—N bond in its molecule without applying electromagnetic energy to increase Si—O bonds and/or Si—C bonds in the film; and then curing the low-k SiOCH film.

Abstract: Methods of fabricating a semiconductor device include forming a field trench in a silicon substrate, forming a first oxide layer in the field trench, forming a first thinned oxide layer by partially removing a surface of the first oxide layer, and forming a first nitride layer on the first thinned oxide layer.

Abstract: A method of making shallow trench isolation (STI) structures includes forming a first opening in a substrate and filling the first opening with silicon oxide to form a first STI structure. The method further includes doping a top surface of the silicon oxide with carbon, wherein a bottom portion of the silicon oxide is free of carbon. The method further includes planarizing the silicon oxide so that the top surface of the silicon oxide is at substantially a same level as a surface of the substrate surrounding the silicon oxide.

Abstract: An isolation region gap fill method comprises depositing a first dielectric material over a semiconductor device through a flowable deposition process or other gap fill deposition processes, wherein the semiconductor device includes a first FinFET comprising a plurality of first fins and a second FinFET comprising a plurality of second fins. The method further comprises removing the first dielectric material between the first FinFET and the second FinFET to form an inter-device gap, depositing a second dielectric material into the inter-device gap and applying an annealing process to the semiconductor device.

Abstract: One illustrative method disclosed herein includes, among other things, forming first, second and third fins that are arranged side-by-side, forming a recessed layer of insulating material in a plurality of trenches, after recessing the layer of insulating material, masking the first and second fins while exposing a portion of the axial length of the second fin, removing the exposed portion of the second fin so as to thereby define a cavity in the recessed layer of insulating material, forming an SDB isolation structure in the cavity, wherein the SDB isolation structure has an upper surface that is positioned above the recessed upper surface of the recessed layer of insulating material, removing the masking layer, and forming a gate structure for a transistor above the SDB isolation structure.

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

Abstract: A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. A via is defined in the insulating layers above the intermediate insulating layer. A channel is created for etch with a sacrificial spacer. A pore is defined in the intermediate insulating layer. All insulating layers above the intermediate insulating layer are removed, and the entirety of the remaining pore is filled with phase change material. An upper electrode is formed above the phase change material.

Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of (b) forming, on a back face of a dummy substrate and back faces of a plurality of semiconductor substrates, inorganic films having such thicknesses as to be resistant to a temperature of a thermal oxidizing treatment or a heat treatment and to sufficiently decrease an amount of oxidation or reducing gaseous species to reach the back faces of the dummy substrate and the plurality of semiconductor substrates, (c) disposing the dummy substrate and the plurality of semiconductor substrates in a lamination with surfaces turned in the same direction at an interval from each other, and (d) carrying out a thermal oxidizing treatment or post annealing over the surfaces of the semiconductor substrates in an oxidation gas atmosphere or a reducing gas atmosphere after the steps (b) and (c).

Abstract: Low capacitance finFET gate structures and methods of manufacturing. The method includes forming a layer of material on a substrate. The method further includes forming a dummy gate structure on the substrate which abuts the layer of material. The method further includes forming at least one spacer adjacent to the dummy gate structure and the layer of material. The method further includes removing the dummy gate structure and at least a portion of the layer of material to form an opening with a varying length. The method further includes forming a replacement gate structure with varying length by depositing gate material in the opening with the varying length.

Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound. The silicon compound includes a silicon atom, an atomic group having an amino group combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.