With Epitaxial Deposition Of Semiconductor In Groove Patents (Class 438/44)
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Patent number: 7977706Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.Type: GrantFiled: August 13, 2010Date of Patent: July 12, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Anthony J. Lochtefeld
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Patent number: 7968363Abstract: A manufacture method for zinc oxide (ZnO) based semiconductor crystal includes providing a substrate having a Zn polarity plane; and reacting at least zinc (Zn) and oxygen (O) on the Zn polarity plane of said substrate to grow ZnO based semiconductor crystal on the Zn polarity plane of said substrate in a Zn rich condition. (a) An n-type ZnO buffer layer is formed on a Zn polarity plane of a substrate. (b) An n-type ZnO layer is formed on the surface of the n-type ZnO buffer layer. (c) An n-type ZnMgO layer is formed on the surface of the n-type ZnO layer. (d) A ZnO/ZnMgO quantum well layer is formed on the surface of the n-type ZnMgO layer, by alternately laminating a ZnO layer and a ZnMgO layer. @(e) A p-type ZnMgO layer is formed on the surface of the ZnO/ZnMgO quantum well layer. (f) A p-type ZnO layer is formed on the surface of the p-type ZnMgO layer. @(g) An electrode is formed on the n-type ZnO layer and p-type ZnO layer. The n-type ZnO layer is formed under a Zn rich condition at the step (b).Type: GrantFiled: March 29, 2010Date of Patent: June 28, 2011Assignee: Stanley Electric Co., Ltd.Inventors: Hiroshi Kotani, Michihiro Sano, Hiroyuki Kato, Akio Ogawa
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Patent number: 7968356Abstract: Provided are a light-emitting element, a light-emitting device including the same, and methods of fabricating the light-emitting element and the light-emitting device. The light-emitting element includes a substrate on which a dome pattern is formed and a light-emitting structure conformally formed on the dome pattern. The light-emitting structure includes a first conductive layer of a first conductivity type, a light-emitting layer, and a second conductive layer of a second conductivity type sequentially stacked on the substrate. The light-emitting element also includes a first electrode formed on the first conductive layer and a second electrode formed on the second conductive layer.Type: GrantFiled: August 10, 2009Date of Patent: June 28, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Yu-Sik Kim
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Patent number: 7968361Abstract: A method for producing a gallium nitride based compound semiconductor light emitting device which is excellent in terms of the light emitting properties and the light emission efficiency and a lamp is provided. In such a method for producing a gallium nitride based compound semiconductor light emitting device, which is a method for producing a GaN based semiconductor light emitting device having at least a buffer layer, an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on a translucent substrate, on which an uneven pattern composed of a convex shape and a concave shape is formed, the buffer layer is formed by a sputtering method conducted in an apparatus having a pivoted magnetron magnetic circuit and the buffer layer contains AlN, ZnO, Mg, or Hf.Type: GrantFiled: March 30, 2007Date of Patent: June 28, 2011Assignee: Showa Denko K.K.Inventors: Hiroshi Osawa, Hironao Shinohara
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Patent number: 7960292Abstract: A zinc oxide (ZnO) film is fabricated. Metal-organic chemical vapor deposition (MOCVD) is used to obtain the film with few defects, high integrity and low cost through an easy procedure. The ZnO film above a silicon substrate has a matching crystal orientation to the substrate. Thus, the ZnO film is fit for ultraviolet light-emitting diodes (UV LED), solar cells and related laser devices.Type: GrantFiled: May 2, 2009Date of Patent: June 14, 2011Assignee: Atomic Energy Council-Institute of Nuclear Energy ResearchInventor: Tsun-Neng Yang
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Patent number: 7955880Abstract: A method of producing a semiconductor optical device includes a first step of growing a stacked semiconductor layer including a first III-V group compound semiconductor layer for an active layer on a substrate; a second step of forming a silicon oxide film on the stacked semiconductor layer, the silicon oxide film having a predetermined film stress and a predetermined thickness; a third step of forming a strip-shaped groove in the silicon oxide film by etching the silicon oxide film, using a resist pattern formed on the silicon oxide film, until a surface of the stacked semiconductor layer is exposed; and a fourth step of growing a second III-V group compound semiconductor layer in the groove using the silicon oxide film as a selective mask.Type: GrantFiled: June 10, 2009Date of Patent: June 7, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Toshio Nomaguchi, Tetsuya Hattori, Kazunori Fujimoto
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Patent number: 7955883Abstract: Interdigitated electrode arrays are very promising devices for multi-parameter (bio)sensing, for example the label-free detection of nucleic acid hybridization for diagnostic applications. The current disclosure provides an innovative method for the affordable manufacturing of polymer-based arrays of interdigitated electrodes with ?m-dimensions. The method is based on a combination of an appropriate three-dimensional structure and a single and directional deposition of conductive material. The three-dimensional structure can be realized in a polymer material using a molding step, for which the molds are manufactured by electroplating as a reverse copy of a silicon master structure. In order to ensure sufficient electrical isolation and individual, but convenient, accessibility of the sensors in the array, the interdigitated electrode regions need to be complemented with specific features on the three-dimensional structure. Combined with the use of e.g.Type: GrantFiled: September 6, 2006Date of Patent: June 7, 2011Assignees: IMEC, InnogeneticsInventors: Wim Laureyn, Jan Suls, Paul Jacobs
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Patent number: 7947569Abstract: A method for producing a semiconductor including a material layer. In one embodiment a trench is produced having two opposite sidewalls and a bottom, in a semiconductor body. A foreign material layer is produced on a first one of the two sidewalls of the trench. The trench is filled by epitaxially depositing a semiconductor material onto the second one of the two sidewalls and the bottom of the trench.Type: GrantFiled: June 30, 2008Date of Patent: May 24, 2011Assignee: Infineon Technologies Austria AGInventors: Anton Mauder, Frank Pfirsch, Rudolf Berger, Stefan Sedlmaier, Wolfgang Lehnert, Raimund Foerg
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Publication number: 20110108800Abstract: A semiconductor device includes a substrate comprising a first surface having a first orientation and a second surface having a second orientation and a plurality of III-V nitride layers on the substrate, wherein the plurality of III-V nitride layers are configured to emit light when an electric current is produced in one or more of the plurality of III-V nitride layers.Type: ApplicationFiled: June 24, 2008Publication date: May 12, 2011Inventor: Shaoher X. Pan
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Patent number: 7939448Abstract: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.Type: GrantFiled: September 23, 2010Date of Patent: May 10, 2011Assignee: Renesas Electronics CorporationInventors: Tsutomu Okazaki, Motoi Ashida, Hiroji Ozaki, Tsuyoshi Koga, Daisuke Okada
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Patent number: 7935554Abstract: Provided are a semiconductor light emitting device having a nano pattern and a method of manufacturing the semiconductor light emitting device. The semiconductor light emitting device includes: a semiconductor layer comprising a plurality of nano patterns, wherein the plurality of nano patterns are formed inside the semiconductor layer; and an active layer formed on the semiconductor layer. The optical output efficiency is increased and inner defects of the semiconductor light emitting device are reduced.Type: GrantFiled: March 19, 2009Date of Patent: May 3, 2011Assignee: Samsung LED Co., Ltd.Inventors: Jeong-wook Lee, Youn-joon Sung, Ho-sun Paek, Hyun-soo Kim, Joo-sung Kim, Suk-ho Yoon
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Patent number: 7927977Abstract: A method of making a semiconductor device includes forming a first layer comprising a seed material over an underlying layer, forming a second layer comprising a sacrificial material over the first layer, the sacrificial material being different from the seed material, patterning the first layer and the second layer into a plurality of separate features, forming an insulating filling material between the plurality of the separate features, removing the sacrificial material from the separate features to form a plurality of openings in the insulating filling material such that the seed material is exposed in the plurality of openings, and growing a semiconductor material on the exposed seed material in the plurality of openings.Type: GrantFiled: July 15, 2009Date of Patent: April 19, 2011Assignee: SanDisk 3D LLCInventors: Raghuveer S. Makala, Vance Dunton, Yoichiro Tanaka, Steven Maxwell, Tong Zhang, Steven J. Radigan
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Patent number: 7903708Abstract: A nitride semiconductor laser device uses a substrate with low defect density, contains reduced strains inside a nitride semiconductor film, and thus offers a satisfactorily long useful life. On a GaN substrate (10) with a defect density as low as 106 cm?2 or less, a stripe-shaped depressed portion (16) is formed by etching. On this substrate (10), a nitride semiconductor film (11) is grown, and a laser stripe (12) is formed off the area right above the depressed portion (16). With this structure, the laser stripe (12) is free from strains, and the semiconductor laser device offers a long useful life. Moreover, the nitride semiconductor film (11) develops reduced cracks, resulting in a greatly increased yield rate.Type: GrantFiled: July 30, 2004Date of Patent: March 8, 2011Assignee: Sharp Kabushiki KaishaInventors: Takeshi Kamikawa, Eiji Yamada, Masahiro Araki, Yoshika Kaneko
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Patent number: 7901968Abstract: Some embodiments of the invention are related to manufacturing semiconductors. Methods and apparatuses are disclosed that provide thin and fully relaxed SiGe layers. In some embodiments, the presence of oxygen between a single crystal structure and a SiGe heteroepitaxial layer, and/or within the SiGe heteroepitaxial layer, allow the SiGe layer to be thin and fully relaxed. In some embodiments, a strained layer of Si can be deposited over the fully relaxed SiGe layer.Type: GrantFiled: March 23, 2006Date of Patent: March 8, 2011Assignee: ASM America, Inc.Inventors: Keith Doran Weeks, Paul D. Brabant
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Patent number: 7903710Abstract: A nitride semiconductor light-emitting device wherein a substrate or nitride semiconductor layer has a defect concentration region and a low defect density region other than the defect concentration region. A portion including the defect concentration region of the nitride semiconductor layer or substrate has a trench region deeper than the low defect density region. Thus by digging the trench in the defect concentration region, the growth detection is uniformized, and the surface planarity is improved. The uniformity of the characteristic in the wafer surface leads to improvement of the yield.Type: GrantFiled: February 19, 2010Date of Patent: March 8, 2011Assignees: Sharp Kabushiki Kaisha, Sumitomo Electric Industries, Ltd.Inventors: Takeshi Kamikawa, Yoshika Kaneko, Kensaku Motoki
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Patent number: 7903707Abstract: A nitride semiconductor light-emitting device wherein a substrate or nitride semiconductor layer has a defect concentration region and a low defect density region other than the defect concentration region. A portion including the defect concentration region of the nitride semiconductor layer or substrate has a trench region deeper than the low defect density region. Thus by digging the trench in the defect concentration region, the growth detection is uniformized, and the surface planarity is improved. The uniformity of the characteristic in the wafer surface leads to improvement of the yield.Type: GrantFiled: May 27, 2004Date of Patent: March 8, 2011Assignees: Sharp Kabushiki Kaisha, Sumitomo Electric Industries, Ltd.Inventors: Takeshi Kamikawa, Yoshika Kaneko, Kensaku Motoki
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Patent number: 7888779Abstract: There is provided a method of fabricating InGaAlN film on a silicon substrate, which comprises the following steps of forming a pattern structured having grooves and mesas on the silicon substrate, and depositing InGaAlN film on the surface of substrate, wherein the depth of the grooves is more than 6 nm, and the InGaAlN film formed on the mesas of both sides of the grooves are disconnected in the horizontal direction. The method may grow high quality, no crack and large area of InGaAlN film by simply treating the substrate. At the same time, there is also provided a method of fabricating InGaAlN light-emitting device by using the silicon substrate.Type: GrantFiled: April 14, 2006Date of Patent: February 15, 2011Assignee: Lattice Power (Jiangxi) CorporationInventors: Fengyi Jiang, Wenqing Fang, Li Wang, Chunlan Mo, Hechu Liu, Maoxing Zhou
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Patent number: 7875511Abstract: A CMOS structure includes an n-FET device comprising an n-FET channel region and a p-FET device comprising a p-FET channel region. The n-FET channel region includes a first silicon material layer located upon a silicon-germanium alloy material layer. The p-FET channel includes a second silicon material layer located upon a silicon-germanium-carbon alloy material layer. The silicon-germanium alloy material layer induces a desirable tensile strain within the n-FET channel. The silicon-germanium-carbon alloy material layer suppresses an undesirable tensile strain within the p-FET channel region. A silicon-germanium-carbon alloy material from which is comprised the silicon-germanium-carbon alloy material layer may be formed by selectively incorporating carbon into a silicon-germanium alloy material from which is formed the silicon-germanium alloy material layer.Type: GrantFiled: March 13, 2007Date of Patent: January 25, 2011Assignee: International Business Machines CorporationInventors: Liu Yaocheng, Ricardo A. Donaton, Kern Rim
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Patent number: 7867846Abstract: An Organic Light Emitting Display (OLED) and its fabrication method has a pixel defining layer provided on a first electrode which is formed with a gas vent groove to allow gas to vent when the pixel defining layer is being formed, so that gas is not left in a pixel but vented when a donor film is laminated by a Laser-Induced Thermal Imaging (LITI) method, thereby decreasing edge open failures.Type: GrantFiled: July 13, 2010Date of Patent: January 11, 2011Assignee: Samsung Mobile Display Co., Ltd.Inventors: Tae-Min Kang, Seong-Taek Lee, Myung-Won Song, Mu-Hyun Kim, Byung-Doo Chin, Jae-Ho Lee
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Patent number: 7858414Abstract: A method of manufacturing a nitride semiconductor device includes the steps of forming a groove on a surface of a first substrate by scribing, and forming a nitride semiconductor layer on the surface where the groove is formed. In addition, the method includes the steps of bonding the nitride semiconductor layer and a second substrate together and separating the nitride semiconductor layer and the first substrate from each other. With this manufacturing method, a nitride semiconductor device can be obtained with high yield.Type: GrantFiled: March 17, 2006Date of Patent: December 28, 2010Assignee: Sharp Kabushiki KaishaInventors: Mayuko Fudeta, Satoshi Komada
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Patent number: 7858417Abstract: A vertical cavity surface emitting laser having a dielectric gain guide. The gain guide may provide current confinement, device isolation and possibly optical confinement. The first mirror and an active region may be grown. A pattern may be placed on or near the active region. A dielectric material may be deposited on the pattern and the pattern may be removed resulting in a gain guide. Then a top mirror may be grown on the gain guide. This structure with the dielectric gain guide may have specific characteristics and/or additional features.Type: GrantFiled: October 2, 2007Date of Patent: December 28, 2010Assignee: Finisar CorporationInventors: Jae-Hyun Ryou, Gyoungwon Park
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Patent number: 7838372Abstract: Methods of manufacturing semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming recesses in a first region and a second region of a workpiece. The first region of the workpiece is masked, and the recesses in the second region of the workpiece are filled with a first semiconductive material. The second region of the workpiece is masked, and the recesses in the first region of the workpiece are filled with a second semiconductive material.Type: GrantFiled: May 22, 2008Date of Patent: November 23, 2010Assignees: Infineon Technologies AG, Chartered Semiconductor Manufacturing, Ltd., International Business Machines Corporation, Samsung Electronics Co., Ltd.Inventors: Jin-Ping Han, Jong Ho Yang, Chung Woh Lai, Henry Utomo
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Patent number: 7821017Abstract: The invention discloses a method for fabricating a light-emitting diode. In an embodiment of the invention, the method comprises the following steps of (a) preparing a substrate; (b) forming an epitaxial layer on the substrate, wherein the epitaxial layer has an upper surface; (c) forming a mask layer on a first region of the upper surface of the epitaxial layer; (d) forming a semiconductor multi-layer structure on a second region of the upper surface of the epitaxial layer, wherein the second region is distinct from the first region; (e) removing the mask layer formed on the first region of the upper surface of the epitaxial layer; and (f) forming an electrode on the first region of the upper surface of the epitaxial layer.Type: GrantFiled: April 20, 2009Date of Patent: October 26, 2010Assignee: HUGA Optotech Inc.Inventors: Chi-Shen Lee, Su-Hui Lin
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Publication number: 20100255621Abstract: A light emitting element having a recess-protrusion structure on a substrate is provided. A semiconductor light emitting element 100 has a light emitting structure of a semiconductor 20 on a first main surface of a substrate 10. The first main surface of the substrate 10 has substrate protrusion portion 11, the bottom surface 14 of each protrusion is wider than the top surface 13 thereof in a cross-section, or the top surface 13 is included in the bottom surface 14 in a top view of the substrate. The bottom surface 14 has an approximately polygonal shape, and the top surface 13 has an approximately circular or polygonal shape with more sides than that of the bottom surface 14.Type: ApplicationFiled: June 15, 2010Publication date: October 7, 2010Inventors: Shunsuke MINATO, Junya Narita, Yohei Wakai, Yukio Narukawa, Motokazu Yamada
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Patent number: 7799593Abstract: The present invention discloses a light emitting diode structure and a method for fabricating the same. In the present invention, a substrate is placed in a solution to form a chemical reaction layer. Next, the substrate is etched to form a plurality of concave zones and a plurality of convex zones with the chemical reaction layer overhead. Next, the chemical reaction layer is removed to form an irregular geometry of the concave zones and convex zones on the surface of the substrate. Then, a semiconductor light emitting structure is epitaxially formed on the surface of the substrate. Thereby, the present invention can achieve a light emitting diode structure having improved internal and external quantum efficiencies.Type: GrantFiled: August 10, 2009Date of Patent: September 21, 2010Assignee: Tekcore Co., Ltd.Inventors: Chia-Ming Lee, Hung-Cheng Lin, Jen-Inn Chyi
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Patent number: 7799592Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.Type: GrantFiled: September 26, 2007Date of Patent: September 21, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Anthony J. Lochtefeld
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Publication number: 20100213436Abstract: An ultra-violet light-emitting device and method for fabricating an ultraviolet light emitting device, 12, (LED or an LD) with an AlInGaN multiple-quantum-well active region, 10, exhibiting stable cw-powers. The device includes a non c-plane template with an ultraviolet light-emitting structure thereon. The template includes a first buffer layer, 321, on a substrate, 100, then a second buffer layer, 421, on the first preferably with a strain-relieving layer, 302, in both buffer layers. Next there is a semi-conductor layer having a first type of conductivity, 500, followed by a layer providing a quantum-well region, 600. Another semi-conductor layer, 700, having a second type of conductivity is applied next. Two metal contacts, 980 and 990, are applied to this construction, one to the semiconductor layer having the first type of conductivity and the other to the semiconductor layer having the second type of conductivity, to complete the light emitting device.Type: ApplicationFiled: May 8, 2008Publication date: August 26, 2010Inventor: Asif Khan
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Patent number: 7781245Abstract: A process for the semiconductor laser diode is disclosed, which prevents the abnormal growth occurred at the second growth for the burying region of the buried hetero structure. The ICP (Induction-Coupled Plasma) CVD apparatus forms a silicon oxide file with a thickness of above 2 ?m as adjusting the bias power PBIAS. Patterning the silicon oxide mask and dry-etching the semiconductor layers, a mesa structure including the active layer may be formed. As leaving the patterned silicon oxide film, the second growth for the burying region buries the mesa structure. The residual stress of the silicon oxide film is ?250 to ?150 MPa at a room temperature, while, it is ?200 to 100 MPa at temperatures from 500 to 700° C.Type: GrantFiled: January 6, 2009Date of Patent: August 24, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takeshi Kishi, Tetsuya Hattori, Kazunori Fujimoto
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Patent number: 7781796Abstract: A nitride semiconductor laser element includes a substrate and a nitride semiconductor layer in which a first semiconductor layer, an active layer, and a second semiconductor layer are laminated in this order on the substrate. At least one of the first semiconductor layer and the second semiconductor layer includes a first section forming recessed and raised portions and a second section embedding the recessed and raised portions of the first section. A region with a higher aluminum mixed crystal ratio than the second section that embeds the recessed and raised portions is disposed on top faces of the raised portions. The nitride semiconductor layer defines resonant planes, and the recessed and raised portions are formed in a shape of stripes that extend substantially parallel to the resonant planes.Type: GrantFiled: June 14, 2007Date of Patent: August 24, 2010Assignee: Nichia CorporationInventors: Shingo Masui, Kazutaka Tsukayama
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Patent number: 7754513Abstract: Latch-up resistant semiconductor structures formed on a hybrid substrate and methods of forming such latch-up resistant semiconductor structures. The hybrid substrate is characterized by first and second semiconductor regions that are formed on a bulk semiconductor region. The second semiconductor region is separated from the bulk semiconductor region by an insulating layer. The first semiconductor region is separated from the bulk semiconductor region by a conductive region of an opposite conductivity type from the bulk semiconductor region. The buried conductive region thereby the susceptibility of devices built using the first semiconductor region to latch-up.Type: GrantFiled: February 28, 2007Date of Patent: July 13, 2010Assignee: International Business Machines CorporationInventors: Jack Allan Mandelman, William Robert Tonti
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Patent number: 7750338Abstract: A semiconductor includes a semiconductor substrate, a gate stack on the semiconductor substrate, and a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor includes a first stressor region and a second stressor region on the first stressor region, wherein the second stressor region extends laterally closer to a channel region underlying the gate stack than the first stressor region.Type: GrantFiled: December 5, 2006Date of Patent: July 6, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Yin-Pin Wang
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Patent number: 7749786Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.Type: GrantFiled: March 14, 2007Date of Patent: July 6, 2010Assignee: Micron Technology, Inc.Inventor: David H. Wells
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Patent number: 7741138Abstract: A semiconductor device and fabricating method thereof are disclosed, by which channel mobility is enhanced and by which effect of flicker noise can be minimized. Embodiments relate to a method of fabricating a semiconductor device which includes forming a first epi-layer over a substrate, forming a second epi-layer over the first epi-layer, forming a gate electrode over the second epi-layer, forming a spacer over both sides of the gate electrode, etching an area adjacent both sides of the spacer to a depth of the substrate, forming an LDD region in a region under the spacer, and forming a third epi-layer for a source/drain region over the etched area adjacent both of the sides of the spacer.Type: GrantFiled: August 24, 2008Date of Patent: June 22, 2010Assignee: Dongbu HiTek Co., Ltd.Inventor: Yong-Soo Cho
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Patent number: 7736923Abstract: An optical semiconductor device includes: a first conductivity type first semiconductor region; a first conductivity type second semiconductor region formed on the first semiconductor region; a second conductivity type third semiconductor region formed on the second semiconductor region; a photodetector section formed of the second semiconductor region and the third semiconductor region; a micro mirror formed of a trench formed selectively in a region of the first semiconductor region and the second semiconductor region except the photodetector section; and a semiconductor laser element held on the bottom face of the trench. A first conductivity type buried layer of which impurity concentration is higher than those of the first semiconductor region and the second semiconductor region is selectively formed between the first semiconductor region and the second semiconductor region in the photodetector section.Type: GrantFiled: April 7, 2008Date of Patent: June 15, 2010Assignee: Panasonic CorporationInventor: Takaki Iwai
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Patent number: 7736925Abstract: A method of manufacturing a nitride-based semiconductor laser diode that can minimize optical absorption on a cavity mirror plane and improve the surface roughness of the cavity mirror plane is provided. The method includes the steps of: forming on a (0001) GaN (gallium nitride) substrate having at least two masks spaced apart by a distance equal to a laser cavity length in stripes that extend along the <11-20> direction; growing an n-GaN layer on the GaN substrate between the masks so that two (1-100) edges of the n-GaN layer are thicker than the remaining regions thereof; sequentially stacking an n-clad layer, an active layer, and a p-clad layer on the n-GaN layer to form an edge-emitting laser cavity structure in which laser light generated in the active layer passes through a region of the n-clad layer aligned laterally with the active layer and is output; and etching a (1-100) plane of the laser cavity structure to form a cavity mirror plane.Type: GrantFiled: June 8, 2006Date of Patent: June 15, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Tan Sakong, Youn-joon Sung, Ho-sun Paek
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Patent number: 7713769Abstract: The present invention discloses a light emitting diode structure and a method for fabricating the same. In the present invention, a substrate is placed in a solution to form a chemical reaction layer on carved regions; the carved region is selectively etched to form a plurality of concave zones and form a plurality of convex zones; a semiconductor layer structure is epitaxially grown on the element regions and carved regions of the substrate; the semiconductor layer structure on the element regions is fabricated into a LED element with a photolithographic process.Type: GrantFiled: December 21, 2007Date of Patent: May 11, 2010Assignee: Tekcore Co., Ltd.Inventors: Hung-Cheng Lin, Chia-Ming Lee, Jen-Inn Chyi
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Patent number: 7696019Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A preferred embodiment includes a semiconductor device comprising a workpiece, the workpiece including a first region and a second region proximate the first region. A first material is disposed in the first region, and at least one region of a second material is disposed within the first material in the first region, the second material comprising a different material than the first material. The at least one region of the second material increases a first stress of the first region.Type: GrantFiled: March 9, 2006Date of Patent: April 13, 2010Assignee: Infineon Technologies AGInventor: Jin-Ping Han
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Manufacturing method of nitride substrate, nitride substrate, and nitride-based semiconductor device
Patent number: 7691732Abstract: A manufacturing method of a nitride substrate includes the steps of preparing a ground substrate; forming a mask on the ground substrate; placing the ground substrate in a reactor, and heating the ground substrate to a temperature of 850° C. to 1100° C. In the step of heating the ground substrate, HCl and NH3 are supplied into the reactor so that partial pressure PHCl satisfies (1.5+0.0005 p) kPa?PHCl?(4+0.0005 p) kPa and partial pressure PNH3 satisfies (15?0.0009 p) kPa?PNH3?(26?0.0017 p) kPa, whereby an AlxGayIn1-x-yN crystal (0?x<1, 0<y?1) is grown, and whereby a ridge-valley structure including a plurality of ridges and valleys parallel to one another is formed. The AlxGayIn1-x-yN crystal is grown so that the ridge-valley structure is not buried while a height of the valleys from the ground substrate is allowed to exceed 2.5 (p?s).Type: GrantFiled: June 18, 2008Date of Patent: April 6, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takuji Okahisa, Hideaki Nakahata, Koji Uematsu -
Patent number: 7692200Abstract: A nitride semiconductor light-emitting device wherein a substrate or nitride semiconductor layer has a defect concentration region and a low defect density region other than the defect concentration region. A portion including the defect concentration region of the nitride semiconductor layer or substrate has a trench region deeper than the low defect density region. Thus by digging the trench in the defect concentration region, the growth detection is uniformized, and the surface planarity is improved. The uniformity of the characteristic in the wafer surface leads to improvement of the yield.Type: GrantFiled: December 3, 2008Date of Patent: April 6, 2010Assignees: Sharp Kabushiki Kaisha, Sumitomo Electric Industries, Ltd.Inventors: Takeshi Kamikawa, Yoshika Kaneko, Kensaku Motoki
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Patent number: 7662672Abstract: A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed.Type: GrantFiled: May 19, 2008Date of Patent: February 16, 2010Assignees: ChipMos Technologies (Bermuda) Ltd., ChipMos Technologies Inc.Inventor: Hung-Tsun Lin
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Patent number: 7653281Abstract: Waveguide(s) (130) including at least partially buried channels) (120) within substrate(s) (100) having at least one substantially planar surface (110) are disclosed. According to some embodiments at least part of the channel (120) is located beneath at least a portion of the substrate (100). According to some embodiments the waveguide channel (120) includes a substantially transparent core (140) and optional cladding (160) extending through the channel (120). Alternately, an inner surface of the channel (120) is highly reflective. Furthermore, structures for use as waveguides (130) and/or as microchannels for fluid flow are disclosed herein. Also disclosed are production methods for such waveguides and said structures (130) and said structures, and methods of using such waveguides (130).Type: GrantFiled: September 4, 2005Date of Patent: January 26, 2010Assignee: Ramot At Tel-Aviv University Ltd.Inventors: Stanislav Stepanov, Shlomo Ruschin
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Publication number: 20090317929Abstract: A method of producing a semiconductor optical device includes a first step of growing a stacked semiconductor layer including a first III-V group compound semiconductor layer for an active layer on a substrate; a second step of forming a silicon oxide film on the stacked semiconductor layer, the silicon oxide film having a predetermined film stress and a predetermined thickness; a third step of forming a strip-shaped groove in the silicon oxide film by etching the silicon oxide film, using a resist pattern formed on the silicon oxide film, until a surface of the stacked semiconductor layer is exposed; and a fourth step of growing a second III-V group compound semiconductor layer in the groove using the silicon oxide film as a selective mask.Type: ApplicationFiled: June 10, 2009Publication date: December 24, 2009Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Toshio Nomaguchi, Tetsuya Hattori, Kazunori Fujimoto
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Publication number: 20090298213Abstract: The present invention discloses a light emitting diode structure and a method for fabricating the same. In the present invention, a substrate is placed in a solution to form a chemical reaction layer. Next, the substrate is etched to form a plurality of concave zones and a plurality of convex zones with the chemical reaction layer overhead. Next, the chemical reaction layer is removed to form an irregular geometry of the concave zones and convex zones on the surface of the substrate. Then, a semiconductor light emitting structure is epitaxially formed on the surface of the substrate. Thereby, the present invention can achieve a light emitting diode structure having improved internal and external quantum efficiencies.Type: ApplicationFiled: August 10, 2009Publication date: December 3, 2009Inventors: Chia-Ming LEE, Hung-Cheng Lin, Jen-Inn Chyi
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Patent number: 7618836Abstract: A method for manufacturing a semiconductor optical device comprises: forming a groove on a first semiconductor layer; forming a second semiconductor layer containing aluminum in the groove; forming a third semiconductor layer on the first semiconductor layer and the second semiconductor layer; forming an insulating layer on the third semiconductor layer covering the region opposite the second semiconductor layer; forming a stripe-shaped structure by etching the first semiconductor layer and the third semiconductor layer without exposing the second semiconductor layer, using the insulating layer as a mask; and burying the stripe-shaped structure with burying layers.Type: GrantFiled: May 1, 2008Date of Patent: November 17, 2009Assignee: Mitsubishi Electric CorporationInventor: Go Sakaino
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Patent number: 7615390Abstract: The present invention provides a method of depositing epitaxial layers based on Group IV elements on a silicon substrate by Chemical Vapor Deposition, wherein nitrogen or one of the noble gases is used as a carrier gas, and the invention further provides a Chemical Vapor Deposition apparatus (10) comprising a chamber (12) having a gas input port (14) and a gas output port (16), and means (18) for mounting a silicon substrate within the chamber (12), said apparatus further including a gas source connected to the input port and arranged to provide nitrogen or a noble gas as a carrier gas.Type: GrantFiled: August 13, 2003Date of Patent: November 10, 2009Assignee: NXP B.V.Inventors: Philippe Meunier-Beillard, Mathieu Rosa Jozef Caymax
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Patent number: 7598105Abstract: The present invention discloses a light emitting diode structure and a method for fabricating the same. In the present invention, a substrate is placed in a solution to form a chemical reaction layer. Next, the substrate is etched to form a plurality of concave zones and a plurality of convex zones with the chemical reaction layer overhead. Next, the chemical reaction layer is removed to form an irregular geometry of the concave zones and convex zones on the surface of the substrate. Then, a semiconductor light emitting structure is epitaxially formed on the surface of the substrate. Thereby, the present invention can achieve a light emitting diode structure having improved internal and external quantum efficiencies.Type: GrantFiled: December 21, 2007Date of Patent: October 6, 2009Assignee: Tekcore Co., Ltd.Inventors: Chia-Ming Lee, Hung-Cheng Lin, Jen-Inn Chyi
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Patent number: 7588951Abstract: A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer over the first major surface of the first device, forming a via in the first dielectric layer, forming a seed layer within the via and over a portion of the first dielectric layer, physically coupling a connector to the seed layer, and plating a conductive material over the seed layer to form a first interconnect in the first via and over a portion of the first dielectric layer.Type: GrantFiled: November 17, 2006Date of Patent: September 15, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Marc A. Mangrum, Kenneth R. Burch
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Patent number: 7569461Abstract: In a method for fabricating a nitride-based compound layer, first, a GaN substrate is prepared. A mask layer with a predetermined pattern is formed on the GaN substrate to expose a partial area of the GaN substrate. Then a buffer layer is formed on the partially exposed GaN substrate. The buffer layer is made of a material having a 10% or less lattice mismatch with GaN. Thereafter, the nitride-based compound is grown laterally from a top surface of the buffer layer toward a top surface of the mask layer and the nitride-based compound layer is vertically grown to a predetermined thickness. Also, the mask layer and the buffer layer are removed via wet-etching to separate the nitride-based compound layer from the GaN substrate.Type: GrantFiled: June 21, 2006Date of Patent: August 4, 2009Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Soo Min Lee, Cheol Kyu Kim, Jaeun Yoo, Sung Hwan Jang, Masayoshi Koike
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Patent number: 7560298Abstract: Methods are disclosed for producing a tunable vertical cavity surface emitting laser (VCSEL) using photonic crystals and an electrostrictive material that includes a hologram with a narrow filter function. Photonic crystals are formed such that the active region of the VCSEL is bounded by the photonic crystals. The photonic crystals have a periodic cavity structure that reflects light of certain wavelengths through the active region of the VCSEL such that laser light at the wavelengths is generated. The periodic cavity structure includes a central defect that does not include any cavities. The single mode is emitted through the central defect. The electrostrictive material that includes a hologram makes the VCSEL tunable because the shape of the electrostrictive material changes when an electric field is applied. The filter function of the hologram thus changes as well in response to the electric field such that the VCSEL is tunable.Type: GrantFiled: May 21, 2004Date of Patent: July 14, 2009Assignee: Finisar CorporationInventor: Jan Lipson
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Publication number: 20090159871Abstract: The present invention discloses a light emitting diode structure and a method for fabricating the same. In the present invention, a substrate is placed in a solution to form a chemical reaction layer. Next, the substrate is etched to form a plurality of concave zones and a plurality of convex zones with the chemical reaction layer overhead. Next, the chemical reaction layer is removed to form an irregular geometry of the concave zones and convex zones on the surface of the substrate. Then, a semiconductor light emitting structure is epitaxially formed on the surface of the substrate. Thereby, the present invention can achieve a light emitting diode structure having improved internal and external quantum efficiencies.Type: ApplicationFiled: December 21, 2007Publication date: June 25, 2009Inventors: Chia-Ming LEE, Hung-Cheng Lin, Jen-Inn Chyi