With Epitaxial Deposition Of Semiconductor In Groove Patents (Class 438/44)
  • Patent number: 6815241
    Abstract: Included in the invention are laminates having layers of group III-V materials having low dislocation densities, semiconductor devices fabricated using low dislocation density group III-V layers, and methods for making these structures. Some of the inventions are concerned with GaN layers, GaN semiconductor devices, and semiconductor lasers fabricated from GaN materials. Detailed information on various example embodiments of the inventions are provided in the Detailed Description below, and the inventions are defined by the appended claims.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: November 9, 2004
    Assignee: Cao Group, Inc.
    Inventor: Tao Wang
  • Patent number: 6806115
    Abstract: A method for producing a semiconductor light emitting device includes the steps of forming a mask layer having a plurality of openings on a surface of a silicon substrate; and forming a column-like multi-layer structure including a light emitting layer in each of the plurality of openings with nitride semiconductor materials. A width between two adjacent openings of the plurality of openings of the mask layer is 10 &mgr;m or less.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: October 19, 2004
    Assignees: Sharp Kabushiki Kaisha
    Inventors: Norikatsu Koide, Junji Yamamoto, Tsuyoshi Dohkita, Nobuhiko Sawaki, Yoshio Honda, Yousuke Kuroiwa, Masahito Yamaguchi
  • Patent number: 6803309
    Abstract: A method for forming an adhesion/barrier liner with reduced fluorine contamination to improve adhesion and a specific contact resistance of metal interconnects including providing a semiconductor wafer having a process surface including an etched opening extending through a dielectric insulating layer thickness and in closed communication with a conductive underlayer surface; pre-heating the semiconductor wafer in a plasma reactor to a pre-heating temperature of at least about 400° C.; cleaning the etched opening according to a plasma assisted reactive pre-cleaning process (RPC) comprising nitrogen trifluoride (NF3); and, blanket depositing at least a first adhesion/barrier layer over the etched opening substantially free of fluorine containing residue.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: October 12, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Shih-Wei Chou, Chii-Ming Wu
  • Patent number: 6790697
    Abstract: An optical semiconductor device includes an optical semiconductor element, a semiconductor region, and a buried layer. The optical semiconductor element is formed on a semiconductor substrate. The semiconductor region opposes the optical semiconductor element and essentially surrounds the optical semiconductor element to form walls. The buried layer is arranged between the walls of the semiconductor region and the optical semiconductor element and formed by vapor phase epitaxy. In this optical semiconductor device, a distance between the wall of the semiconductor region and a side wall of the optical semiconductor element is larger in a portion in which the growth rate of the vapor phase epitaxy in a horizontal direction from the side wall of the optical semiconductor element and the wall of the semiconductor region is higher.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: September 14, 2004
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Fumihiko Kobayashi, Takeo Miyazawa, Hidefumi Mori, Jun-ichi Nakano
  • Patent number: 6787383
    Abstract: The light-emitting device 100 has an ITO electrode layer 8 for applying drive voltage for light emission to a light emitting layer section 24, where the light from the light emitting layer section 24 is extracted as being passed through the ITO electrode layer 8. Between the light emitting layer section 24 and the ITO electrode layer 8, an electrode contact layer 7 composed of In-containing GaAs is located so as to contact with such ITO electrode layer 8, where occupied areas and unoccupied areas for the electrode contact layer 7 are arranged in a mixed manner on the contact interface with the transparent electrode layer 8. The electrode contact layer 7 can be obtained by annealing a stack 13, which comprises a GaAs layer 7″ formed on the light emitting layer section 24 and the ITO electrode layer 8 formed so as to contact with the GaAs layer 7″, to thereby allow In to diffuse from the ITO electrode layer to the GaAs layer 7″.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: September 7, 2004
    Assignees: Shin-Etsu Hanotai Co., Ltd., Nanoteco Corporation
    Inventors: Shunichi Ikeda, Masato Yamada, Nobuhiko Noto, Shinji Nozaki, Kazuo Uchida, Hiroshi Morisaki
  • Patent number: 6756290
    Abstract: A method for making a semiconductor device having a pattern of highly doped regions located some distance apart in a semiconductor substrate and regions of low doping located between the highly doped regions. A diffusion barrier material is applied to the semiconductor substrate at the location of the regions of low doping by imprinting with the barrier material in the pattern of the regions of low doping. The doping material is applied after or before imprinting with barrier material so that the highly doped regions are formed essentially between the barrier material in the substrate.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: June 29, 2004
    Assignee: Stichting Energieonderzoek Centrum Nederland
    Inventor: Jan Hendrik Bultman
  • Patent number: 6740552
    Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: May 25, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
  • Patent number: 6730944
    Abstract: The invention provides a laser structure that operates at a wavelength of 1.3 &mgr;m and at elevated temperatures and a method of making same. The laser structure includes a quantum well layer of InAsP. The quantum well layer is sandwiched between a first barrier layer and a second barrier layer. Each barrier layer exhibits a higher bandgap energy than the quantum well layer. Also, each barrier layer comprises Gax(AlIn)1−xP in which x 0. This material has a higher bandgap energy than conventional barrier layer materials, such as InGaP. The resulting larger conduction band discontinuity leads to improved high temperature performance without increasing the threshold current of the laser structure.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: May 4, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Ashish Tandon, Ying-Ian Chang, Scott W. Corzine, David P. Bour, Michael R. T. Tan
  • Patent number: 6716659
    Abstract: A method and an apparatus for shaping semiconductor surfaces, in which a semiconductor wafer with a surface to be shaped is clamped in-between two plates. In which case at least one plate has a negative form with respect to the desired form to be formed in a semiconductor surface and the semiconductor surface is pressed by the plates at an elevated temperature. The method can be used particularly advantageously for fabricating concave microlens structures in semiconductor surfaces.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: April 6, 2004
    Assignee: Infineon Technologies AG
    Inventor: Torsten Wipiejewski
  • Patent number: 6716654
    Abstract: The present invention discloses a light-emitting diode with enhanced brightness and a method for fabricating the same. The light-emitting diode comprises: an epitaxial LED structure having at least one lighting-emitting active layer with a plurality of spacers inside the lighting-emitting active layer; at least one conductive contact, formed on the bottom surface where no spacer is formed inside the lighting-emitting active layer; a transparent material layer formed in the spacers; an adhesion layer formed between the transparent material layer and a permanent substrate; a bottom electrode formed on the bottom surface of the permanent substrate; and an opposed electrode formed on the top surface of the epitaxial LED structure.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: April 6, 2004
    Assignee: Opto Tech Corporation
    Inventors: Jung-Kuei Hsu, Hsueh-Chih Yu, Chia-Liang Hsu, Hung-Yuan Lu, Yen-Hu Chu, Chui-Chuan Chang, Kwang-Ru Wang, Chang-Da Tsai, San Bao Lin, Yung-Chiang Hwang, Ming-Der Lin
  • Patent number: 6696307
    Abstract: A method is provided, the method comprising forming a first of n masking layers for a device and forming a first of n phase-shift layers for the device using the first of the n masking layers. The method also comprises forming a second of n masking layers for a device, and forming a second of n phase-shift layers for the device using the second of the n masking layers and forming at least n+1 and at most 2n different optical thicknesses for the device using the n masking layers and the n phase-shift layers.
    Type: Grant
    Filed: September 11, 2001
    Date of Patent: February 24, 2004
    Assignee: Applied Optoelectronics, Inc.
    Inventors: Wen-Yen Hwang, Klaus Alexander Anselm, Jun Zheng, James N. Baillargeon
  • Patent number: 6682963
    Abstract: A method of realizing an active matrix display device having flexibility is provided. Further, a method for reducing parasitic capacitance between wirings formed on different layers is provided. After fixing a second substrate to a thin film device formed on a first substrate by bonding, the first substrate is removed, and wirings and the like are formed in the thin film device. The second substrate is removed next, and an active matrix display device having flexibility is formed. Further, parasitic capacitance can be reduced by forming wirings, after removing the first substrate, on the side in which a gate electrode over an active layer is not formed.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: January 27, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akira Ishikawa
  • Patent number: 6682949
    Abstract: A semiconductor laser basically includes a first cladding layer; an active layer; a second cladding layer; and a current constriction means for defining a current injection region in the active layer. The active layer has a gain region which acquires an optical gain by current injection thereto; a saturable absorption region in which current injection thereto little occurs and light effusion thereto occurs; and an outside region, being in contact with the saturable absorption region, in which current injection thereto little occurs and light effusion thereto little occurs. In this semiconductor laser, an effective band gap of the saturable absorption region is set to be larger than that of the outside region. With this configuration, carriers in the saturable absorption region are efficiently migrated to the outside region, so that the carrier lifetime in the saturable absorption region is actually shortened.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: January 27, 2004
    Assignee: Sony Corporation
    Inventor: Masakazu Ukita
  • Patent number: 6653162
    Abstract: An optical device having a current blocking layer of a buried ridge structure and a fabrication method thereof are disclosed. This invention reduces a leakage current between active layer and ion implant layer in buried ridge structure. To minimize leakage current, a P-N-P current blocking layer and an ion implanting current blocking layer are combined. An optical device of the present invention includes: active layers of a mesa structure in a predetermined region on a substrate; a first current blocking layer of a P-N-P structure, which is placed to cover the mesa structure; and a second current blocking layer of a buried ridge structure, which is placed to surround the environs of the first current blocking layer.
    Type: Grant
    Filed: April 3, 2002
    Date of Patent: November 25, 2003
    Assignees: Electronics and Telecommunications Research Institute, Korea Telecom
    Inventors: Sung Bock Kim, Jeong Soo Kim
  • Patent number: 6639258
    Abstract: Aluminum gallium nitride (AlxGa1−xN, 0<x<1) is employed as a substrate of a Group III nitride compound semiconductor device. In light-emitting diodes and laser diodes employing the substrate, crack generation is prevented, even when a thick cladding layer formed of aluminum gallium nitride (AlxGa1−xN, 0<x<1) is stacked on the substrate. The smaller the difference in Al compositional proportion between the substrate and an aluminum gallium nitride (AlxGa1−xN, 0<x<1) layer, the less likely the occurrence of crack generation.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: October 28, 2003
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Shiro Yamasaki
  • Patent number: 6617182
    Abstract: A semiconductor device includes: a crystalline substrate including a primary surface and a crystal plane provided within the primary surface so as to have a surface orientation different from a surface orientation of the primary surface; a semiconductor layered structure grown over the crystalline substrate; and an active region provided at a portion in the semiconductor layer structure above the crystal plane.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: September 9, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Ishida, Shinji Nakamura, Kenji Orita, Osamu Imafuji, Masaaki Yuri
  • Patent number: 6605498
    Abstract: A stressed channel is formed in a PMOS transistor by etching a recess and subsequently backfilling the recess with an epitaxially formed alloy of silicon, germanium, and an n-type dopant. The alloy has the same crystal structure as the underlying silicon, but the spacing of the crystal is larger, due to the inclusion of the germanium. An NMOS transistor can be formed by including carbon instead of germanium.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: August 12, 2003
    Assignee: Intel Corporation
    Inventors: Anand S. Murthy, Brian S. Doyle, Brian E. Roberds
  • Publication number: 20030116774
    Abstract: A nitride-based semiconductor light-emitting device includes: a conductive semiconductor substrate having first and second main surfaces; a high resistant or insulative intermediate layer formed on the first main surface of the substrate; a plurality of nitride semiconductor layers of AlxByInzGa1-x-y-zN (0<x≦1, 0≦y<1, 0≦z≦1, x+y+z=1) formed on the intermediate layer, the nitride semiconductor layers including at least one first conductivity type layer, a light-emitting layer and at least one second conductivity type layer sequentially stacked on the intermediate layer; a metal film penetrating through or detouring around the intermediate layer to connect the first conductivity type layer in contact with the intermediate layer to the conductive substrate; a first electrode formed on the second conductivity type layer; and a second electrode formed on the second main surface of the substrate.
    Type: Application
    Filed: December 4, 2002
    Publication date: June 26, 2003
    Inventors: Kensaku Yamamoto, Norikatsu Koide
  • Patent number: 6582984
    Abstract: A method for fabricating an organic light emitting diode. The method uses a mask to create an anode position by etching on a substrate and forming a plural groove in the substrate. Next, the anode is formed on the bottom of the groove. A dot-matrix type mask is used to form the organic emitting layer over the anode and under a predetermined cathode position. A hole injection layer, hole transport layer and an electron transport layer are formed inside the groove. More particularly, the total thickness of the anode, the organic emitting layer, the hole injection layer, the hole transport layer and the electron transport layer is equal to the depth of the groove to provide a smooth surface of the substrate. Finally, another mask is utilized on the substrate to form a strip shaped cathode, thus completing the fabrication of the organic light emitting diode.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: June 24, 2003
    Assignee: Helix Technology Inc.
    Inventor: Kuang-Chung Peng
  • Publication number: 20030104645
    Abstract: A method for fabricating a semiconductor device suitable for embodying an isotropic etching profile in etching a silicon substrate when a single drain cell is formed, including the steps of: a) forming a gate electrode on a silicon substrate; b) forming a spacer contacting both sides of the gate electrode; c) growing a silicon germanium layer on the silicon substrate exposed at the bottom of the spacer; d) exposing a source/drain formation region by selectively removing the silicon germanium layer; and e) growing an epitaxial silicon layer doped on the opened source/drain region.
    Type: Application
    Filed: August 16, 2002
    Publication date: June 5, 2003
    Inventors: Dae-Hee Weon, Seung-Ho Hahn
  • Patent number: 6566256
    Abstract: A method for forming an epitaxial layer involves depositing a buffer layer on a substrate by a first deposition process, followed by deposition of an epitaxial layer by a second deposition process. By using such a dual process, the first and second deposition processes can be optimized, with respect to performance, growth rate, and cost, for different materials of each layer. A semiconductor heterostructure prepared by a dual deposition process includes a buffer layer formed on a substrate by MOCVD, and an epitaxial layer formed on the buffer layer, the epitaxial layer deposited by hydride vapor-phase deposition.
    Type: Grant
    Filed: April 16, 1999
    Date of Patent: May 20, 2003
    Assignees: GBL Technologies, Inc., Matsushita Electric Industrial Co., Ltd
    Inventors: Glenn S. Solomon, David J. Miller, Tetsuzo Ueda
  • Patent number: 6562649
    Abstract: A compound semiconductor light emitting device that can keep the effect of confining carriers into an active layer and that can improve light emission efficiency. In the device having a first conductive type substrate; and active layer on the first conductive type substrate; a second conductive type sub-layer and a first conductive type sub-layer, in this order from a lower portion to an upper portion of the device, on the first conductive type substrate and at both sides of the active layer; a second conductive type cladding layer on/over the active layer and the first conductive type sub-layer; and a second conductive type contact layer on the second conductive type cladding layer 19. A p-type diffusion barrier layer is further formed between the n-type sub-layer and the p-type cladding layer.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: May 13, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Tsutomu Munakata, Yasumasa Kashima
  • Patent number: 6518159
    Abstract: An object of the present invention is provide an InGaAlP-based semiconductor layer of a good crystal quality at a higher temperature up to a re-evaporating temperature by MBE process. A buffer layer made of GaAs and a buffer layer made of GaInP are formed by MBE (molecular beam epitaxy) process on a GaAs substrate having a facet, which is to be a main facet, inclined by &thgr; in [011] direction from (100) facet. Then semiconductor layers are formed by MBE process so as to include cladding layers having a bandgap Egc and an AlGaInP active layer having a bandgap Ega which is adjusted by an amount of III-group element to be represented by Ega<Egc. The semiconductor laser device has a ridge stripe extending in [01-1] direction.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: February 11, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Atsuo Tsunoda
  • Patent number: 6518076
    Abstract: A semiconductor laser device includes an active layer formed on a substrate, and current blocking layers formed on the substrate so as to sandwich the active layer. Each current blocking layer has a low impurity concentration at a portion near the active layer and a high impurity concentration at a portion apart from the active layer. A manufacturing method of the semiconductor laser device is also disclosed.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: February 11, 2003
    Assignee: NEC Corporation
    Inventor: Tetsuya Hosoda
  • Patent number: 6509139
    Abstract: A method of fabricating an integrated optical component on a silicon-on insulator chip comprising a silicon layer (1) separated from a substrate (2) by an insulating layer (3), the component having a first set of features, eg a rib waveguide (5) at a first level in the silicon layer (1) adjacent the insulating layer (3) and a second set of features, eg a triangular section (5B) at a second level in the silicon layer (1) further from the insulating layer (3), the method comprising the steps of: selecting a silicon-on-insulator chip having a silicon layer (1) of sufficient thickness for the first set of features; fabricating the first set of features in the silicon layer (1) at a first level in the silicon layer; increasing the thickness of the silicon layer (1) in selected areas to form a second level of the silicon layer (1) over part of the first level; and then fabricating the second set of features at the second level in the silicon layer (1).
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: January 21, 2003
    Assignee: Bookham Technology PLC
    Inventors: Stephen William Roberts, John Paul Drake, Arnold Peter Roscoe Harpin
  • Patent number: 6471770
    Abstract: A thick GaN layer is grown on sapphire through an Au layer at a temperature lower than the melting point of 1064° C. of the Au layer, and temperature of a sample is raised to reach and exceed the melting point of the Au layer so that the Au layer is dissolved. In this state, the sapphire and GaN layer are separated from each other.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: October 29, 2002
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Seiji Nagai
  • Patent number: 6455337
    Abstract: A Group III-V nitride compound semiconductor light emitting device is constructed without the employing homogeneous layers of AlGaN. Instead of homogeneous AlGaN cladding layers, GaN cladding layers are utilized. Since high temperature growths that accompany the formation of AlGaN layers is no longer required, the stochiometric amount of indium in InxGa1−xN core layers utilized in the active region may be made greater to achieve better electrical and optical properties in the device. The loss of waveguiding achieved by the higher refractive index layers of AlGaN is compensated by the use of core layers of InGaN on adjacent sides of the active region comprising InyGa1−yN layer or layers.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: September 24, 2002
    Assignee: JDS Uniphase Corporation
    Inventor: Boris N. Sverdlov
  • Publication number: 20020106826
    Abstract: The invention describes a CVD reactor on solid substrates and a related method of deposition of epitaxial layers on the wafers. In the reactor of the invention, the wafer carrier is transported between a loading position and a deposition position. In the deposition position, the wafer carrier is detachably mounted on an upper end of a rotatable spindle without an intermediate susceptor. The reactor of the invention may process a single wafer or a plurality of wafers at the same time.
    Type: Application
    Filed: February 7, 2001
    Publication date: August 8, 2002
    Inventors: Vadim Boguslavskiy, Alexander Gurary
  • Patent number: 6406929
    Abstract: A pn junction diode (250) having its metallurgical junction of the oppositely-doped regions (254, 256) coincident with the surface WS of an electrically-doped wafer W and a method of forming such a diode. The method includes preparing (202) the wafer surface prior to placing the wafer into a reaction chamber (14). The preparation of the wafer surface includes UV ozonation (102d) and hydrogen-termination (102e) in a hydrofluoric acid solution. After the wafer surface is prepared, the wafer is inserted into the reaction chamber and heated to a temperature of less than 650° C. Without delay, a pn junction (252) is formed by growing on the wafer surface an epitaxial film layer having a doping opposite the doping of the wafer. The doped film layer is grown (204) by plasma-enhanced chemical vapor deposition while simultaneously introducing dopant atoms into the reaction chamber.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: June 18, 2002
    Assignee: University of Vermont and State Agricultural College
    Inventors: Walter J. Varhue, Sean G. Reidy
  • Patent number: 6363092
    Abstract: High power edge emitting semiconductor lasers are formed to emit with very narrow spectral width at precisely selected wavelengths. An epitaxial structure is grown on a semiconductor substrate, e.g., GaAs, and includes an active region at which light emission occurs, upper and lower confinement layers and upper and lower cladding layers. A distributed feedback grating is formed in an aluminum free section of the upper confinement layer to act upon the light generated in the active region to produce lasing action and emission of light from an edge face of the semiconductor laser. Such devices are well suited to being formed to provide a wide stripe, e.g., in the range of 50 to 100 &mgr;m or more, and high power, in the 1 watt range, at wavelengths including visible wavelengths.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: March 26, 2002
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Dan Botez, Thomas L Earles, Luke J. Mawst
  • Patent number: 6350629
    Abstract: In an optical semiconductor device including a semiconductor substrate, an active layer formed on the semiconductor substrate, a pnpn-type current blocking layer formed on a side of the active layer, and a carrier recombination layer on the semiconductor substrate on the side of the active layer, a structure of the active layer is different from a structure of the carrier recombination layer.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: February 26, 2002
    Assignee: NEC Corporation
    Inventor: Yasutaka Sakata
  • Patent number: 6342404
    Abstract: A group III nitride compound semiconductor device is produced according to the following manner. A separation layer made of a material which prevents group III nitride compound semiconductors from being grown thereon is formed on a substrate. Group III nitride compound semiconductors is grown on a surface of the substrate uncovered with the separation layer while keeping the uncovered substrate surface separated by the separation layer.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: January 29, 2002
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Naoki Shibata, Jun Ito, Toshiaki Chiyo, Shizuyo Asami, Hiroshi Watanabe, Shinya Asami
  • Patent number: 6337223
    Abstract: A semiconductor optical device and a method for fabricating the same. The semiconductor optical device comprises a substrate, a semiconductor electrode layer of a first conductive type formed on the substrate and having a groove formed to a desired depth therein, a semiconductor layer of the first conductive type formed from side walls of the groove up to a part of the semiconductor electrode layer of the first conductive type on the periphery of the groove, a cladding layer of the first conductive type, an active layer of the first conductive type, a cladding layer of a second conductive type and a semiconductor electrode layer of the second conductive type sequentially formed on the semiconductor layer of the first conductive type, and electrodes of the first and second conductive types formed respectively on the semiconductor electrode layers of the first and second conductive types.
    Type: Grant
    Filed: July 12, 1999
    Date of Patent: January 8, 2002
    Assignee: LG Electronics Inc.
    Inventors: Wook Kim, Tae Kyung Yoo
  • Patent number: 6320209
    Abstract: A semiconductor light emitting device includes: a substrate; a contact layer made of a gallium nitride based compound semiconductor formed on the substrate; a stripe-shaped conductive selective growth mask formed above the contact layer; and a layered structure made of a gallium nitride based compound semiconductor. The layered structure includes at least a pair of cladding layers, formed on the conductive selective growth mask, and an active layer, including at least one layer, sandwiched by the cladding layers.
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: November 20, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshio Hata, Shigetoshi Ito
  • Patent number: 6277756
    Abstract: A method of manufacturing a semiconductor device, which can effectively form a trench having a high aspect ratio with relatively simple steps. An initial trench is formed in a silicon substrate by a reactive ion etching using an oxide film mask as an etching mask. After forming a protection oxide film on an inside surface of the trench, a part of the protection oxide film at which positions at a bottom surface of the trench is removed by a reactive ion etching, so that an etching of the silicon substrate is advanced through the bottom surface of the trench. Furthermore, the step for forming the protection oxide film and the step for re-etching the bottom surface of the trench are repeatedly performed, so that a depth of the trench becomes a predetermined depth. These steps are performed in a common chamber by using plasma processed with switching gases to be introduced to the chamber.
    Type: Grant
    Filed: February 10, 2000
    Date of Patent: August 21, 2001
    Assignee: Denso Corporation
    Inventors: Junji Ohara, Shinji Yoshihara, Kazuhiko Kano, Nobuyuki Ohya
  • Patent number: 6235547
    Abstract: In a semiconductor device, concave sections in which an opening area becomes small in proportion as a depth becomes deep are formed in a crystal layer, and a quantum structure is formed on at least one crystal face of a bottom section of the concave section and a border formed between plural sidewalls thereof. In case the quantum structure is formed in the bottom section, a quantum box is formed therein. If the quantum structure is formed in the border between the sidewalls of the concave section, a quantum wire is formed therein. In case the quantum structure is formed in the sidewall of the concave section, a two-dimensional quantum well is formed therein.
    Type: Grant
    Filed: August 4, 1999
    Date of Patent: May 22, 2001
    Assignee: Fujitsu Limited
    Inventors: Yoshiki Sakuma, Yoshihiro Sugiyama, Shunichi Muto
  • Patent number: 6228670
    Abstract: In a method of manufacturing a semiconductor optical waveguide array in an ultra-high integration, the device yield per wafer is considerably increased and uniform and improved characteristics are obtained. In this method, there is manufactured a semiconductor optical waveguide array including a plurality of optical waveguides in an array structure in stripe-shaped growth regions enclosed by dielectric thin films on a substrate. The waveguides are fabricated through a selective crystal growth process and include a semiconductor multilayer structure including a quantum well layer or a semiconductor multilayer structure including a bulk layer. Namely, there is formed a plurality of stripe-shaped growth regions elongated parallel to each other, the regions being enclosed with a dielectric thin film. In each growth region, a semiconductor multilayer structure is selectively grown by metallo-organic vapor phase epitaxy (MOVPE).
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: May 8, 2001
    Assignee: NEC Corporation
    Inventor: Koji Kudo
  • Patent number: 6222866
    Abstract: A surface emitting semiconductor laser comprises a semiconductor multilayer reflecting film of a first conductivity type, a quantum well active layer having at least one quantum well structure, a semiconductor multilayer reflecting film of a second conductivity type and a contact layer of the second conductivity type sequentially stacked in a layered manner inside a concavity formed on a surface of a semiconductor substrate. The contact layer of the second conductivity type is formed in a buried manner so that the surface of the contact layer is approximately flush with the surface of the semiconductor substrate. A second electrode is formed on a part of the surface of the contact layer other than a part left for forming a light guiding region thereon.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: April 24, 2001
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Yasuji Seko
  • Patent number: 6210987
    Abstract: A multilayered LED structure which has an active light-emitting layer of porous silicon carbide and a sequence of layers of porous silicon carbide underneath which serves as a quarter-wavelength multilayer mirror. The result is the electroluminescent emission of spectrally narrow visible light in the deep blue to UV range, in a highly directed pattern. The deep, intense blue luminescence is accomplished via the appropriate preparation and passivation of a single porous silicon carbide layer, followed by the deposition of a transparent, semiconducting layer, such as ITO (In2O3) or ZnO.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: April 3, 2001
    Assignee: Kulite Semiconductor Products Inc.
    Inventors: Anthony D. Kurtz, Jonathan E. Spanier
  • Patent number: 6168964
    Abstract: A method of fabricating a semiconductor light emitting device includes fabricating semiconductor light emitting devices on a large scale by forming desirable end surfaces of resonators using an etching process. The method includes the steps of forming, on a base body, semiconductor layers for constituting a plurality of semiconductor light emitting devices; grooving the semiconductor layers formed on the base body in the direction from a front surface of the semiconductor layers to the base body, to form stripe-like grooves; and forming a semiconductor film in the grooves by epitaxial growth; wherein a side surface of each of the grooves, which side surface finally forms an end surface of a resonator of each of the semiconductor light emitting devices, is a crystal plane being later in epitaxial growth rate than a bottom surface of the groove.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: January 2, 2001
    Assignee: Sony Corporation
    Inventor: Yuichi Hamaguchi
  • Patent number: 6117699
    Abstract: An array of n-wavelength vertical cavity surface emitting lasers (VCSELs) can be grown with precise and repeatable wavelength control. First, a foundation VCSEL structure is grown on a substrate. Next, n-paired layers of AlGaAs and InGaP are grown, where n is the desired number of different wavelengths. Next, one of the n regions is masked and etched. The steps of masking and etching are repeated until all n regions are etched. Finally, the upper VCSEL structure is grown.
    Type: Grant
    Filed: April 10, 1998
    Date of Patent: September 12, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Brian E. Lemoff, Dubravko Babic, Richard P. Schneider
  • Patent number: 6107112
    Abstract: In a distributed feedback semiconductor laser includes an InP substrate and a multiple layer structure formed on a main surface of the InP substrate, the multiple layer structure includes at least an active layer for emitting laser light and a periodical structure for distributed feedback of the laser light, and the periodical structure includes a plurality of semiconductor regions each having a triangular cross section in a direction perpendicular to the main surface of the InP substrate and parallel to a cavity length of the distributed feedback semiconductor laser, the triangular cross section projecting toward the InP substrate.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: August 22, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Kito, Masato Ishino, Nobuyuki Otsuka, Yasushi Matsui, Shinji Nakamura
  • Patent number: 5991326
    Abstract: A monolithic long-wavelength vertical optical cavity device built up along a vertical direction. The device, when designed as a surface emitting laser, has a bottom Distributed Bragg Reflector (DBR), an active region consisting of active bulk medium or quantum wells, a current confinement layer next to the active layer, and a top DBR. The bottom DBR and the active region are lattice matched to the lattice defining material, while the top DBR is lattice relaxed. The design achieves high reflectivity, low absorption and diffraction loss. The design also ensures low production cost due to low precision requirement and wafer size production. The device can be used as a light detector when the active region is replaced by a spacer or a optical filter.
    Type: Grant
    Filed: April 14, 1998
    Date of Patent: November 23, 1999
    Assignee: Bandwidth9, Inc.
    Inventors: Wupen Yuen, Gabriel S. Li, Constance J. Chang-Hasnian
  • Patent number: 5985683
    Abstract: A method for fabricating an improved aperture is provided in which an oxidizable layer is deposited on a substrate, a mask is deposited in a first region over the oxidizable layer to leave a second region exposed, the oxidizable layer in the second region is removed, additional non-oxidizable material is deposited over the second region, a side wall of the oxidizable region is exposed, and the oxidizable layers is oxidized to form an oxidized region in at least a portion of the first region.
    Type: Grant
    Filed: November 5, 1997
    Date of Patent: November 16, 1999
    Assignee: Picolight, Inc.
    Inventor: Jack L. Jewell
  • Patent number: 5939734
    Abstract: A method of fabricating a semiconductor light emitting device includes fabricating, semiconductor light emitting devices on a large scale by forming desirable end surfaces of resonators using an etching process. The method includes the steps of forming, on a base body, semiconductor layers for constituting a plurality of semiconductor light emitting devices; grooving the semiconductor layers formed on the base body in the direction from a front surface of the semiconductor layers to the base body, to form stripe-like grooves; and forming a semiconductor film in the grooves by epitaxial growth; wherein a side surface of each of the grooves, which side surface finally forms an end surface of a resonator of each of the semiconductor light emitting devices, is a crystal plane being later in epitaxial growth rate than a bottom surface of the groove.
    Type: Grant
    Filed: February 20, 1998
    Date of Patent: August 17, 1999
    Assignee: Sony Corporation
    Inventor: Yuichi Hamaguchi
  • Patent number: 5930592
    Abstract: Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source.
    Type: Grant
    Filed: October 1, 1996
    Date of Patent: July 27, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Daniel Kadosh, Brad T. Moore, Jon D. Cheek
  • Patent number: 5920767
    Abstract: The disclosure describes a method of forming a groove in a structure of a semiconductor laser diode, which comprises a crystal growth procedure of epitaxial growth of a core layer comprising MP, wherein M represents one or more of elements belonging to group IIIb of periodic table and an upper layer comprising MAs, wherein M represents one or more of elements belonging to group IIIb of periodic table, successively on (100) surface of MAs crystals in a lower layer comprising MAs; a photolithography and wet etching procedure of, after forming an etching mask on the upper layer, forming an etching window to the etching mask; a first etching procedure of selective etching the upper layer; and a second etching procedure of selective etching other faces except for the face in which (111) face of MP crystals in the core layer is exposed.
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: July 6, 1999
    Assignee: Mitsubishi Chemical Company
    Inventors: Hideyoshi Horie, Toshinari Fujimori, Satoru Nagao, Nobuyuki Hosoi, Hideki Goto
  • Patent number: 5904492
    Abstract: A quantum wire laser diode fabrication method includes the steps of forming a buffer layer and an epitaxial layer sequentially on a substrate, forming a V-grooved pattern into the epitaxial layer to form a current blocking layer, and forming another buffer layer thereon, forming a quantum wire laser structure on the V-grooved pattern, forming a contact layer, and forming an electrode. The fabrication method employs a current blocking layer formed outside the V-grooved pattern to interrupt the current from flowing thereinto, for thereby enabling the current to only flow into the active layer, without requiring any subsequent processes which allow the current to efficiently flow into the active layer, and further obtaining the low threshold current.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: May 18, 1999
    Assignee: Korea Institute of Science and Technology
    Inventors: Suk-Ki Min, Eun Kyu Kim
  • Patent number: 5898662
    Abstract: A semiconductor light emitting device comprises: a compound semiconductor substrate; an n-type cladding layer on the compound semiconductor substrate; an active layer on the n-type cladding layer; a p-type cladding layer on the active layer: and a p-type contact layer on the p-type cladding layer, the n-type cladding layer, the active layer, the p-type cladding layer and the p-type contact layer being made of II-VI compound semiconductors containing at least one of group II elements selected from the group consisting of Zn, Cd, Mg, Hg and Be and at least one of group VI elements selected from the group consisting of S, Se, Te and O, characterized in that at least the active layer has undulations and at least the p-type layer is flat.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: April 27, 1999
    Assignee: Sony Corporation
    Inventors: Akira Ishibashi, Satoshi Taniguchi, Tomonori Hino, Takashi Kobayashi, Kazushi Nakano, Norikazu Nakayama
  • Patent number: 5882950
    Abstract: A fabrication method for a horizontal direction semiconductor PN junction array which can be achieved when an epitaxial layer is grown by a metalorganic chemical vapor deposition (MOCVD method) by introducing (or doping) a small amount of CCl.sub.4 or CBr.sub.4 gas, includes forming a recess on an N type GaAs substrate by using a non-planar growth, performing a growth method of a P type epitaxial layer on the N type GaAs substrate by a metalorganic chemical vapor deposition method, and forming a horizontal direction PN junction array of P-GaAs/N-GaAs or P-AlGaAs/N-GaAs by introducing a gas comprising CCl.sub.4 or CBr.sub.4 .
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: March 16, 1999
    Assignee: Korea Institute Of Science And Technology
    Inventors: Suk-Ki Min, Seong-Il Kim, Eun Kyu Kim