Groove Formation Patents (Class 438/42)
  • Patent number: 11697614
    Abstract: Embodiments of a article including include a substrate and a patterned coating are provided. In one or more embodiments, when a strain is applied to the article, the article exhibits a failure strain of 0.5% or greater. Patterned coating may include a particulate coating or may include a discontinuous coating. The patterned coating of some embodiments may cover about 20% to about 75% of the surface area of the substrate. Methods for forming such articles are also provided.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: July 11, 2023
    Assignee: Corning Incorporated
    Inventors: Shandon Dee Hart, Guangli Hu, Nicholas James Smith
  • Patent number: 11677216
    Abstract: A light-emitting device comprising VCSELs formed in a die. The VCSEL distribution is characterized by an essentially linear decrease in VCSEL density over the die from a highest VCSEL density in a first die region to a lowest VCSEL density in another die region. The VCSELs share a common anode and a common cathode for collective switching of the plurality of VCSELs. A method of manufacturing such a VCSEL die is also described.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: June 13, 2023
    Assignee: LUMILEDS LLC
    Inventor: Rob Jacques Paul Engelen
  • Patent number: 11594654
    Abstract: A method of generating a germanium structure includes performing an epitaxial depositing process on an assembly of a silicon substrate and an oxide layer, wherein one or more trenches in the oxide layer expose surface portions of the silicon substrate. The epitaxial depositing process includes depositing germanium onto the assembly during a first phase, performing an etch process during a second phase following the first phase in order to remove germanium from the oxide layer, and repeating the first and second phases. A germanium crystal is grown in the trench or trenches. An optical device includes a light-incidence surface formed by a raw textured surface of a germanium structure obtained by an epitaxial depositing process without processing the surface of the germanium structure after the epitaxial process.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 28, 2023
    Assignee: Infineon Technologies AG
    Inventors: Andre Roeth, Henning Feick, Heiko Froehlich, Thoralf Kautzsch, Olga Khvostikova, Stefano Parascandola, Thomas Popp, Maik Stegemann, Mirko Vogt
  • Patent number: 11538895
    Abstract: A display apparatus includes a display area, a non-display area surrounding the display area, and a bending area formed in at least one side of the non-display area. The display apparatus includes a first glass substrate provided in the display area, a second glass substrate provided in the non-display area, an anti-etching member provided to overlap the bending area, and a link line portion formed on the anti-etching member and formed to overlap the non-display area.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: December 27, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: SeungHan Paek, Kyungjae Yoon, HyunJin An, Seongwoo Park
  • Patent number: 11437784
    Abstract: A surface emitting laser may include an isolation layer including a first center portion and a first plurality of outer portions extending from the first center portion, and a metal layer including a second center portion and a second plurality of outer portions extending from the second center portion. The metal layer may be formed on the isolation layer such that a first outer portion, of the second plurality of outer portions, is formed over one of the first plurality of outer portions. The surface emitting laser may include a passivation layer including a plurality of openings. An opening may be formed over the first outer portion. The surface emitting laser may include a plurality of oxidation trenches. An oxidation trench may be positioned at least partially between the first outer portion and a second outer portion of the second plurality of outer portions.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: September 6, 2022
    Assignee: Lumentum Operations LLC
    Inventors: Ajit Vijay Barve, Albert Yuen
  • Patent number: 11380900
    Abstract: Provided are an anode for a lithium secondary battery and a lithium secondary battery comprising the same. The anode comprises: a current collector; an anode active material layer disposed on the current collector; and a coating layer disposed on the anode active material layer and including an inorganic material and a binder polymer, wherein the binder polymer has a decomposition temperature of 100° C. to 400° C., and an elastic modulus of 1.0 GPa to 3.0 GPa at 220° C. or lower.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 5, 2022
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Yongho Kim, Junghyun Nam, Seyeong Kang
  • Patent number: 11264530
    Abstract: Described are light emitting diode (LED) devices having patterned substrates and methods for effectively growing epitaxial III-nitride layers on them. A nucleation layer, comprising a III-nitride material, is grown on a substrate before any patterning takes place. The nucleation layer results in growth of smooth coalesced III-nitride layers over the patterns.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: March 1, 2022
    Assignee: LUMILEDS LLC
    Inventors: Isaac Wildeson, Toni Lopez, Hee-Jin Kim, Robert Armitage, Parijat Deb
  • Patent number: 11236439
    Abstract: A method for producing a GaN crystal is provided. In the method, front surfaces of a plurality of tiling GaN seeds closely arranged side by side on a flat surface of a plate are planarized. An aggregated seed is formed by arranging the tiling GaN seeds closely side by side on a susceptor of an HVPE apparatus in the same arrangement as when fixed on the plate, with the front planarized surfaces facing upward. A bulk GaN crystal is grown epitaxially on the aggregated seed by an HVPE method.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: February 1, 2022
    Assignee: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Yusuke Tsukada, Masayuki Tashiro, Hideo Namita
  • Patent number: 11233174
    Abstract: A semiconductor optical device includes an element structure layer that includes a mesa stripe extending in a first direction; an electrode film that covers at least an upper surface of the mesa stripe; an electrode pad portion that covers a part of a first region positioned in a second direction, intersecting the first direction, relative to the mesa stripe on an upper surface of the element structure layer and is electrically connected to the electrode film; a first dummy electrode that covers another part of the first region and is electrically insulated from the electrode film; and a second dummy electrode that covers at least a part of a second region positioned in a third direction, opposite to the second direction, relative to the mesa stripe on the upper surface of the element structure layer and is electrically insulated from the electrode film, wherein the first dummy electrode includes a first portion disposed in the first direction relative to the electrode pad portion and a second portion dispose
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: January 25, 2022
    Assignee: Lumentum Japan, Inc.
    Inventors: Masahiro Ebisu, Takayuki Nakajima, Yuji Sekino
  • Patent number: 10743448
    Abstract: A substrate position detection device includes: an irradiator that irradiates a predetermined range of a substrate with a predetermined light; an imager that takes an image of the predetermined range of the substrate irradiated with the predetermined light; a moving mechanism that causes a relative movement of the imager and the substrate; and a controller that: detects a position of the substrate by sequentially executing to a plurality of recognition objects on the substrate: a moving process of relatively moving the imager to a position corresponding to a predetermined recognition object among the plurality of recognition objects on the substrate; an imaging process of taking an image of the predetermined recognition object under a predetermined imaging condition; and a recognition process of recognizing the predetermined recognition object based on image data obtained by the imaging process.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: August 11, 2020
    Assignee: CKD CORPORATION
    Inventors: Takahiro Ninomiya, Kensuke Takamura, Nobuyuki Umemura
  • Patent number: 10641824
    Abstract: A semiconductor device comprises a device substrate and a metal film, with first and second non-recessed areal regions separated by a recessed areal region. The metal film covers contiguously the recessed and non-recessed areal regions and transition surfaces joining them. A first transition surface includes metallized portions over which (i) the first transition surface is not parallel to the other transition surface, (ii) the first transition surface is inclined relative to the device substrate, and (iii) the metal film on the first transition surface is contiguous with adjacent metal film portions on the recessed and non-recessed areal regions. A portion of an optoelectronic device surface running parallel to an optical waveguide of the device can be left exposed by a metal film on the device. Light propagating transversely out of the waveguide through the exposed portion can be detected, measured, or imaged for non-destructive device characterization or testing.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: May 5, 2020
    Assignee: Emcore Corporation
    Inventors: Xiaoguang He, Ruby Zendejaz, Dustin Huynh
  • Patent number: 10325793
    Abstract: A method for producing a crystal substrate includes preparing, measuring, holding, and machining. The preparing prepares a crystal substrate body including a curved crystal lattice plane. The measuring measures a shape feature of the crystal lattice plane. The holding holds the crystal substrate body in a warped state in accordance with the shape feature measured by the measuring, to more flatten the crystal lattice plane than the crystal lattice plane at the preparing. The machining machines a surface of the crystal substrate body held in the warped state, to flatten the surface.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: June 18, 2019
    Assignee: SCIOCS COMPANY LIMITED
    Inventors: Masahiro Hayashi, Chiharu Kimura
  • Patent number: 10312491
    Abstract: A separator includes a first layer that has a first principal face and a second principal face, and a second layer that is formed on at least one of the first principal face and the second principal face. The first layer is a microporous membrane including a first polymer resin, and the second layer is a microporous membrane including inorganic particles having an electrically insulating property and a second polymer resin.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: June 4, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazuki Chiba, Atsushi Kajita, Yukako Teshima, Masatake Hayashi
  • Patent number: 9788814
    Abstract: An ultrasonic measuring apparatus includes an ultrasonic transducer device having a substrate and an ultrasonic transducer element array that has a first channel group and a second channel group that are arranged on the substrate, a first integrated circuit apparatus that is mounted on the substrate, at one edge portion of the ultrasonic transducer element array in a first direction, such that a long-side direction coincides with a second direction that intersects the first direction, and performs at least one of signal transmission to the first channel group and signal reception from the first channel group, and a second integrated circuit apparatus that is mounted on the substrate, at the other edge portion of the ultrasonic transducer element array in the first direction, such that the long-side direction coincides with the second direction, and performs at least one of signal transmission to the second channel group and signal reception from the second channel group.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: October 17, 2017
    Assignee: Seiko Epson Corporation
    Inventor: Kogo Endo
  • Patent number: 9466762
    Abstract: A base for making an epitaxial structure is provided. The base includes a substrate and a carbon nanotube layer. The substrate has an epitaxial growth surface. The carbon nanotube layer is located on the epitaxial growth surface. The carbon nanotube layer defines a plurality of apertures to expose part of the epitaxial growth surface so that an epitaxial layer can grow from an exposed epitaxial growth surface and through the apertures. A method for making an epitaxial structure using the base is also provided.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: October 11, 2016
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wei, Chen Feng, Shou-Shan Fan
  • Patent number: 9293653
    Abstract: Certain example embodiments of this invention relate to techniques for improving the performance of Lambertian and non-Lambertian light sources. In certain example embodiments, this is accomplished by (1) providing an organic-inorganic hybrid material on LEDs (which in certain example embodiments may be a high index of refraction material), (2) enhancing the light scattering ability of the LEDs (e.g., by fractal embossing, patterning, or the like, and/or by providing randomly dispersed elements thereon), and/or (3) improving performance through advanced cooling techniques. In certain example instances, performance enhancements may include, for example, better color production (e.g., in terms of a high CRI), better light production (e.g., in terms of lumens and non-Lambertian lighting), higher internal and/or external efficiency, etc.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: March 22, 2016
    Assignee: Guardian Industries Corp.
    Inventors: Vijayen S. Veerasamy, Jemssy Alvarez
  • Patent number: 9142726
    Abstract: Structures are incorporated into a semiconductor light emitting device which may increase the extraction of light emitted at glancing incidence angles. In some embodiments, the device includes a low index material that directs light away from the metal contacts by total internal reflection. In some embodiments, the device includes extraction features such as cavities in the semiconductor structure which may extract glancing angle light directly, or direct the glancing angle light into smaller incidence angles which are more easily extracted from the device.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: September 22, 2015
    Assignee: Philips Lumileds Lighting Company LLC
    Inventors: Aurelien J. F. David, Henry Kwong-Hin Choy, Jonathan J. Wierer, Jr.
  • Patent number: 9040322
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor light emitting element. The method can include bonding a stacked main body of a structural body to a substrate main body. The structural body includes a growth substrate and the stacked main body provided on the growth substrate. The stacked main body includes a first nitride semiconductor film, a light emitting film provided on the first nitride semiconductor film, and a second nitride semiconductor film provided on the light emitting film. The method can include removing the growth substrate. The method can include forming a plurality of stacked bodies. The method can include forming an uneven portion in a surface of a first nitride semiconductor layer. The method can include forming a plurality of the semiconductor light emitting elements.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taisuke Sato, Kotaro Zaima, Jumpei Tajima, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 9040328
    Abstract: A manufacturing method for an LED includes providing a substrate having a buffer layer and a first N-type epitaxial layer, forming a blocking layer on the first N-type epitaxial layer, and etching the blocking layer to form patterned grooves penetrating the blocking layer to the first N-type epitaxial layer. A second N-type epitaxial layer is then formed on the blocking layer to contact the first N-type epitaxial layer; a light emitting layer, a P-type epitaxial layer and a conductive layer are thereafter disposed on the second N-type epitaxial layer; an N-type electrode is formed to electrically connect with the first N-type epitaxial layer, and a P-type electrode is formed on the conductive layer. The N-type electrode is disposed on the blocking layer and separated from the second N-type epitaxial layer and has a portion extending into the patterned grooves to contact the first N-type epitaxial layer.
    Type: Grant
    Filed: May 4, 2014
    Date of Patent: May 26, 2015
    Assignee: Zhongshan Innocloud Intellectual Property Services Co., Ltd.
    Inventors: Ya-Wen Lin, Shih-Cheng Huang, Po-Min Tu, Chia-Hung Huang, Shun-Kuei Yang
  • Publication number: 20150137087
    Abstract: An organic light-emitting element including: a substrate; a light-emitting part above the substrate, the light-emitting part including an organic layer; and banks defining bounds of the organic layer in a direction along a main surface of the substrate. In the organic light-emitting element, in plan view, a surface of the organic layer is longer in a first direction than in a second direction perpendicular to the first direction, and in the second direction, the surface of the organic layer is convex, protruding upwards in a thickness direction of the organic layer, and in the first direction, the surface of the organic layer is concave, protruding downwards in the thickness direction.
    Type: Application
    Filed: September 26, 2012
    Publication date: May 21, 2015
    Applicant: PANASONIC CORPORATION
    Inventor: Tsuyoshi Yamamoto
  • Patent number: 9034670
    Abstract: A method (100; 100a; 100b; 100c) for manufacturing a solar cell from a semiconductor substrate (1) of a first conductivity type, the semiconductor substrate having a front surface (2) and a back surface (3). The method includes in a sequence: texturing (102) the front surface to create a textured front surface (2a); creating (103) by diffusion of a dopant of the first conductivity type a first conductivity-type doped layer (2c) in the textured front surface and a back surface field layer (4) of the first conductivity type in the back surface; removing (105; 104a) the first conductivity-type doped layer from the textured front surface by an etching process adapted for retaining texture of the textured front surface; creating (106) a layer of a second conductivity type (6) on the textured front surface by diffusion of a dopant of the second conductivity type into the textured front surface.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: May 19, 2015
    Assignee: Stichting Energieonderzoek Centrum Nederland
    Inventors: Paul Cornelis Barton, Ronald Cornelis Gerard Naber, Arno Ferdinand Stassen
  • Patent number: 9029177
    Abstract: An optoelectronic semiconductor chip has a first semiconductor layer sequence which comprises a multiplicity of microdiodes, and a second semiconductor layer sequence which comprises an active region The first semiconductor layer sequence and the second semiconductor layer sequence are based on a nitride compound semiconductor material, the first semiconductor layer sequence is before the first semiconductor layer sequence in the direction of growth, and the microdiodes form an ESD protection for the active region.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: May 12, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Rainer Butendeich, Alexander Walter, Matthias Peter, Tobias Meyer, Tetsuya Taki, Hubert Maiwald
  • Patent number: 9012953
    Abstract: A light emitting device and method for making the same is disclosed. The light-emitting device includes an active layer sandwiched between a p-type semiconductor layer and an n-type semiconductor layer. The active layer emits light when holes from the p-type semiconductor layer combine with electrons from the n-type semiconductor layer therein. The active layer includes a number of sub-layers and has a plurality of pits in which the side surfaces of a plurality of the sub-layers are in contact with the p-type semiconductor material such that holes from the p-type semiconductor material are injected into those sub-layers through the exposed side surfaces without passing through another sub-layer. The pits can be formed by utilizing dislocations in the n-type semiconductor layer and etching the active layer using an etching atmosphere in the same chamber used to deposit the semiconductor layers without removing the partially fabricated device.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Steven Lester, Jeff Ramer, Jun Wu, Ling Zhang
  • Patent number: 9012934
    Abstract: A method of forming a semiconductor layer is provided. The method includes forming a plurality of nanorods on a substrate and forming a lower semiconductor layer on the substrate so as to expose at least portions of the nanorods. The nanorods are removed so as to form voids in the lower semiconductor layer, and an upper semiconductor layer is formed on an upper portion of the lower semiconductor layer and the voids.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong Suk Lee, Ok Hyun Kim, Dong Yul Lee, Dong Ju Lee, Jeong Wook Lee, Heon Ho Lee
  • Patent number: 9006012
    Abstract: A method of manufacturing an organic light emitting diode display according to an exemplary embodiment of the present invention includes: forming a first electrode on a substrate; forming an insulation layer on the first electrode; etching the insulation layer to expose the first electrode so as to form a pixel defining layer having the same height as the first electrode; forming an organic layer including one or more emission layers on the first electrode of a sub-pixel region defined by the pixel defining layer by applying a laser-induced thermal imaging (LITI) method; and forming a second electrode on the organic layer.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: April 14, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Valeriy Prushinskiy, Min-Soo Kim, Won-Sik Hyun, Heung-Yeol Na, Jin-Won Sun
  • Publication number: 20150097209
    Abstract: A semiconductor device including a Si (110) substrate, a buffer layer, a first type doped semiconductor layer, a light-emitting layer and a second type doped semiconductor layer is provided. The Si (110) substrate has a plurality of trenches. Each trench at least extends along a first direction, and the first direction is parallel to a <1-10> crystal direction of the Si (110) substrate. The buffer layer is located on the Si (110) substrate and exposes the trenches. The first type doped semiconductor layer is located on the buffer layer and covers the trenches. The light-emitting layer is located on the first type doped semiconductor layer. The second type doped semiconductor layer is located on the light-emitting layer. A fabrication method of a semiconductor device is also provided.
    Type: Application
    Filed: November 29, 2013
    Publication date: April 9, 2015
    Applicant: National Taiwan University
    Inventors: Chih-Chung Yang, Chun-Han Lin, Chia-Ying Su, Horng-Shyang Chen
  • Patent number: 9000471
    Abstract: There is provided a manufacturing method of an LED module including: forming an insulating film on a substrate; forming a first ground pad and a second ground pad separated from each other on the insulating film; forming a first division film that fills a space between the first and second ground pads, a second division film deposited on a surface of the first ground pad, and a third division film deposited on a surface of the second ground pad; forming a first partition layer of a predetermined height on each of the division films; sputtering seed metal to the substrate on which the first partition layer is formed; forming a second partition layer of a predetermined height on the first partition layer; forming a first mirror connected with the first ground pad and a second mirror connected with the second ground pad by performing a metal plating process to the substrate on which the second partition layer is formed; removing the first and second partition layers; connecting a zener diode to the first mirror
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: April 7, 2015
    Assignee: Daewon Innost Co., Ltd.
    Inventors: Won Sang Lee, Young Keun Kim
  • Patent number: 8995490
    Abstract: An edge-emitting semiconductor laser diode includes an epitactic semiconductor layer stack and a planarization layer. The semiconductor layer stack includes a main body and a ridge waveguide. The main body includes an active layer for generating electromagnetic radiation. The planarization layer embeds the ridge waveguide such that a surface of the ridge waveguide and a surface of the planarization layer form a flat main surface. A method for producing such a semiconductor laser diode is also disclosed.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: March 31, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Alfred Lell, Christoph Nelz, Christian Rumbolz, Stefan Hartauer
  • Publication number: 20150079713
    Abstract: An LED includes a first electrode, for connecting the LED to a negative electrode of a power supply and a substrate located on the first electrode in which a plurality of contact holes are formed extending through the substrate. The diameter of upper parts of the contact holes is less than the diameter of lower parts of the contact holes, and the contact holes are filled with electrode plugs connecting the first electrode to the LED die. The light emitting device includes the LED, and further includes a susceptor and an LED mounted on the susceptor. The manufacturing method includes forming successively an LED die and a second electrode on a substrate, patterning a back surface of the substrate to form inverted trapezoidal contact holes which expose the LED die, and filling the contact holes with conductive material until the back face of the substrate is covered by the conductive material.
    Type: Application
    Filed: November 20, 2014
    Publication date: March 19, 2015
    Inventors: Richard Rugin Chang, Deyuan Xiao
  • Patent number: 8962363
    Abstract: Provided is a novel method for forming a groove composed of two smooth inclined surfaces on a surface of a flat plate formed of a nitride semiconductor crystal having an A, C, M-axes. In the present invention, a disk-shaped dicing blade is moved along a direction of the A-axis to form first and second inclined surfaces on the surface of the flat plate. The following mathematical formulae (I)-(III) are satisfied: 45 degrees??b?a?60 degrees (I) 45 degrees??b+a?60 degrees (II), 0 degrees?|a|?7.5 degrees, where angle ?b represents an angle formed between a surface of the edge and a radial direction of the dicing blade in a cross-sectional view which includes the M-axis and the C-axis. The angle a represents an angle formed between the principal surface and the M-axis.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: February 24, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Akira Inoue, Toshiyuki Fujita, Toshiya Yokogawa
  • Publication number: 20150043603
    Abstract: Provided is a high-output light-emitting device capable of emitting a light beam in a single mode. The light-emitting device includes a laminate structure body configured by laminating, in order, a first compound semiconductor layer, an active layer, and a second compound semiconductor layer on a base substrate, a second electrode, and a first electrode. The first compound semiconductor layer has a laminate structure including a first cladding layer and a first light guide layer in order from the base substrate, and the laminate structure body has a ridge stripe structure configured of the second compound semiconductor layer, the active layer, and a portion in a thickness direction of the first light guide layer. Provided that a thickness of the first light guide layer is t1, and a thickness of the portion configuring the ridge stripe structure of the first light guide layer is t1?, 6×10?7 m<t1 and 0(m)<t1??0.5·t1 are satisfied.
    Type: Application
    Filed: September 4, 2012
    Publication date: February 12, 2015
    Inventors: Masaru Kuramoto, Rintaro Koda, Hideki Watanabe
  • Patent number: 8945963
    Abstract: An optical device processing method including: a groove forming step of forming a plurality of grooves on a front side of a sapphire substrate; a film forming step of forming an epitaxial film on the front side of the sapphire substrate after performing the groove forming step, thereby forming a plurality of optical devices and a plurality of crossing division lines for partitioning the optical devices; and a dividing step of dividing the sapphire substrate with the epitaxial film along the division lines after performing the film forming step, thereby obtaining a plurality of individual optical device chips.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: February 3, 2015
    Assignee: Disco Corporation
    Inventor: Kazuma Sekiya
  • Patent number: 8946738
    Abstract: According to one embodiment, a light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a first insulating layer, a p-side interconnect layer, an n-side interconnect layer, and a second insulating layer. The portion of the second p-side interconnect layer has the L-shaped cross section being configured to include a p-side external terminal exposed from the first insulating layer and the second insulating layer at a third surface having a plane orientation different from the first surface and the second surface. The portion of the second n-side interconnect layer has the L-shaped cross section being configured to include an n-side external terminal exposed from the first insulating layer and the second insulating layer at the third surface.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: February 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Kojima, Yoshiaki Sugizaki, Yosuke Akimoto, Kazuhito Higuchi, Susumu Obata
  • Patent number: 8945960
    Abstract: An optical device wafer has a plurality of optical devices formed on a front side and a plurality of crossing division lines for partitioning the optical devices. Each optical device has electrodes formed on the front side. A processing method includes: forming a groove on the front side of the wafer along each division line, the groove having a depth reaching a finished thickness; of forming a nonconductive reflective film on the front side of the wafer to thereby form the reflective film on at least the side surfaces of the groove; removing the reflective film formed on the electrodes to thereby expose the electrodes; and grinding a back side of the wafer to thereby reduce the thickness to the finished thickness until the groove is exposed to the back side of the wafer to divide the wafer into individual optical device chips.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: February 3, 2015
    Assignee: Disco Corporation
    Inventor: Kazuma Sekiya
  • Publication number: 20150014626
    Abstract: A semiconductor light emitting element includes a substrate and a stacked body. The stacked body is aligned with the substrate. The stacked body includes first and second semiconductor layers, a light emitting layer, and first and second electrodes. The first semiconductor layer has a first face including first and second portions. The first portion is provided with a plurality of convex portions. The second portion is aligned with the first portion. The second semiconductor layer is provided facing the second portion. The light emitting layer is provided between the second portion and the second semiconductor layer. The second semiconductor layer is disposed between the second electrode and the light emitting layer. An interval of each of the convex portions is no less than 0.5 times and no more than 4 times a wavelength of a light emitted from the light emitting layer.
    Type: Application
    Filed: July 3, 2014
    Publication date: January 15, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Satoshi MITSUGI, Shinji Yamada, Shinya Nunoue
  • Publication number: 20150014644
    Abstract: A display device includes a bottom member, a display panel, a top member and a groove region. The display panel is disposed on the bottom member, and includes an organic layer. The top member is disposed on the display panel. The groove region is formed by removing at least one of the top member or the bottom member at a bending region of the display device.
    Type: Application
    Filed: December 23, 2013
    Publication date: January 15, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventors: Jun Namkung, Kwang-Hyeok Kim, Soon-Ryong Park, Jung-Ho So, Chul-Woo Jeong
  • Patent number: 8932888
    Abstract: A method of applying a conversion means to an optoelectronic semiconductor chip includes preparing the optoelectronic semiconductor chip having a main radiation face, preparing the conversion means, the conversion means being applied to a main carrier face of a carrier, arranging the conversion means such that it faces the main radiation face and has a spacing relative to the main radiation face, and releasing the conversion means from the carrier and applying the conversion means to the main radiation face by irradiation and heating of an absorber constituent of the conversion means and/or of a release layer located between the conversion means and the carrier with a pulsed laser radiation which passes through the carrier.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: January 13, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Ralph Wagner
  • Patent number: 8921846
    Abstract: The present invention aims at providing an organic EL device that emits light by an alternating current, has a simple structure and provides little increase of production processes, while downsizing an overall configuration and a simplifying a method for producing said organic EL device. The organic EL device includes a power feeding part and an organic-EL-element forming part. The organic-EL-element forming part includes a plurality of unit EL elements formed on a substrate. There is provided a plurality of series-connected parts each formed by a plurality of the unit EL elements that are electrically connected in series in a forward direction. A plurality of the series-connected parts are electrically connected to the power feeding part in parallel. The series-connected parts that are connected in parallel include a series-connected part that is connected to the power feeding part so as to have a reverse polarity.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: December 30, 2014
    Assignee: Kaneka Corporation
    Inventors: Akira Nishikawa, Shigeru Ayukawa, Hideo Yamagishi
  • Patent number: 8916405
    Abstract: Carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof are provided. In one aspect, a LED is provided. The LED includes a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first bottom gate and the second bottom gate; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED; and metal source and drain contacts to the carbon material.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Keith Kwong Hon Wong, Jun Yuan
  • Patent number: 8916873
    Abstract: A photodetector includes a semiconductor substrate having an irradiation zone configured to generate charge carriers having opposite charge carrier types in response to an irradiation of the semiconductor substrate. The photodetector further includes an inversion zone generator configured to operate in at least two operating states to generate different inversion zones within the substrate, wherein a first inversion zone generated in a first operating state differs from a second inversion zone generated in a second operating state, and wherein the first inversion zone and the second inversion zone have different extensions in the semiconductor substrate. A corresponding method for manufacturing a photodetector and a method for determining a spectral characteristic of an irradiation are also described.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: December 23, 2014
    Assignee: Infineon Technologies AG
    Inventor: Thoralf Kautzsch
  • Patent number: 8912557
    Abstract: An LED includes a substrate, a first n-type GaN layer, a connecting layer, a second n-type GaN layer, a light emitting layer, and a p-type GaN layer. The first n-type GaN layer, the connecting layer, and the second n-type GaN layer are formed on the substrate in sequence. The connecting layer is etchable by alkaline solution, and a bottom surface of the second n-type GaN layer facing towards the connecting layer has a roughed exposed portion. The GaN on the bottom surface of the second n-type GaN layer is N-face GaN. A top surface of the second n-type GaN layer facing away from the connecting layer includes a first area and a second area. The light emitting layer and the p-type GaN layer are formed on the first area of the top surface of the second n-type GaN layer in sequence.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: December 16, 2014
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Tzu-Chien Hung, Chia-Hui Shen
  • Publication number: 20140361280
    Abstract: An organic EL device with which occurrence of leakage current between electrodes can be prevented includes: a substrate; a first electrode layer separating groove that separates a first electrode layer into small pieces; a function layer separating groove that separates a function layer into small light emitting regions; and a unit light emitting element separating groove extending from a second electrode layer to the function layer and separating the second electrode layer into small pieces. One of the small pieces of the first electrode layer, one of the small light emitting regions, and one of the small pieces of the second electrode layer structure a unit organic EL element, electrically connected in series. The average width of the unit light emitting element separating groove at the second electrode layer is wider than the average width of the unit light emitting element separating groove at the light emitting portion separating layer.
    Type: Application
    Filed: December 20, 2012
    Publication date: December 11, 2014
    Applicant: KANEKA CORPORATION
    Inventors: Eiji Kuribe, Jumpei Suzuki
  • Patent number: 8906726
    Abstract: A method for making light emitting diode, the method includes the following steps. First, a substrate having an epitaxial growth surface is provided. Second, a carbon nanotube layer is suspended above the epitaxial growth surface. Third, a first semiconductor layer, an active layer and a second semiconductor layer are grown on the epitaxial growth surface in that order, wherein the first semiconductor layer includes a buffer layer, an intrinsic semiconductor layer, and a doped semiconductor layer stacked in that order. Fourth, the doped semiconductor layer is exposed by removing the substrate, the buffer layer, and the intrinsic semiconductor layer. Fifth, a first electrode is prepared on the first semiconductor layer and a second electrode is prepared on the second semiconductor layer.
    Type: Grant
    Filed: May 27, 2013
    Date of Patent: December 9, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Publication number: 20140350375
    Abstract: An optrode may provide a cylindrical substrate two or more electrodes deposited said cylindrical substrate. The cylindrical substrate and electrodes may be coated by an insulating layer with openings or vias over certain portions of the electrodes that may provide a contact for the neural probe or may be utilized to connect lead lines. Manufacturing of an optrode may utilize a jig that secures a cylindrical substrate coated by a conductive material and a resist. A first mask may be positioned in an opening provided by the jig, and the cylindrical substrate may be exposed ions or neutral particles to define one or more electrode patterns. After regions of the resist and conductive material are removed to form the electrodes, a second mask may be utilized to define vias regions in which portions of the electrodes are exposed and uncoated by an insulating layer.
    Type: Application
    Filed: May 27, 2014
    Publication date: November 27, 2014
    Applicants: University of Houston, Vanderbilt University
    Inventors: John C. Wolfe, Mufaddal Gheewala, Wei-Chuan Shih, Gopathy Purushothaman
  • Patent number: 8895400
    Abstract: A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: November 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Yun-Gi Kim, Young-Woong Son, Bong-Soo Kim
  • Publication number: 20140339959
    Abstract: A thin film bulk acoustic resonator and a method of manufacturing the same is disclosed. The thin film bulk acoustic resonator includes an acoustic resonator including a first electrode, a second electrode, and a piezoelectric layer disposed between the first electrode and the second electrode; an air gap disposed below the acoustic resonator and above a substrate to reflect the acoustic wave; and an anchor disposed on each of both surfaces of the air gap and having the same thickness as the air gap.
    Type: Application
    Filed: June 7, 2012
    Publication date: November 20, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Moon Chul Lee, In Sang Song, Duck Hwan Kim, Chul Soo Kim, Sang Uk Son, Jea Shik Shin, Ho Soo Park, Jing Cui
  • Patent number: 8889447
    Abstract: A method for fabricating an optical modulator includes forming n-type layer, a first oxide portion on a portion of the n-type layer, and a second oxide portion on a second portion of the n-type layer, patterning a first masking layer over the first oxide portion, portions of a planar surface of the n-type layer, and portions of the second oxide portion, implanting p-type dopants in the n-type layer to form a first p-type region and a second p-type region, removing the first masking layer, patterning a second masking layer over the first oxide portion, a portion of the first p-type region, and a portion of the n-type layer, and implanting p-type dopants in exposed portions of the n-type layer, exposed portions of the first p-type region, and regions of the n-type layer and the second p-type region disposed between the substrate and the second oxide portion.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: William M. Green, Jessie C. Rosenberg, Yurii A. Vlasov
  • Patent number: 8889448
    Abstract: Provided are a light-emitting element and a method of fabricating the same. The light-emitting element includes: a first pattern including conductive regions and non-conductive regions. The non-conductive regions are defined by the conductive regions. The light-emitting element also include an insulating pattern including insulating regions and non-insulating regions which correspond respectively to the conductive regions and non-conductive regions. The non-insulating regions are defined by the insulating regions. The light-emitting element further includes a light-emitting structure interposed between the first pattern and the insulating pattern. The light-emitting structure includes a first semiconductor pattern of a first conductivity type, a light-emitting pattern, and a second semiconductor pattern of a second conductivity type which are stacked sequentially. The light-emitting element also includes a second pattern formed in the non-insulating regions.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yu-Sik Kim
  • Patent number: 8883533
    Abstract: A method for manufacturing an LED package comprising steps of: providing a substrate and forming spaced electrode structures on the substrate; providing a mold on the top surface of the substrate wherein the mold defines spaced annular grooves which cooperate with the top surface of the substrate to define cavities; filling the cavities with metal material; removing the mold and hardening the metal material to form reflection cups wherein each reflection cup surrounds a corresponding electrode structure and defines a recess; polishing surfaces of the reflection cups and the electrode structures; arranging LED chips in the recesses with each LED chip electrically connected to the electrode structure; injecting an encapsulation layer in the recesses to seal the LED chips; and cutting the substrate to obtain individual LED packages.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: November 11, 2014
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Hsin-Chiang Lin, Pin-Chuan Chen, Lung-Hsin Chen
  • Patent number: 8877652
    Abstract: A substrate structure and method of manufacturing the same are disclosed. The substrate structure may includes a substrate on which a plurality of protrusions are formed on one surface thereof and a plurality of buffer layers formed according to a predetermined pattern and formed spaced apart from each other on the plurality of protrusions.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Su-hee Chae, Hyun-gi Hong, Young-jo Tak