Abstract: A wafer is processed by transferring a wafer to a holding surface of a chuck table by using a suction pad. The front side of the wafer is held through a protective tape on the holding surface under suction. The suction pad is then removed from the back side of the wafer and the back side of the wafer is ground, thereby thinning the wafer and also dividing the wafer into individual device chips. The wafer is mounted on the holding surface while held by the suction pad. The wafer is sandwiched between the suction pad and the holding surface when the suction force is removed. A suction force is applied to the holding surface to thereby hold the front side of the wafer through the protective tape on the holding surface, and the suction pad is then removed from the back side of the wafer.

Abstract: Methods for forming a chip package are provided. The method includes providing at least one carrier substrate including first semiconductor dies mounted thereon. The method also includes forming a first noble metal layer including nanopores irregularly distributed therein to cover each one of the first semiconductor dies. The method further includes immersing the carrier substrate with the first semiconductor dies into an etchant solution including a fluoride etchant and an oxidizing agent, so that each one of the first semiconductor dies covered by the first noble metal layer is thinned.

Abstract: A method of processing a wafer includes: a grinding step of grinding a back surface of the wafer to form, on the back side of the wafer, a recess corresponding to a device region and an annular projecting portion corresponding to a peripheral marginal region; and a splitting groove forming step of forming, after the grinding step is conducted, a splitting groove for splitting the device region and the peripheral marginal region from each other at the boundary between the recess and the annular projecting portion, the splitting groove extending from the front surface of the wafer to reach the back surface of the wafer. The splitting groove is formed by dry etching.

Abstract: A reflow enhancement layer is formed in an opening prior to forming and reflowing a contact metal or metal alloy. The reflow enhancement layer facilitates the movement (i.e., flow) of the contact metal or metal alloy during a reflow anneal process such that a void-free metallization structure of the contact metal or metal alloy is provided.

Abstract: A method of producing electronic components each including a substrate-type terminal and a device connected to the substrate-type terminal including a substrate body with first and second principal surfaces opposite to each other and an electrode configured to be connected to the device on the first principal surface, wherein the device is disposed on the first principal surface, includes forming grooves in a substrate from one of the first and second principal surfaces of the substrate such that the substrate is divided into the substrate-type terminals, the grooves each having a depth less than a thickness of the substrate, cutting the substrate from another principal surface opposite to the principal surface of the substrate body such that the grooves penetrate through the substrate in a thickness direction thereof, and mounting the device on each of the first principal surfaces.

Abstract: Disclosed herein is a wafer processing method including a cover plate providing step of providing a cover plate on the front side of a wafer to thereby form a composite wafer, a welding step of applying a laser beam along each division line formed on the front side of the wafer in the condition where the focal point of the laser beam is set at the interface between the wafer and the cover plate on opposite sides of the lateral center of each division line, thereby forming two parallel welded lines for joining the wafer and the cover plate along each division line, and a dividing step of forming a cut line between the two parallel welded lines formed along each division line, thereby cutting the composite wafer along each division line to obtain individual device chips each covered with the cover plate.

Abstract: A land grid array (LGA) includes a grid array of metal pads plated directly onto a printed circuit board, and a discrete metal pad soldered to each of the plated metal pads in the grid array. Each discrete metal pad has an exposed contact surface after soldering, and a thickness of each discrete metal pad is selected as a function of location in the grid array so that the discrete pads provide a locus of exposed surfaces having greater flatness than the printed circuit board.

Abstract: Disclosed herein is a wafer processing method including a first modified layer forming step of applying a laser beam having a transmission wavelength to a wafer from the back side thereof along each division line in the condition where the focal point of the laser beam is set inside the wafer near the front side thereof, thereby forming a first modified layer inside the wafer along each division line. The wafer processing method further includes a second modified layer forming step of applying the laser beam to the wafer from the back side thereof along each division line in the condition where the focal point of the laser beam is set adjacent to the first modified layer thereabove toward the back side of the wafer, thereby forming a second modified layer for growing a crack from the first modified layer toward the front side of the wafer.

Abstract: A method and device for separating a substrate with a laser beam. The duration of the laser beam's effect is extremely short, so the substrate is only modified concentrically about the laser beam axis (Z) without it degrading the substrate material. While the laser beam acts upon the substrate, the substrate moves relative to a laser machining head, producing plural filament-type modifications along a separating surface to be incorporated. The laser beam is initially diverted by a transmission medium having a higher intensity dependent refractive index than air, then reaches the substrate. The non-constant pulsed laser intensity increases to a maximum over the temporal course of the single pulse, then reduces, and the refractive index changes. The laser beam focus point moves between the substrate's outer surfaces along the beam axis (Z), reaching the desired modification along the beam axis (Z) without correcting the laser machining head in the z-axis.

Abstract: Disclosed herein is a wafer processing method in which laser processing is carried out on a wafer along streets. The wafer processing method includes a step of holding the wafer by a chuck table, a protective film forming step of forming a water-soluble protective film on a surface of the wafer, a laser beam irradiating step of irradiating the wafer with a laser beam along the streets after the protective film forming step, a step of supplying a chemical having an amino group to the wafer, and a removing step of cleaning and removing a compound that is generated by the supplying of the chemical having an amino group and contains phosphorus.

Abstract: According to one embodiment, there is provided a printed circuit board including a substrate having a trench between a first region and a second region. The first region is a region where a first package is to be mounted. The second region is a region where a second package is to be mounted. The trench has an opening portion in at least one of a first main surface and a second main surface of the substrate. The first main surface is a surface on which the first package is placed. The second main surface is positioned on reverse side of the first main surface of the substrate.

Abstract: A display panel motherboard and a manufacturing method thereof are provided. The display panel motherboard comprises display panel regions (Q1) spaced apart from each other and precut regions (Q2) adjacent to the display panel regions. The manufacturing method comprises forming an electrical insulating layer (102); and removing at least portions of the electrical insulating layer provided on the precut regions (Q2). The method avoids the problem of other patterns offset on the display panel motherboard caused by the larger internal stress within the electrical insulating layer.

Abstract: A method of transferring micro-devices is provided. A carrying unit including a carrying substrate, a plurality of electrodes, a dielectric layer covering the electrodes, and a plurality of micro-devices disposed on the electrodes, including a first micro-device and a second micro-device, are also provided. A voltage is applied to an electrode corresponding to the first micro-device, so that an electrostatic force generated on the first micro-device by the carrying unit is larger than a force generated on the second micro-device by the carrying unit. A transfer stamp contacts the first micro-device and the second micro-device, and moves when the transfer stamp contacts the first micro-device and the second micro-device and the electrostatic force is greater than the force generated by the carrying unit, so that the second micro-device is picked up by the transfer stamp and transferred to a receiving unit, and the first micro-device remains on the carrying unit.

Abstract: A blanking system for multi charged particle beams includes a blanking aperture array device to include a first substrate where a plurality of openings corresponding to passage positions of multi-beams are formed in a penetrating manner from the upper surface, and a plurality of electrode groups each having a pair of electrodes which are close to a corresponding one of the plurality of openings and are at opposite sides, on a same surface, of the corresponding one of the plurality of openings are arranged on the first substrate, a second substrate whose lower surface is electrically connected through a bump to the upper surface of the first substrate, and a mounting substrate whose upper surface is electrically connected through a bump to the lower surface of the second substrate.

Abstract: A method including: providing a structure comprising: a spalled layer having a first side and a second side; and a tape layer provided on the first side of the spalled layer, wherein the tape layer is provided at below a first temperature range; applying a temporary substrate layer to the second side of the spalled layer, wherein the temporary substrate layer is applied at a second temperature range, and wherein at least a portion of the second temperature range is lower than the first temperature range; and after applying the temporary substrate layer, separating the tape layer from the spalled layer.

Abstract: According to one embodiment, an electronic component includes a metal portion, a mold resin covering at least a part of the metal portion, and a molecular adhesion layer provided between a surface of the metal portion and the mold resin.

Abstract: In the fabrication of semiconductor packages, a leadframe is formed by masking and etching a metal sheet from both sides, and a plastic block is formed over a plurality of dice attached to die pads in the leadframe. A laser beam is used to form individual plastic capsules for each package, and a second laser beam is used to singulate the packages by severing the metal conductors, tie bars and rails between the packages. A wide variety of different types of packages, from gull-wing footed packages to leadless packages, with either exposed or isolated die pads, may be fabricated merely by varying the patterns of the openings in the mask layers and the width of the plastic trenches created by the first laser beam.

Abstract: A method of dicing a wafer may include forming a plurality of active regions in a wafer, each active region including at least one electronic component, the active regions extending from a first surface of the wafer into the wafer by a height and being separated by separation regions, the separation regions being free from metal, forming at least one trench in the wafer by plasma etching in at least one separation region from the first surface of the wafer. The at least one trench is extending into the wafer farther than the plurality of active regions. The method may further include processing a remaining portion of the wafer in the separation region to separate the wafer into individual chips.

Abstract: The semiconductor optical device has a chip of semiconductor lamination having a first semiconductor layer of a first conductivity type having a first surface, a second semiconductor layer of a second conductivity type opposite to the first conductivity type having a second surface, and an active layer sandwiched between the first semiconductor layer and the second semiconductor layer, the chip having side surface including a first side surface which is contiguous to the second surface, forms an obtuse angle with the second surface, extends across the second semiconductor layer and the active layer, and enters the first semiconductor layer, and a cracked surface which is contiguous to the first side surface, a first conductivity type side electrode formed on the first surface, and a second conductivity type side electrode formed on the second surface, wherein in-plane size of the semiconductor lamination is 50 ?m or less.

Abstract: A design method includes a process of preparing plural cutting members having different degrees of taper in a tip portion thereof, a process of preparing plural grooves on a front surface side having the same shape, a process of confirming a breakage status when a groove on a rear surface side is formed by the plural cutting members, and a process of selecting, when it is confirmed that both of a cutting member that causes breakage and a cutting member that does not cause the breakage are included, the degree of taper of the cutting member that does not cause the breakage as a tip shape of a cutting member to be used in a mass production process.

Abstract: A method of fabricating a plurality of light emitting elements includes forming a nitride semiconductor layer on a growth substrate, the nitride semiconductor layer including at least an n-type nitride semiconductor layer, an active layer made of a nitride semiconductor, and a p-type nitride semiconductor layer stacked in this order; forming a p-electrode layer, the p-electrode layer including portions that correspond to the light emitting elements; forming a p-passivation layer that includes portions between the portions of the p-electrode layer formed on the upper surface of the nitride semiconductor layer; forming a seed layer on the p-electrode layer and the p-passivation layer; forming an insulating layer having portions formed on an upper surface of the seed layer; forming a plating layer on the seed layer; and forming a plating substrate by removing the insulating layer to form spaces between portions of the plating layer.

Abstract: A method of processing a wafer having a device area where a plurality of devices are formed and a peripheral marginal area surrounding the device area on the front side of the wafer is disclosed. The devices are formed in regions defined by division lines. Each device has a plurality of bump electrodes on the front side. A first laser beam is applied through dicing tape from the back side along the boundary between the device area and the peripheral marginal area, with the focal point of the first laser beam set inside the wafer, thereby forming an annular modified layer inside the wafer. A second laser beam is applied through the dicing tape from the back side along each division line with the focal point of the second laser beam set inside the wafer, thereby forming a modified layer inside the wafer along each division line.

Abstract: A wafer processing method which includes a first tape attaching step of attaching a first tape to the front side of a wafer and mounting the wafer through the first tape to a first annular frame, a separating step of holding the wafer through the first tape on a chuck table and applying a laser beam to the boundary between an annular projection formed along the outer circumference of the wafer and a device area surrounded by the annular projection to cut the wafer and the first tape along this boundary, thereby separating the device area from the annular projection, and a removing step of removing the annular projection together with the first annular frame from the device area of the wafer in the condition where the annular projection is supported through the first tape to the first annular frame.

Abstract: The present invention discloses a new tool to slice crystal ingots by using laser beams. Ingot crystals of III-nitride such as GaN are immersed in alkali solutions and irradiated with scanned lines of laser beams to slice wafers out of the ingots. The method is expected to achieve approximately one order of magnitude smaller slicing loss with minimized slicing damage.

Abstract: A wafer-level packaging method of BSI image sensors includes the following steps: S1: providing a wafer package body comprising a silicon base, an interconnect layer, a hollow wall and a substrate; S2: cutting the wafer package body via laser in a first cutting process to separate the interconnect layer of adjacent BSI image sensors; and S3: cutting the wafer package body via a blade in a second cutting process to obtain independent BSI image sensors. As a result, damage of the interconnect layer and the substrate may be decreased to improve performance and reliability of the BSI image sensor.

Abstract: A method of singulating a semiconductor wafer with laser energy while the semiconductor wafer is supported on a mounting tape during singulation comprises the step of depositing a coating material onto a portion of the mounting tape adjacent to a perimeter of the semiconductor wafer to form a protective layer over the mounting tape. The semiconductor wafer is then cut with a laser beam such that the laser beam at least partially impinges upon the protective layer during cutting of the semiconductor wafer. After singulation of the semiconductor wafer, the protective layer is removed from the mounting tape.

Abstract: A method of processing a plate-shaped workpiece includes: a positioning step of mounting the plate-shaped workpiece on a support plate; a joining step of irradiating an outer peripheral portion of the plate-shaped workpiece mounted on the support plate with a laser beam to form a fusion bond region where the plate-shaped workpiece is fusion-bonded to the support plate at the outer peripheral portion of the plate-shaped workpiece, thereby fixing the plate-shaped workpiece onto the support plate; and a processing step of processing the plate-shaped workpiece after the joining step.

Abstract: A method of etching a substrate using a metal-assisted chemical etching process is provided. The method may include forming a metal catalytic layer to a predetermined thickness on a substrate and reacting the metal catalytic layer with the etching solution to form a porous surface in the metal catalytic layer and etch the substrate. When the metal catalytic layer is reacted with an etching solution, a porous surface may be formed on the metal catalytic layer.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device comprises forming through holes extending through a semiconductor substrate in a thickness direction to integrated circuits in chip areas, and forming a first mark opening and second mark openings in a dicing line. The method detects the first mark opening based on positions of the second mark openings. Then, the method performs alignment of exposure positions based on the position of the first mark opening to perform photolithography, thereby forming a resist pattern on the back side of the semiconductor substrate.

Abstract: Image projection utilizing light-emitting diodes on a silicon (LEDoS) substrate is described herein. LEDoS devices selectively activate LED pixels to produce light. Light can excite color conversion materials of the LEDoS devices to form color images. Images can be projected onto a projection surface.

Abstract: In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and applying a pressure substantially uniformly along the second major surface to batch separate the layer of material in the singulation lines. In one embodiment, a fluid filled vessel can be used to apply the pressure.

Abstract: The invention relates to a method for making a 3D nanostructure having a nanosubstructure, comprising the steps of: i) providing a mold comprising at least one sharp concave corner; ii) conformational depositing at least one structural material in the sharp concave corner; iii) isotropically removing structural material; iv) depositing at least one other structural material; v) removing earlier deposited structural material; vi) forming a nanosubstructure; and vii) removing the mold thereby providing the 3D nanostructure having the nanosubstructure.

Abstract: A wafer processing method including a wafer supporting step of attaching a front side of a dicing tape formed of synthetic resin to a back side of a wafer and supporting a peripheral portion of the dicing tape to an annular frame, a dicing tape heating step of heating a back side of the dicing tape attached to the wafer to soften the dicing tape, thereby flattening the back side of the dicing tape, and a modified layer forming step of applying a laser beam having a transmission wavelength to the wafer through the dicing tape from the back side thereof along the division lines in the condition where the focal point of the laser beam is set inside the wafer, thereby forming a modified layer inside the wafer along each division line.

Abstract: A method of manufacturing an epitaxial wafer, including a silicon substrate having a surface sliced from single-crystalline silicon and a silicon epitaxial layer deposited on the surface of the silicon substrate, includes an oxygen concentration controlling heat treatment process in which a heat treatment of the epitaxial layer is performed under a non-oxidizing atmosphere after the epitaxial growth such that an oxygen concentration of the surface of the silicon epitaxial layer is set to 1.0×1017 to 12×1017 atoms/cm3 (ASTM F-121, 1979).

Abstract: An optical device including a substrate and a light emitting layer formed on the front surface of the substrate. Both the front surface and the back surface of the substrate are parallel to each other and have substantially the same rectangular shape. The substrate has four side surfaces connecting the front surface and the back surface of the substrate. Of the four side surfaces, each of the two side surfaces adjacent to each other has a convex sectional shape between the front surface and the back surface of the substrate, and each of the other two side surfaces adjacent to each other has a concave sectional shape between the front surface and the back surface of the substrate.

Abstract: Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer.

Abstract: The present invention relates to an ultrasound transducer assembly (100) comprising ultrasound transducer elements (175, 175a) for transmitting ultrasound waves in a general transmission direction (A). Each of or each of part of the ultrasound transducer elements (175, 175a) comprises a piezoelectric layer (110, 110a) having a top surface, a bottom surface and a side surface with respect to the general transmission direction (A), as well as a bottom electrode layer (111, 111a) and a top electrode layer (112, 112a). A conductive layer (125) is applied at least partly on the side surface of at least one specific one (110a) of the piezoelectric layers, such that the conductive layer (125) is connected to the top electrode layer (112a) and the bottom electrode layer (111a) of said specific piezoelectric layer (110a).

Abstract: A method for debonding two temporary bonded wafers, includes providing a debonder comprising a top chuck assembly, a bottom chuck assembly, a static gantry supporting the top chuck assembly, an X-axis carriage drive supporting the bottom chuck assembly and an X-axis drive control configured to drive horizontally the X-axis carriage drive and the bottom chuck assembly from a loading zone to a process zone under the top chuck assembly and from the process zone back to the loading zone. Next, loading a wafer pair comprising a carrier wafer bonded to a device wafer via an adhesive layer upon the bottom chuck assembly at the loading zone oriented so that the unbonded surface of the device wafer is in contact with the bottom assembly. Next, driving the X-axis carriage drive and the bottom chuck assembly to the process zone under the top chuck assembly. Next, placing the unbonded surface of the carrier wafer in contact with the top chuck assembly and holding the carrier wafer by the top chuck assembly.

Abstract: Methods, systems, and devices are described for slicing and shaping materials using magnetically guided chemical etching. In one aspect, a method includes forming a pattern on a substrate by a mask, depositing a catalytic etcher layer on the patterned substrate, a magnetic guide layer on the etcher layer, and a protection layer on the guide layer, etching the substrate by applying an etching solution to the substrate that chemically reacts with the etcher layer and etches material from the substrate at exposed regions not covered by the mask, steering the composite etching structure into the substrate during the etching by an applied magnetic field that creates a force on the guide layer to direct the etching, in which the steering defines the shape of the sliced regions of the etched substrate, and removing the etched material, the mask, and the composite etching structure to produce a sliced material structure.

Abstract: Disclosed herein is a wafer processing method including a wafer supporting step of mounting an adhesive film for die bonding on the back side of a wafer, attaching a dicing tape to the adhesive film, and supporting the peripheral portion of the dicing tape to an annular frame, wherein the wafer has already been divided into individual device chips along division lines formed on the front side or a break start point has already been formed inside the wafer along each division line, a protective film forming step of applying a water-soluble resin to the front side of the wafer and/or the peripheral portion of the adhesive film projecting from the outer circumference of the wafer, thereby forming a protective film from the water-soluble resin, and an adhesive film breaking step of expanding the dicing tape to thereby break the adhesive film along the individual device chips.

Abstract: A method of manufacturing a light-emitting device comprising the steps of cutting a substrate by a laser beam to form a cavity in the substrate and generate a by-product directly on the substrate by the cutting, and removing the by-product by a chemical solution containing an acid under a predetermined cleaning temperature.

Abstract: Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side.

Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

Abstract: Laser and plasma etch wafer dicing where a mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The semiconductor wafer is coupled to a film frame by an adhesive film. The mask is patterned by laser scribing to provide a patterned mask with gaps. The laser scribing exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is plasma etched through the gaps in the patterned mask while the film frame is maintained at an acceptably low temperature with a chamber shield ring configured to sit beyond the wafer edge and cover the frame. The shield ring may be raised and lowered, for example, on lifter pins to facilitate transfer of the wafer on frame.

Abstract: A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate containing a nanowire mesh device and a second portion of the SOI substrate containing a FINFET device. The nanowire mesh device including stacked and spaced apart semiconductor nanowires located on the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; and a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region. The FINFET device including spaced apart fins on a top semiconductor layer on the second portion of the substrate; and a gate region over at least a portion of the fins.

Abstract: A method serves to produce optoelectronic semiconductor components. A leadframe assemblage includes a number of leadframes. The leadframes each comprise at least two leadframe parts and are connected together at least in part via connecting webs. Electrical connections are attached between neighboring leadframes. A potting body connects the leadframes and the leadframe parts mechanically together. At least some of the connecting webs are removed and/or interrupted, the resulting structure is singulated into the semiconductor components.

Abstract: A semiconductor wafer, includes: a plurality of element regions; a surface electrode that is disposed in each of the plurality of element regions; an insulating layer that is disposed in each of the plurality of element regions and of which height from a front side surface of the semiconductor wafer is higher than that of the surface electrode in a periphery of the surface electrode; and a dicing line groove that is formed in a front side surface of the semiconductor wafer, that surrounds the surface electrode with the insulating layer therebetween, of which height from the front side surface of the semiconductor wafer is lower than that of the insulating layer, and that extends to a perimeter of the semiconductor wafer; in which the insulating layer is formed with a communication passage that extends from a side of the surface electrode to the dicing line groove.

Abstract: The present invention provides a method for plasma processing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; loading a work piece onto the work piece support, the work piece having a support film, a frame and the substrate; providing a cover ring above the work piece, the cover ring having at least one perforated region, and at least one non-perforated region; generating a plasma using the plasma source; and processing the work piece using the generated plasma.

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma processing apparatus includes a processing chamber having a chamber wall. The plasma processing apparatus also includes a plasma source in an upper portion of the processing chamber. A sample support is included for situating a sample below the plasma source. An actively-cooled shadow ring having a cooling channel therein for cooling fluid transport is fixedly attached to the chamber wall of the processing chamber, between the plasma source and the sample support.

Abstract: A camera system including, a first image sensor array and a second image sensor array wherein the first image sensor array is designed for a first focal plane in front of the camera, and the second image sensor array is designed for a second focal plane in front of the camera, wherein the distance to the first focal plane is substantially different than the distance to the second focal plane.