Abstract: A method for manufacturing a semiconductor device is provided including: providing a reinforcing member on one surface of a wiring substrate that has a first region where a semiconductor chip is mounted and a second region around the first region, and has terminals extending from the first region to the second region formed on another surface thereof in a manner that the reinforcing member overlaps the terminals and a part thereof protrudes from the first region to the second region; cutting the terminals along a boundary between the first region and the second region; and continuously cutting the reinforcing member from an inboard side thereof to an outboard side along the boundary between the first region and the second region.

Abstract: A method for manufacturing a multilayered substrate for a semiconductor device, as well as a semiconductor device, is provided, the multilayered substrate exhibiting an excellent thermal conduction property and an excellent heat spreading effect without occurrence of warp and deformation. A diamond layer is formed through vapor phase deposition on one principal surface of a first silicon substrate by a CVD method. A SiO2 layer is formed on this diamond layer. A SiO2 layer is formed on a surface of a second silicon substrate by a thermal oxidation method. The diamond layer is bonded to the second silicon substrate with SiO2 layers disposed on both the diamond layer and the second silicon substrate therebetween. The first silicon substrate is removed by dissolution through etching to expose the surface of the diamond layer. A silicon layer serving as a semiconductor layer is formed on the diamond layer by a CVD method.

Abstract: The present invention relates to a method for dividing a substrate into a number of individual chip parts, comprising the steps of: forming a number of chip parts in the substrate, comprising, for each chip part, of arranging recesses in the substrate for containing fluid; arranging one or more breaking grooves in the substrate along individual chip parts; applying mechanical force to the substrate to break the substrate along the breaking grooves. The invention also relates to a substrate as well as a chip part.

Abstract: An electrode insulator and method for fabricating the same, wherein a T-shape electrode insulator made of inorganic dielectric material is fabricated perpendicular to the first electrode formed on the substrate, and insulating the second electrode from the first electrode. Inorganic films are used twice to form the insulator, and the T-shaped insulator fabricated is composed of two parts, the lower part is a column of ridge and the upper part is a horizontal cover to form an overhanging portion. Thereby, the overhanging portion can prevent metal film of the second electrode from forming between two insulators, so that the insulation can be achieved.

Abstract: A method of dividing a wafer along predetermined dividing lines, comprising the steps of a deteriorated layer forming step for applying a pulse laser beam capable of passing through the wafer along the dividing lines to form deteriorated layers in the inside of the wafer along the dividing lines; an extensible protective tape affixing step for affixing an extensible protective tape to one side of the wafer before or after the deteriorated layer forming step; and a dividing step for dividing the wafer along the deteriorated layers by expanding the protective tape affixed to the wafer after the deteriorated layer forming step.

Abstract: A QFP exposed pad package which includes leads exposed within the bottom surface of the package body of the package in addition to those gull-wing leads protruding from the sides of the package body. Those leads exposed within the bottom surface of the package body are created through the utilization of a standard leadframe with additional lead features that are electrically isolated subsequent to a molding process through the use of a partial saw method.

Abstract: Semiconductor chip assemblies incorporating flexible, sheet-like elements having terminals thereon overlying the front or rear face of the chip to provide a compact unit. The terminals on the sheet-like element are movable with respect to the chip, so as to compensate for thermal expansion. A resilient element such as a compliant layer interposed between the chip and terminals permits independent movement of the individual terminals toward the chip driving engagement with a test probe assembly so as to permit reliable engagement despite tolerances.

Abstract: A method which can divide a semiconductor wafer sufficiently precisely along a street by use of a laser beam, while fully avoiding or suppressing contamination of circuits formed in rectangular regions on the face of the semiconductor water, and without causing chipping to the rectangular regions on the face. A laser beam is applied from beside one of the back and the face of a semiconductor substrate and focused onto the other of the back and the face of the semiconductor substrate, or the vicinity thereof, to partially deteriorate at least a zone ranging from the other of the back and the face of the semiconductor substrate to a predetermined depth.

Abstract: In the high-frequency module of the present invention, an insulating resin is formed so as to seal a high-frequency semiconductor element mounted on a surface of a substrate and further to seal electronic components. Furthermore, a metal thin film is formed on the surface of the insulating resin. This metal thin film provides an electromagnetic wave shielding effect.

Abstract: A microelectromechanical system switch may be formed with a protrusion defined on the substrate which makes contact with a deflectable member arranged over the substrate. The deflectable member may, for example, be a cantilevered arm or a deflectable beam. The protrusion may be formed in the substrate in one embodiment using field oxide techniques.

Abstract: The present invention includes providing a leadframe including a metal layer formed on an upper surface of the leadframe and a plurality of units in an array arrangement, in which each unit includes a die pad, a plurality of leads, and a plurality of outer dambars, adhering a die to the die pad, forming a plurality of conductive wires to electrically connect bond pads of the die with bond regions of the leads, forming an encapsulation covering the leadframe, forming a patterned photoresist layer on a lower surface of the leadframe to expose a plurality of interval regions and the outer dambars, performing an etching process to expose the metal layer located in the interval regions and the outer dambars, cutting off the metal layer located in the interval regions by a half cutting process, and performing a singulation process to singulate the units.

Abstract: A sacrificial layer is formed in a recess of a substrate, and leads extending from the substrate into an area of the sacrificial layer are formed. A cut is formed from the bottom surface of the substrate, the cut extending from the bottom surface to the area of the sacrificial layer via the substrate, then the sacrificial layer is removed. A probe unit can be obtained having the leads whose front portions extend beyond the edge of the substrate. A through conductor may be formed in a through hole formed in a substrate. Leads may be formed on a photosensitive etching glass substrate to thereafter selectively etch the chemically cutting type glass.

Abstract: A vertically integrated structure includes a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS. The structure includes a metal stud connecting a surface of the chip and the MEMS; the MEMS has an anchor portion having a conducting pad on an underside thereof contacting the metal stud. The MEMS is spaced from the chip by a distance corresponding to a height of the metal stud, and the MEMS includes a doped region in contact with the conducting pad. In particular, the MEMS may include a cantilever structure, with the end portion including a tip extending in the vertical direction. A support structure (e.g. of polyimide) may surround the metal stud and contact both the underside of the MEMS and the surface of the chip. A temporary carrier plate is used to facilitate handling of the MEMS and alignment to the chip.

Abstract: Spring structures are subjected to pre-release and post-release annealing to tune their tip height to match a specified target. Post-release annealing increases tip height, and pre-release annealing decreases tip height. The amount of tuning is related to the annealing temperature and/or time. Annealing schedules are determined for a pre-fabricated cache of unreleased spring structures such that finished spring structures having a variety of target heights can be economically produced by releasing/annealing the cache according to associated annealing schedules. Selective annealing is performed using lasers and heat absorbing/reflecting materials. Localized annealing is used to generate various spring structure shapes. Both stress-engineered and strain-engineered spring structures are tuned by annealing.

Abstract: A method for forming a semiconductor die, comprising forming a trench in a surface of the die; filing the trench with a sacrificial material; patterning the die to form a series of channels extending substantially perpendicularly to the trench; depositing a conductive material in the channels; removing at least a portion of the sacrificial material; and removing portions of the die under the trench so as to separate a portion of the die on one side of the trench from a portion on another side of the trench. The sacrificial material may be patterned so that the channels extend so as to be partially in a portion of the die and partially a portion of the sacrificial material. A series of structures are formed having dies with micro-pins.

Abstract: A wafer level fabricated chip scale integrated circuit package having an air gap formed between the integrated circuit die of the package and compliant leads located over and conductively attached to the die is described. Contact bumps offset on the compliant leads provide for connection of the integrated circuit package to other substrates. In some embodiments, the compliant leads include a conductive layer overlaid with an outer resilient layer, and may further include an inner resilient layer beneath the conductive layer. The outer resilient layer has a via formed through it exposing the underlying conductive layer. The via is offset along the compliant lead a horizontal distance from the bond pad to which the compliant lead is conductively coupled. The chip scale package provides a highly compliant connection between the die and any substrate that the die is attached to.

Abstract: A wiring pattern is formed over a semiconductor wafer, and an external terminal is formed on the wiring pattern. The wiring pattern extends from a pad which is part of an interconnect to an integrated circuit formed in the semiconductor wafer. A non-resin layer of a non-resin material is formed in a first region of the semiconductor wafer. A resin layer is formed in a second region which is a region of the semiconductor wafer other than the first region by utilizing the non-resin layer. The semiconductor wafer is cut long the first region.

Abstract: A semiconductor wafer saw and method of using the same for dicing semiconductor wafers including a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.

Abstract: A semiconductor wafer is applied to a support disk via an intervening adhesive layer with the front side of the semiconductor wafer facing the adhesive layer, which is sensitive to a certain exterior factor for reducing its adhesive force; the semiconductor wafer is ground on the rear side; the wafer-and-support combination is applied to a dicing adhesive tape with the so ground rear side facing the dicing adhesive tape, which is surrounded and supported by the circumference by a dicing frame; the certain exterior factor is effected on the intervening adhesive layer to reduce its adhesive force; and the intervening adhesive layer and support disk are removed from the semiconductor wafer or chips without the possibility of damaging the same.

Abstract: The invention is aimed to prevent that fall of characteristic of a solar battery and producing yield caused by particles of powder condition generating from working part at laser beam process in the method producing the solar battery by laser beam process. The constitution of the invention is characterized by comprising: a first step forming the lower electrode and the semiconductor layer on the insulating substrate by laminating; a second step forming a protective film on surface of the semiconductor; a third step forming an opening portion at the semiconductor layer, or the semiconductor layer and the lower electrode by laser beam process after the second step; and a fourth step removing the protective film.

Abstract: A device manufacturing method capable of imaging structures on both sides of a substrate, is presented herein. One embodiment of the present invention comprises a device manufacturing method that etches reversed alignment markers on a first side of a substrate to a depth of 10 ?m, the substrate is flipped over, and bonded to a carrier wafer and then lapped or ground to a thickness of 10 ?m to reveal the reversed alignment markers as normal alignment markers. The reversed alignment markers may comprise normal alignment patterns overlaid with mirror imaged alignment patterns.

Abstract: A vertically integrated structure includes a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS. The MEMS has an anchor portion having a conductor therethrough, by which it is connected to a substrate. The chip is attached to the MEMS substrate in a direction normal to the substrate surface, so as to make a conductive path from the chip to the MEMS. The chip may be attached by bonding the conductor to C4 metal pads formed on the chip, or by bonding the conductor to metal studs on the chip. The MEMS substrate may be thinned before attachment to the chip, or may be removed from the underside of the MEMS. A temporary carrier plate is used to facilitate handling of the MEMS and alignment to the chip.

Abstract: This invention is to support a plate member such as a bonded substrate stack in a horizontal state without coming into contact with one surface of the member and also to efficiently progress separation. Separation is executed while arranging a bonded substrate stack (50) generated by bonding a seed substrate (10) to a handle substrate (20) such that the seed substrate (10) remains on the lower side. At the first stage, the peripheral portion is separated while causing a first substrate support section (101) to chuck and support the central portion of the lower surface of the bonded substrate stack (50). Then, at the second stage, the central portion is separated while causing a second substrate support section (102) to support the lower peripheral portion and side of the bonded substrate stack (50).

Abstract: A tool and method is described to decide partial wafer sizes to process multiple random sizes of wafers in pick and place equipment for wafermap operation. The tool identifies the wafer and gets wafermap data. The position of one or more cutters is displayed. The position of the cutters relative to the wafer is displayed. The tool generates and displaying the results of the type of dies in each partial that would result from a cut according to said displayed position of the cutters.

Abstract: A method for forming protective layers on a plurality of semiconductor device components carried by a fabrication substrate includes applying a layer of protective material to surfaces of the semiconductor device components. The layer of protective material is then severed and the fabrication substrate is at least partially severed. Cracks and delaminated regions that are formed during severing are then healed. The protective material may be applied as a preformed sheet or in a liquid form, then at least partially cured or hardened. If a curable polymer is employed as the protective material, it may be partially cured before severing is effected, then self-healed before being fully cured. Alternatively, a thermoplastic material may be used as the protective material, with healing being effected by heating at least regions of the thermoplastic material. Semiconductor device components, including chip-scale packages, which are formed by the method are also disclosed.

Abstract: Disconnection of wiring and deterioration of step coverage are prevented to offer a semiconductor device of high reliability. A pad electrode formed on a silicon die is connected with a re-distribution layer on a back surface of the silicon die. The connection is made through a pillar-shaped conductive path filled in a via hole penetrating the silicon die from the back surface of the silicon die to the pad electrode.

Abstract: An unsingulated semiconductor wafer is provided. Electrical interconnect elements are formed on the unsingulated wafer such that the interconnect elements are electrically connected to terminals of the semiconductor dice composing the wafer. At least a portion of the interconnect elements extend beyond the boundaries of the dice into the scribe streets separating the individual dice. Thereafter, the wafer is singulated into individual dice.

Abstract: A method of using protective caps (160) applied to a first side of a wafer (150) in the production of microfabricated devices (152), such as micro-electro-mechanical systems (MEMS) devices. One cap (160) covers each microfabricated device or group respectively, such that a gap remains between adjacent protective caps. One or more etches are applied to the gaps between the caps to remove material and separate the wafer into separate units.

Abstract: The electronic component has semiconductor chips that are stacked on one another. On their active top sides, the chips having interconnects for rewiring to contact areas through contacts formed on the sawn edges of the semiconductor chip. The electronic components of overlying and underlying semiconductor chips are thus connected to one another via the through contacts.

Abstract: An etching mask is made of a metal such as Permalloy (NiFe) and has a T-shaped cross section made up of a vertical bar having width W1 and a lateral bar having width W2. Through ion beam etching with the etching mask, the region in the surface of a workpiece not covered with the mask is selectively removed by the ion beams applied thereto. In the mask the vertical bar has a region obstructed by the lateral bar and a redeposit portion. As a result, the region of the vertical bar near the interface between the workpiece and the vertical bar that substantially determines the pattern width does not change in width. Consequently, a pattern of the workpiece on which etching has been performed has the top width and bottom width substantially equal to width W1 of the vertical bar of the mask. The pattern is rectangular in cross section.

Abstract: Notches are formed in a surface of a wafer on which semiconductor elements have been formed. Then, a surface protection tape is stuck to the element-formed surface of the wafer. Subsequently, the wafer is cleaved along a crystal orientation using the notches as starting points. Finally, a back surface of the wafer is ground.

Abstract: Devices and method of fabrication thereof are disclosed. A representative device includes one or more lead packages. The lead packages include a substrate including a plurality of die pads, an overcoat polymer layer, a plurality of sacrificial polymer layers disposed between the substrate and the overcoat polymer layer, and a plurality of leads. Each lead is disposed upon the overcoat polymer layer having a first portion disposed upon a die pad. The sacrificial polymer layer can be removed to form one or more air-gaps.

Abstract: To improve the connection reliability at the time of packaging a semiconductor device and to make the method management easy in a semiconductor device manufacturing method. The semiconductor device comprises: a tub 1e for supporting a semiconductor chip 2; a sealing body 3 formed by sealing the semiconductor chip 2 with a resin; a plurality of leads 1a made of a copper alloy, exposed to the back face 3a of the sealing body 3, and having a soldered layer 8 on the exposed mounted face 1d; and wires 4 for connecting the pads 2a of the semiconductor chip 2 and the corresponding leads 1a.

Abstract: A structure includes holes formed in a layer of tape. The holes are aligned over active areas on chips formed in a wafer. A custom vacuum chuck with a plurality of suction ports is aligned on the tape such that the suction ports contact only the tape and not the hole portions. Flats of the custom vacuum chuck are formed so that a perimeter of the flats contacts, and rests on, the tape. In addition, the flats of the custom vacuum chuck are formed so that the flats cover the entire active area on the first surface of each of the chips. Consequently, the combination of the custom vacuum chuck and the single layer of tape form a protective cavity over the active areas of the chips during singulation from the wafer.

Abstract: The invention relates to a method for fabricating a microcontact spring on a substrate (1) with at least one contact pad (2) and a first insulator layer (13) with a window above the contact pad (2).

Abstract: A microelectronic connection component includes a support such as a dielectric sheet having elongated leads extending along a surface. The leads have terminal ends permanently connected to the support and tip ends releasably connected to the support. The support is juxtaposed with a further element such as a semiconductor chip or wafer, and tip ends of the leads are bonded to contacts on the wafer using a bonding tool advanced through holes in the support. After bonding, the support and the further element are moved away from one another so as to deform the leads.

Abstract: A laser sintering system is provided for sintering a die having a serrate edge. The laser sintering system comprises a laser generator for generating a laser beam and a movable carriage for carrying said die. The laser beam sinters the serrate edge of said die into a smooth edge. A method of sintering a die, the die having a serrate edge, comprises the following steps of providing a die and using a laser beam sintering the serrate edge of said die into a smooth edge. A die has a smooth edge sintered by a laser beam.

Abstract: Chip-size semiconductor packages (“CSPs”) containing multiple stacked dies are disclosed. The dies are mounted on one another in a stack such that corresponding ones of the vias in the respective dies are coaxially aligned. An electrically conductive wire or pin is in each set of aligned vias and soldered to corresponding ones of the terminal pads. The pins include portions protruding from the stack of dies that serve as input-output terminals of the package. Heat spreaders can be interleaved between the stacked dies to enhance heat dissipation from the package.

Abstract: In certain implementations, a method for chip singulation is provided including etching a frontside dicing trench from a front side of a wafer, forming a temporary holding material, in the frontside dicing trench, etching a backside dicing trench from a back side of the wafer along the frontside dicing trench, removing the temporary holding material and releasing the chip from the wafer or an adjacent chip. Certain implementations may include etching through surface deposited layers on the front side of the wafer. Certain implementations may further include completely filling the frontside dicing trench with the temporary holding material and etching the backside dicing trench to the temporary holding material that is in the frontside dicing trench, such that removing the temporary holding material self-dices the wafer. Certain implementations may include surrounding MEMS structures with the temporary holding material so as to hold the structures during etching of the back side of the wafer.

Abstract: A method of making a chip-type electronic device includes a first through a third process steps. In the first step, a first electrode is formed on an insulating aggregate board. In the second step, a second electrode overlapping the first electrode is formed on the aggregate board. In the third step, the aggregate board is cut along a predetermined cutting line. The first electrode is formed as spaced from the cutting line, whereas the second electrode extends over the cutting line.

Abstract: Printed tape is used to form a leads on chip (LOC) ball grid array (BGA) semiconductor device. Leads for a plurality of devices may be applied simultaneously. Bond wires, glob top encapsulant, and the ball grid arrays for the devices may be formed in single process steps. A low temperature curing adhesive material may be used to reduce the effects of differential thermal expansion between the tape and surface of the wafer. In another embodiment of the invention, anisotropically conductive adhesive material is used to connect bond pads on a wafer to leads printed on a tape.

Abstract: A method and apparatus for manufacturing a semiconductor physical quantity sensor according to the present invention achieves the high sensing accuracy and reliability and prevents a sticking phenomenon. Specifically, a semiconductor physical quantity sensor is cleaned by a displacement liquid and is dried while a SOI substrate is revolving. The number of revolutions is determined so that a suction force (FS), which acts on a silicon substrate by a surface tension of the displacement liquid, a sensor spring force FK and a centrifugal force (Fr) generated by the acceleration in the revolution can satisfy the following condition: (FK+Fr)>FS. In order to prevent the sticking phenomenon after the stop of the spray, the semiconductor physical quantity sensor is dried by spraying an inert gas such as nitrogen including minus ions so that the revolving SOI substrate can eliminate static electricity generated by friction of the air flow.

Abstract: A method and process sequence for accurately aligning (die to interconnect metal on flex substrate such as polyimide flex is described. A mask for via formation is first patterned in a metal layer on the bottom surface of the flex substrate. Die attach means such as die attach adhesive is then applied to the top side of flex substrate. The bond pads on die are locally, adaptively aligned to the patterned metal via mask on the flex with high accuracy. Vias down to the die bond pads are then created by either plasma etching or excimer laser ablation through the existing aligned metal mask on the flex substrate, and interconnect metal is then deposited, patterned and etched. As a result of this process, the flex metal interconnect artwork does not have to be customized for each die misplacement using “adaptive lithography”. Lower cost commercially available lithography equipment can be used for processing, reducing capital equipment and processing cost.

Abstract: A method is provided for processing a semiconductor wafer having a chip region where chips are formed and a non-chip region where chips are not normally formed. The method includes the steps of forming trench isolation regions in the semiconductor wafer, and forming dummy trench isolation regions in at least a part of the non-chip region of the semiconductor wafer.

Abstract: A method for attaching an integrated circuit chip to an organic substrate comprising the steps of providing an integrated circuit chip having an active and a passive surface, said active surface including a protective polymer layer; activating said polymer layer by exposing it to reactive ion etching plasma, thereby increasing the surface roughness and imparting affinity to adhesion; providing an electrically insulating substrate having first and second surfaces; and contacting said second surface of said substrate to said activated polymer layer on said chip, whereby strong adhesion is exerted at the interface between said layer and said substrate, directly attaching said substrate to said chip.

Abstract: An object of the present invention is to provide a method of manufacturing a semiconductor device which enables a decrease in mounting area on a printed circuit board and an increase in space efficiency on the printed circuit board.

Abstract: The invention is a lead frame that has leads formed in two levels during the etching process in which the lead frame is formed. A lead frame form (40), or continuous strip of lead frame material, is coated on two sides with a photo resist material (41,43). Each photo resist coated side is patterned to define leads on the lead frame. The lead patterns (41,43, 42,44) on the two sides are offset from each other so that patterns on one side of the lead frame material alternate with the patterns on the other side of the lead frame material. Both sides of the photo resist patterned lead frame material are etched to a depth exceeding the thickness of a lead. The photo resist (41,43) material is then removed. The resulting lead frame has leads (50-56)that are in two levels, each level having leads offset by a lead width from the other level, but with an effective zero distance between leads horizontally.

Abstract: A method and apparatus for singulating semiconductor wafers is described. The method comprises the steps of aiming a laser beam at a layer placed over the substrate; absorbing energy from the laser beam into the layer; forming scribe lines in the layer by scanning the laser beam across the layer; and cutting through the substrate along the scribe lines with a saw blade to singulate the wafer. The apparatus includes a laser placed over the coating layer of the substrate, and a saw blade mounted over a surface of the substrate. The coating layer has a first absorption coefficient relative to a wavelength of the laser and the semiconductor substrate has a second absorption coefficient less than the first absorption coefficient. Energy from the laser beam is absorbed into the coating layer to form scribe lines therein, and the saw blade cuts through the substrate along the scribe lines.

Abstract: The present invention is a semiconductor device having the semiconductor element 1 obtained by cutting a semiconductor wafer with the electrode pad 2 formed on one side along the scribe line, the semiconductor element protective layer 7 on the semiconductor element 1 which has the opening 7(1) on the pad 2, the stress cushioning layer 3 on the layer 7 which has the opening 3(1) on the pad 2, the lead wire portion 4 reaching the layer 3 from the electrode pad 2 via the openings 7(1) and 3(1), the external electrodes 6 on the lead wire portion 4, and the conductor protective layer 5 on the layer 3 and the layer 7, the layer 3, and the conductor protective layer 5 form the respective end faces on the end surface 1(1) of the semiconductor element 1 inside the scribe line and expose the range from the end face of the end surface 1(1) to the inside of the scribe line.

Abstract: A method is provided for processing a semiconductor wafer having a chip region where chips are formed and a non-chip region where chips are not normally formed. The method includes the steps of forming trench isolation regions in the semiconductor wafer, and forming dummy trench isolation regions in at least a part of the non-chip region of the semiconductor wafer.