Abstract: A method of processing a substrate, includes: loading the substrate having a silicon-containing film formed thereon into a processing container; a first process of modifying the silicon-containing film by supplying a processing gas containing a halogen-containing gas and a basic gas to the substrate, in a state in which an internal pressure of the processing container is set to a first pressure, to generate a reaction product; a second process of vaporizing the reaction product by setting the internal pressure of the processing container to a second pressure lower than the first pressure; and alternately repeating the modifying the silicon-containing film and the vaporizing the reaction product, wherein subsequent rounds of the first process following the initial first process in the alternately repeating the modifying the silicon-containing film and the vaporizing the reaction product includes supplying the processing gas to the substrate on which the reaction product remains.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.

Abstract: Systems and methods for processing a workpiece are provided. In one example, a method includes exposing the workpiece to a first gas mixture when the workpiece is at a first temperature to conduct a doped silicate glass etch process. The first gas mixture can include hydrofluoric acid (HF) vapor. The doped silicate glass etch process at least partially removes the doped silicate glass layer at a first etch rate that is greater than a second etch rate associated with removal of the at least one second layer. The method can include heating the workpiece to a second temperature. The second temperature is greater than the first temperature. The method can include exposing the workpiece to a second gas mixture when the workpiece is at a second temperature to remove a residue from the workpiece.

Abstract: An energy conversion device for conversion of chemical energy into electricity. The energy conversion device has a first and second electrode. A substrate is present that has a porous semiconductor or dielectric layer placed thereover. The porous semiconductor or dielectric layer can be a nano-engineered structure. A porous catalyst material is placed on at least a portion of the porous semiconductor or dielectric layer such that at least some of the porous catalyst material enters the nano-engineered structure of the porous semiconductor or dielectric layer, thereby forming an intertwining region.

Abstract: Forming a semiconductor device that includes a memory cell array may include performing a switching firing operation on one or more memory cells of the memory array to cause a threshold voltage distribution associated with threshold switching devices in the memory cells to be reduced. The switching device firing operation may be performed such that the threshold voltage distribution is reduced while maintaining the one or more threshold switching devices in the amorphous state. Performing the switching device firing operation on a threshold switching device may include heating the threshold switching device, applying a voltage to the threshold switching device, applying a current to the threshold switching device, some combination thereof, or the like.

Abstract: The present invention provides methods for purifying a layer of carbon nanotubes comprising providing a precursor layer of substantially aligned carbon nanotubes supported by a substrate, wherein the precursor layer comprises a mixture of first carbon nanotubes and second carbon nanotubes; selectively heating the first carbon nanotubes; and separating the first carbon nanotubes from the second carbon nanotubes, thereby generating a purified layer of carbon nanotubes. Devices benefiting from enhanced electrical properties enabled by the purified layer of carbon nanotubes are also described.

Abstract: A phase change memory element and method of forming the same. The memory element includes first and second electrodes. A first layer of phase change material is between the first and second electrodes. A second layer including a metal-chalcogenide material is also between the first and second electrodes and is one of a phase change material and a conductive material. An insulating layer is between the first and second layers. There is at least one opening in the insulating layer providing contact between the first and second layers.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.

Abstract: A rectifying antenna device is disclosed. The device comprises a pair of electrode structures, and at least one nanostructure diode contacting at least a first electrode structure of the pair and being at least in proximity to a second electrode structure of the pair. At least one electrode structure of the pair receives AC radiation, and the nanostructure diode(s) at least partially rectifies a current generated by the AC radiation.

Abstract: An SCR-type component of vertical structure has a main upper electrode formed on a silicon region of a first conductivity type which is formed in a silicon layer of a second conductivity type. The silicon region is interrupted in first areas where the material of the silicon layer comes into contact with the upper electrode, and is further interrupted in second areas filled with resistive porous silicon extending between the silicon layer and the main upper electrode.

Abstract: A method for forming through substrate vias (TSVs) in a non-conducting, glass substrate is disclosed. The method involves patterning a silicon template substrate with a plurality of lands and spaces, bonding a slab or wafer of glass to the template substrate, and melting the glass so that it flows into the spaces formed in the template substrate. The template substrate may then be removed to leave a plurality of TSVs in the glass slab or wafer.

Abstract: Methods for processing a substrate are described herein. Methods can include positioning a substrate with an exposed surface comprising a silicon oxide layer in a processing chamber, biasing the substrate, treating the substrate to roughen a portion of the silicon oxide layer, heating the substrate to a first temperature, exposing the exposed surface of the substrate to ammonium fluoride to form one or more volatile products while maintaining the first temperature, and heating the substrate to a second temperature, which is higher than the first temperature, to sublimate the volatile products.

Abstract: Provided are a deposition substrate of a deposition apparatus, a method of forming a layer using the same, and a method of manufacturing an organic light emitting diode (OLED) display device. The method of forming a layer using the deposition substrate includes preparing a substrate, forming a heating conductive layer for Joule heating on the substrate, forming a first insulating layer on the heating conductive layer for Joule heating and including a groove or hole, forming a deposition material layer on a top surface of the first insulating layer having the groove or hole, and applying an electric field to the heating conductive layer for Joule heating to perform Joule-heating on the deposition material layer. Thus, the method is suitable for manufacturing a large-sized device.

Abstract: A method for changing reflectance or resistance of a region in an optoelectronic memory device. Changing the reflectance of the region includes sending an electric current through the region to cause a reflectance change in the region. Changing the resistance of the region includes: projecting a laser beam at a first beam intensity on the region, resulting in the region changing from a first to a second different resistance value; electrically reading the second resistance value during which an optical signal carried by the laser beam has a first digital value; after electrically reading the second resistance value, the laser beam is projected at a second beam intensity on the region resulting in the region changing from the second to the first resistance value; and electrically reading the first resistance value of the region while the laser beam is being projected on the region at the second beam intensity.

Abstract: A manufacturing method of a semiconductor device in which the threshold is corrected is provided. In a semiconductor device including a plurality of transistors each includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit for supplying a signal to the gate electrode and a circuit for supplying a signal to the source or drain electrode are electrically separated from each other. The process is performed in the state where the potential of the former circuit is set higher than the potential of the latter circuit.

Abstract: A method for manufacturing a memory device includes forming a plurality of active layers alternating with insulating layers on a substrate where the active layers include an active material, etching the active layers and insulating layers to define a plurality of stacks of active strips, and after the etching, causing crystal growth in the active strips. The substrate can have a single crystalline surface with a crystal structure orientation, and the crystal growth in the active material can form crystallized material having the crystal structure orientation of the substrate at least near side surfaces of the active strips. Causing crystal growth includes depositing a seeding layer over the plurality of stacks and the substrate, where the seeding layer is in contact with the side surfaces of the active strips, and in contact with the substrate. The method can include, after causing crystal growth, removing the seeding layer.

Abstract: A processing method and apparatus uses at least one electric field applicator (34) biased to produce a spatial-temporal electric field to affect a processing medium (26), suspended nano-objects (28) or the substrate (30) in processing, interacting with the dipole properties of the medium (26) or particles to construct structure on the substrate (30). The apparatus may include a magnetic field, an acoustic field, an optical force, or other generation device. The processing may affect selective localized layers on the substrate (30) or may control orientation of particles in the layers, control movement of dielectrophoretic particles or media, or cause suspended particles of different properties to follow different paths in the processing medium (26). Depositing or modifying a layer on the substrate (30) may be carried out.

Abstract: In some embodiments, a method for etching features into a substrate may include exposing a substrate having a photoresist layer disposed atop the substrate to a first process gas to form a polymer containing layer atop sidewalls and a bottom of a feature formed in the photoresist layer, wherein the first process gas is selectively provided to a first area of the substrate via a first set of gas nozzles disposed within a process chamber and; exposing the substrate to a second process gas having substantially no oxygen to etch the feature into the substrate, wherein the second process gas is selectively provided to a second area of the substrate via a second set of gas nozzles disposed in the process chamber.

Abstract: An electrical device includes a semiconductor material. The semiconductor material includes a first region of the semiconductor material having a first conductivity type, a second region of the semiconductor material having a second conductivity type complementary to the first conductivity type and an intermediate region of the semiconductor material between the first region and the second region. The first and second regions lie next to each other the intermediate region so as to form a diode structure. A shape of the intermediate region tapers from the first region to the second region.

Abstract: A graphene laminate includes a first piezoelectric material layer having a negatively-charged surface and a positively-charged surface, a first graphene layer under the first piezoelectric material layer, the first graphene layer contacting the positively-charged surface of the first piezoelectric material layer, a second graphene layer underlying the first graphene layer, and a second piezoelectric material layer under the second graphene layer, the second piezoelectric material layer having a negatively-charged surface and a positively-charged surface, the negatively-charged surface contacting the second graphene layer.

Abstract: A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed on the surface of the substrate. The electrically insulating portion of the substrate is interposed between the bulk portion of the substrate and the second graphene electrode. The second graphene electrode is disposed opposite the first graphene electrode to define an exposed substrate area therebetween.

Abstract: The invention provides a method for assembling semiconducting nanowires, which method can include providing a mixture comprising a dielectric solvent and two or more semiconducting nanowires, wherein the semiconducting nanowires can be the same or different; exposing the mixture to an electrostatic charge under lighting conditions; and allowing macroscopic nanowire alignment to occur, wherein each nanowire is substantially oriented along the direction of the applied electric field.

Abstract: An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.

Abstract: A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.

Abstract: A method of depositing semiconductor nanocrystals on a surface can include applying a voltage to the nanocrystals.

Abstract: The present invention relates to a method of generating a hole or recess or well in an electrically insulating or semiconducting substrate, and to a hole or recess or well in a substrate generated by this method. The invention also relates to an array of holes or recesses or wells in a substrate generated by the method. The invention also relates to a device for performing the method according to the present invention.

Abstract: A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and nanoelectronics device systems, is disclosed. A linear or nonlinear nanoparticle (nanowire) junction design that allows precise controllability over an electronic device (e.g., a varistor) performance, which is typically difficult for the traditional sintered bulk varistor, is also disclosed. A localized doping and chemical modulation, across junctions allows flexible and tunable design over the nanoscale grain boundary band engineering is further disclosed. Furthermore, a method of operating memory, using electrostatic potential modulated coding and decoding across periodic nanoparticle grain boundary linearly, is also disclosed.

Abstract: Disclosed herein are nanoscale devices comprising one or more ferroelectric nanoshells characterized as having an extreme curvature in at least one spatial dimension. Also disclosed are ferroelectric field effect transistors and metal ferroelectric metal capacitors comprising one or more ferroelectric nanoshells. Methods for controlling spontaneous ferroelectric polarization in nanoshell devices are also disclosed.

Abstract: This invention relates to a process for forming a continuous pattern on a substrate with a liquid media. Upon the deposition of the liquid media on the substrate, a portion the continuous pattern is evaporated upon contact with the substrate.

Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming a generally planar weakened zone within the first donor structure defined by implanted ions therein. At least one of a concentration of the implanted ions and an elemental composition of the implanted ions may be formed to vary laterally across the generally planar weakened zone. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.

Abstract: A plasma etching method deposits a silicon-containing deposit by a plasma processing using a Si-containing gas on an object to be processed that includes a film to be processed, an organic film formed in a plurality of narrow linear portions on the film to be processed, and a rigid film that covers both the film to be processed which is exposed between the linear portions and the linear portions. In the plasma etching method, each of the plurality of narrow linear portions of the organic film and the film to be processed between the linear portions are exposed by etching the silicon-containing deposit by plasma of CF-based gas and CHF-based gas after the silicon-containing deposit is deposited.

Abstract: A semiconductor memory card includes a lead frame having external connection terminals, a controller chip mounted on the lead frame and a memory chip mounted on the lead frame. The lead frame, the controller chip, and the memory chip are sealed with a sealing resin layer that has a surface at which the external connection terminals are exposed and a recess surrounding the external connection terminals.

Abstract: Embodiments of the invention relate generally to semiconductor wafer technology and, more particularly, to the use of conformal grounding for active charge screening on wafers during wafer processing and metrology. A first aspect of the invention provides a method of reducing an accumulated surface charge on a semiconductor wafer, the method comprising: grounding a layer of conductive material adjacent a substrate of the wafer; and allowing a mirrored charge substantially equal in magnitude and opposite in sign to the accumulated surface charge to be induced along the conductive material.

Abstract: A method for removing a metallic nanotube, which is formed on a substrate in a first direction, includes forming a plurality of conductors in a second direction crossing the first direction, electrically contacting the plurality of conductors with metallic nanotube, respectively, forming at least two voltage-applying electrodes on the conductors, each of which electrically contacting at least one of the conductors, and applying voltages to at least some of the conductors through the voltage-applying electrodes, respectively. Among the conductors to which the voltages are respectively applied, every two adjacent conductors have an electrical potential difference created therebetween, so as to burn out the metallic nanotube.

Abstract: According to one example embodiment, a structure includes at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, where the buried oxide layer overlies a bulk substrate. The structure further includes an electrically charged field control ring situated over the buried oxide layer and surrounding the at least one SOI transistor. A width of the electrically charged field control ring is greater than a thickness of the buried oxide layer. The electrically charged field control ring reduces a conductivity of a surface portion of the bulk substrate underlying the field control ring, thereby reducing RF coupling of the at least one SOI transistor through the bulk substrate. The structure further includes an isolation region situated between the electrically charged field control ring and the at least one SOI transistor. A method to achieve and implement the disclosed structure is also provided.

Abstract: A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape.

Abstract: Native oxides and residue are removed from surfaces of a substrate by performing a hydrogen remote plasma process on the substrate. In one embodiment, the method for removing native oxides from a substrate includes transferring a substrate containing native oxide disposed on a material layer into a processing chamber, wherein the material layer includes a Ge containing layer or a III-V compound containing layer, supplying a gas mixture including a hydrogen containing gas from a remote plasma source into the processing chamber, and activating the native oxide by the hydrogen containing gas to remove the oxide layer from the substrate.

Abstract: A method for manufacturing a through substrate via (TSV) structure, a TSV structure, and a control method of a TSV capacitance are provided. The method for manufacturing the TSV structure includes: providing a substrate having a first surface and a second surface; forming a trench in the first surface of the substrate; filling a low resistance material into the trench; forming an insulating layer on the first surface of the substrate; forming at least one opening in the first surface of the substrate, wherein the opening is located differently the trench; forming an oxide liner layer, a barrier layer and a conductive seed layer on a sidewall and a bottom of the opening and on the insulating layer of the first surface; and filling a conductive material into the opening, wherein the opening is used to form at least one via.

Abstract: A film deposition apparatus configured to perform a film deposition process on a substrate in a vacuum chamber includes a turntable configured to rotate a substrate loading area to receive the substrate, a film deposition area including at least one process gas supplying part configured to supply a process gas onto the substrate loading area and configured to form a thin film by depositing at least one of an atomic layer and a molecular layer along with a rotation of the turntable, a plasma treatment part provided away from the film deposition area in a rotational direction of the turntable and configured to treat the at least one of the atomic layer and the molecular layer for modification by plasma, and a bias electrode part provided under the turntable without contacting the turntable and configured to generate bias potential to attract ions in the plasma toward the substrate.

Abstract: A single-crystal substrate is placed on a supporting table while maintaining crystalline orientation of the single-crystal substrate. The single-crystal substrate has contacting regions on a periphery of an upper surface of the single-crystal substrate. Linear contacting surfaces of contacting pins are placed in contact with the contacting regions of the single-crystal substrate placed on the supporting table. Longitudinal directions on the contacting surfaces of all the contacting pins are not parallel to intersecting lines of the upper surface of the single-crystal substrate and cleaved surfaces of the single-crystal substrate.

Abstract: An integrated circuit including a substrate of a semiconductor material and first metal portions of a first metallization level or of a first via level defining pixels of an image. The pixels are distributed in first pixels, for each of which the first metal portion is connected to the substrate, and in second pixels, for each of which the first metal portion is separated from the substrate by at least one insulating portion.

Abstract: One close loop system and method for electrophoretic deposition (EPD) of phosphor material on light emitting diodes (LEDs). The system comprises a deposition chamber sealed from ambient air. A mixture of phosphor material and solution is provided to the chamber with the mixture also being sealed from ambient air. A carrier holds a batch of LEDs in the chamber with the mixture contacting the areas of the LEDs for phosphor deposition. A voltage supply applies a voltage to the LEDs and the mixture to cause the phosphor material to deposit on the LEDs at the mixture contacting areas.

Abstract: An aspect of the present embodiment, there is provided a shield plate configured to cover a semiconductor substrate including a semiconductor device in which a first semiconductor element and a second semiconductor element are included, in implanting charged particles into the semiconductor substrate to provide a lifetime control layer in the semiconductor substrate, including, an alignment mark configured to align with respect to a semiconductor substrate, a first region configured to cover the first semiconductor element, and a second region configured to cover the second semiconductor element, a thickness of the second region being thinner than a thickness of the first region.

Abstract: A method of manufacturing a semiconductor device disclosed herein includes: mounting a substrate on an electrostatic chuck placed inside a chamber, the electrostatic chuck having a first temperature and the substrate being retained in advance in an atmosphere having a second temperature lower than the first temperature; fixing the substrate onto the electrostatic chuck by applying a voltage to the electrostatic chuck; heating the electrostatic chuck to a third temperature higher than the first temperature and the second temperature after mounting the substrate; and processing the substrate after the heating.

Abstract: In accordance with an embodiment, a nonvolatile semiconductor memory device includes a substrate including a semiconductor layer including an active region, a first insulating film on the active region, a charge storage layer on the first insulating film, an element isolation insulating film defining the active region, a second insulating film, and a control electrode on the second insulating film. The top surface of the element isolation insulating film is placed at a height between the top surface and the bottom surface of the charge storage layer, thereby forming a step constituted of the charge storage layer and the element isolation insulating film. The second insulating film covers the step and the charge storage layer. The second insulating film includes a first silicon oxide film and a first silicon nitride film on the first silicon oxide film. Nitrogen concentration in the first silicon nitride film is non-uniform.

Abstract: An electrical circuit component includes a first electrode, a plurality of second electrodes and a negative differential resistance (NDR) material. The first electrode and the plurality of second electrodes are connected to the NDR material and the NDR material is to electrically connect the first electrode to one of the plurality of second electrodes when a sufficient voltage is applied between the first electrode and the one of the plurality of second electrodes through the NDR material.

Abstract: According to one embodiment, a manufacturing method of a semiconductor device includes forming a monolayer that includes organic compounds that contain conductive type dopants on a semiconductor layer, applying a bias voltage to the semiconductor layer, and injecting plasma inactive gas ions against the monolayer, so that conductive type dopants included in the monolayer are impacted by the ions to form the dopant layer injected with the conductive type dopants in a semiconductor layer. This manufacturing method controls the density of the conductive type dopants in the dopant layer by changing a size of functional group.

Abstract: A processing method and apparatus uses at least one electric field applicator (34) biased to produce a spatial-temporal electric field to affect a processing medium (26), suspended nano-objects (28) or the substrate (30) in processing, interacting with the dipole properties of the medium (26) or particles to construct structure on the substrate (30). The apparatus may include a magnetic field, an acoustic field, an optical force, or other generation device. The processing may affect selective localized layers on the substrate (30) or may control orientation of particles in the layers, control movement of dielectrophoretic particles or media, or cause suspended particles of different properties to follow different paths in the processing medium (26). Depositing or modifying a layer on the substrate (30) may be carried out.

Abstract: Embodiments of the invention relate generally to semiconductor wafer technology and, more particularly, to the use of conformal grounding for active charge screening on wafers during wafer processing and metrology. A first aspect of the invention provides a method of reducing an accumulated surface charge on a semiconductor wafer, the method comprising: grounding a layer of conductive material adjacent a substrate of the wafer; and allowing a mirrored charge substantially equal in magnitude and opposite in sign to the accumulated surface charge to be induced along the conductive material.

Abstract: The present invention provides a method for aligning nanowires which can be used to fabricate devices comprising nanowires that has well-defined and controlled orientation independently on what substrate they are arranged on. The method comprises the steps of providing nanowires (1) and applying an electrical field (E) over the population of nanowires (1), whereby an electrical dipole moment of the nanowires makes them align along the electrical field (E). Preferably the nanowires are dispersed in a fluid during the steps of providing and aligning. When aligned, the nanowires can be fixated, preferably be deposition on a substrate (2). The electrical field can be utilised in the deposition. Pn-junctions or any net charge introduced in the nanowires (1) may assist in the aligning and deposition process. The method is suitable for continuous processing, e.g. in a roll-to-roll process, on practically any substrate materials and not limited to substrates suitable for particle assisted growth.