Abstract: The invention relates to a method and device for the irreversible reduction of the value of an integrated polycrystalline silicon resistor. The inventive method consists in temporarily subjecting the resistor to a stress current which is greater than a current (Im) for which the value of the resistor is maximum.

Abstract: The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

Abstract: During fabrication of single-walled carbon nanotube transistor devices, a porous template with numerous parallel pores is used to hold the single-walled carbon nanotubes. The porous template or porous structure may be anodized aluminum oxide or another material. A gate region may be provided one end or both ends of the porous structure. The gate electrode may be formed and extend into the porous structure.

Abstract: A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

Abstract: The object of the present invention is to provide a nano-scale molecular assembly such as a conductive nano-wire. Specifically, there is provided an electrolytic apparatus for forming a molecular assembly, including two electrodes and an electrolytic cell holding an electrolyte and the two electrodes, wherein the gap between the two electrodes is from 1 nm to 100 ?m, by allowing the electrolytic cell to hold an electrolyte containing molecules that is to constitute the molecular assembly, and applying a voltage across the two electrodes in the state wherein the electrolyte and the two electrodes are in contact.

Abstract: A system for providing electrical contacts between a die and an electrical device includes a die and a package. The package includes a first major surface, a second major surface, a first scalloped edge, a second scalloped edge and a solid end adapted for insertion into a slot. The solid end and the scalloped edges carry current greater than the current needed for an input/output signal. The socket includes a base having an opening therein adapted to receive the package. A slot is located at one end of the opening in the base. The slot is provided with a plurality of conductors for carrying currents greater than the current needed for an input/output signal. A first edge and second edge of the opening include a plurality of spaced overhangs positioned over the opening. The overhangs are sloped with respect to the major planar surface.

Abstract: The object of providing a method for manufacturing solid body electrolyte memory cells or CB memory cells, respectively, which is suited for the simplified manufacturing of highly dense arrays with crosspoint architecture is solved by the present invention in that the solid body electrolyte memory cells are manufactured by self-aligned etching of the word lines that constitute simultaneously the top electrodes of the memory cells, and of the CB memory cells themselves. An advantage of the inventive method consists in that no via lithography is required, so that the manufacturing method is easier to perform, less expensive, and yields reliable results.

Abstract: A processor for making porous silicon or processing other substrates has first and second chamber assemblies. The first and second chamber assemblies include first and second seals for sealing against a wafer, and first and second electrodes, respectively. The first and/or second seal is moveable towards and away from a wafer in the processor, to move between a wafer load/unload position, and a wafer process position. The first electrode may move along with the first seal, and the second electrode may move along with the second seal. A light source shines light onto the first side of the wafer. The processor may be pivotable from a substantially horizontal orientation, for loading and unloading a wafer, to a substantially vertical orientation, for processing a wafer.

Abstract: A method of making a packaged electrical device comprises the steps of (a) connecting one end of a wire to a first point (e.g., a first electrical node) in the package, and (b) connecting the other end of the wire to a second point (e.g., a second electrical node) in the package, characterized by (c) causing energy from an external source to heat at least one predetermined segment of the wire to a temperature that is below its melting point (MP) but not below its recrystallization temperature (RCT), and (d) cooling the heated segment to a temperature below its RCT [e.g., to room temperature (RT)], thereby to increase the stiffness modulus of the segment. In one embodiment, the external source is a laser whose optical output is absorbed by the segment. In another embodiment, the heated segment is rapidly cooled (i.e., quenched) to RT.

Abstract: The electric device (1, 100) has a body (2, 102) having a resistor (7, 107) comprising a phase change material being changeable between a first phase and a second phase. The resistor (7, 107) has a first electrical resistance when the phase change material is in the first phase and a second electrical resistance, different from the first electrical resistance, when the phase change material is in the second phase. The body (2, 102) further has a heating element (6, 106) being able to conduct a current for enabling a transition from the first phase to the second phase. The heating element (6, 106) is arranged in parallel with the resistor (7, 107).

Abstract: A method provides a simple yet reliable technique to assemble one-dimensional nanostructures selectively in a desired pattern for device applications. The method comprises forming a plurality of spaced apart conductive elements (12, 20) in a sequential pattern (26) on a substrate (17) and immersing the plurality of spaced apart conductive elements (12, 20) in a solution (23) comprising a plurality of one-dimensional nanostructures (22). A voltage is applied to one of the plurality of spaced apart conductive elements (12, 20) formed in the sequential pattern (26), thereby causing portions of the plurality of one-dimensional nanostructures (22) to migrate between adjacent conductive elements (12, 20) in sequence beginning with the one of the plurality of spaced apart conductive elements (12, 20) to which the voltage is applied.

Abstract: A method of manufacturing a semiconductor laser that has a ridge portion formed with a compound semiconductor layer containing Ga includes applying an electric current to the semiconductor laser until the characteristics of the semiconductor laser that have deteriorated due to the application of the electric current recover from the deterioration.

Abstract: A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells, arranged in rows and columns; and forming a plurality of resistive bit lines for connecting PCM cells arranged on a same column, each resistive bit lines comprising a respective phase change material portion, covered by a respective barrier portion. After forming the resistive bit lines, electrical connection structures for the resistive bit lines are formed directly in contact with the barrier portions of the resistive bit lines.

Abstract: Certain modifications and additions to the prior art short passivation technique have lead to improvements in the low light voltage of solar cells which are made using the improved passivation technique. Examples of the modifications include: 1) reducing the voltage bias on the cell while increasing the time of application of the voltage; 2) reversing the polarity of the voltage bias on the devices; 3) alternating pulsing between forward and reverse polarity bias; or 4) applying light energy simultaneously with an electrical bias voltage.

Abstract: The subject invention pertains to a method of spark processing silicon and resulting materials. The subject invention also relates to electroluminescent devices incorporating the materials produced by the subject method. The subject method for spark-processing can enhance the EL output, as compared with conventional spark-processed (sp) silicon. The enhancement of EL output can be due, at least in part, to increasing the light emitting area. The subject method can smooth the sp surface, so as to allow more complete coverage of the sp area with a continuous, semitransparent, conducting film. The smoothening of the sp surface can be accomplished by, for example, introducing into the spark plasma a volatile liquid, such as methanol, ethanol, acetone, in which particles can be suspended and/or in which a heavy ion salt is dissolved. The particles preferably float in the volatile liquid, rather than settle quickly. In a specific embodiment, silicon particles in the range of about 0.

Abstract: A semiconductor wafer provided with columnar electrodes which have plated nickel, palladium, and gold films successively formed at the top thereof, or have a plated solder film at their top. The semiconductor wafer can be preferably used for producing a chip-sized semiconductor device provided with columnar electrodes to which an external connection terminal, such as a solder ball, is to be bonded. Methods of producing the semiconductor wafer and device by use of plating are also disclosed.

Abstract: A light receiving or light emitting modular sheet having a plurality of spherical elements arranged in matrix. It is constituted only of acceptable spherical elements and photoelectric conversion efficiency thereof is enhanced. The light receiving modular sheet (1) comprises a plurality of spherical solar cell elements (2) arranged in matrix, a meshed member (3), and a sheet member (4). Each solar cell element (2) comprises a spherical pn junction (13), and positive and negative electrodes (14, 15) formed oppositely while sandwiching the center of the solar cell element (2) and being connected with respective electrodes of the pn junction (13).

Abstract: A polysilicon silicide stringer fuse is constructed having a narrow width by using an overlay tolerance of the photo stepper tool instead of the minimum critical dimension tolerance of the stepper tool. In an example embodiment, a fuse (200) for integration within a semiconductor comprises depositing an insulating layer (205) adjacent to the semiconductor substrate (203). A silicon layer (201) is formed with a first silicon material having a first resistance deposited adjacent the insulating layer (205). The silicon layer has a first width. A metal silicide stringer (202), having a second resistance different from the first resistance is deposited over a portion of the first silicon material (201) and having a second width that is less than the first width within at least a portion thereof. The metal silicide conducts current therethrough with approximately the second resistance and agglomerates in response to a programming current other than the conduct current therethrough with a same second resistance.

Abstract: Three-dimensional structures are electrochemically fabricated by depositing a first material onto previously deposited material through voids in a patterned mask where the patterned mask is at least temporarily adhered to a substrate or previously formed layer of material and is formed and patterned onto the substrate via a transfer tool patterned to enable transfer of a desired pattern of precursor masking material. In some embodiments the precursor material is transformed into masking material after transfer to the substrate while in other embodiments the precursor is transformed during or before transfer. In some embodiments layers are formed one on top of another to build up multi-layer structures. In some embodiments the mask material acts as a build material while in other embodiments the mask material is replaced each layer by a different material which may, for example, be conductive or dielectric.

Abstract: A method of simultaneously bonding components, comprising the following steps. At least first, second and third components are provided and comprise: at least one glass component; and at least one conductive or semiconductive material component. The order of stacking of the components is determined to establish interfaces between the adjacent components. A hydrogen-free amorphous film is applied to one of the component surfaces at each interface comprising an adjacent: glass component; and conductive or semiconductive component. A sol gel with or without alkaline ions film is applied to one of the component surfaces at each interface comprising an adjacent: conductive or semiconductive component; and conductive or semiconductive component. The components are simultaneously anodically bonded in the determined order of stacking.

Abstract: A process for producing a semiconductor substrate is provided which comprises steps of forming a porous layer on a first substrate, forming a nonporous monocrystalline semiconductor layer on the porous layer of the first substrate, bonding the nonporous monocrystalline layer onto a second substrate, separating the bonded substrates at the porous layer, removing the porous layer on the second substrate, and removing the porous layer constituting the first substrate.

Abstract: A method for stably activating pn-successive layers in a semiconductor element in a short time is disclosed. Pulsed beams, each of which has a pulse shape that is approximately rectangular, are projected from respective laser irradiation devices and successively combined into a pulsed beam equivalent to one pulse, with which the doped layer region is irradiated. By successively projecting the pulsed beams onto the doped layer region in this way, an effect is obtained which is the same as that of irradiating the doped layer region with a single pulsed beam having a long full-width at half maximum. A high activation ratio from a shallow region to a deep region of the doped layer region is enabled. This can stably activate the semiconductor element having the pn-successive layers as the doped layer region in a short time, making possible the manufacture of semiconductor elements having superior device characteristics.

Abstract: The electric device (100) has a body (102) having a resistor (107) comprising a phase change material being changeable between a first phase and a second phase. The resistor (107) has a first electrical resistance when the phase change material is in the first phase, and a second electrical resistance, different from the first electrical resistance, when the phase change material is in the second phase. The phase change material constitutes a conductive path between a first contact area and a second contact area. A cross-section of the conductive path is smaller than the first contact area and the second contact area. The body (102) may further have a heating element 106 being able to conduct a current for enabling a transition from the first phase to the second phase. The heating element (106) is preferably arranged in parallel with the resistor (107).

Abstract: A method for crystallizing an amorphous film by using an electric field and an ultraviolet (UV) ray, and method for fabricating an LCD by using the same. The method for crystallizing an amorphous film includes forming an amorphous film having a catalytic metal deposited thereon on a substrate, irradiating a UV ray on the amorphous film, and applying an electric field to the amorphous film.

Abstract: A non-volatile memory array includes memory cells connected in a common source arrangement and formed in columns of isolated well regions so that Fowler-Nordheim tunneling is used for both write and erase operations of the memory cells. The memory arrays can be formed as NOR arrays or NAND arrays. In one embodiment, the memory array of the present invention is formed as a byte alterable EEPROM with parallel access. In another embodiment, an insulated gate bipolar transistor (IGBT) is coupled to the memory cells to increase the cell read current of the memory array. When the memory array incorporates IGBTs on the bitlines, the cell read current becomes independent of the wordline voltages. Thus, the memory array of the present invention can be operated at low voltages. The use of IGBTs in the memory array of the present invention enables formation of embedded non-volatile memories in low-voltage digital integrated circuits.

Abstract: According to an embodiment of the present invention, a method of producing an electronic circuit comprises printing first metal-containing resin particles which consist of at least a thermosetting resin and fine metal particles and second metal-containing resin particles which consist of at least a thermoplastic resin and fine metal particles by electrophotography to form a first base pattern which consists of the first metal-containing resin particles and a second base pattern which consists of the second metal-containing resin particles on a substrate; forming a first metal conductor layer on the first and second base patterns; forming a second metal conductor layer on the first metal conductor layer by electrolytic plating by supplying electric current to the first metal conductor layer; and removing the second base pattern and the first and second metal conductor layers which are formed on the second base pattern.

Abstract: A device and a method for generating an electric-field-induced spin current are disclosed. A highly spin-polarized electric current is generated using a semiconductor structure and an applied electric field across the semiconductor structure. The semiconductor structure can be a hole-doped semiconductor having finite or zero bandgap or an undoped semiconductor of zero bandgap. In one embodiment, a device for injecting spin-polarized current into a current output terminal includes a semiconductor structure including first and second electrodes, along a first axis, receiving an applied electric field and a third electrode, along a direction perpendicular to the first axis, providing the spin-polarized current. The semiconductor structure includes a semiconductor material whose spin orbit coupling energy is greater than room temperature (300 Kelvin) times the Boltzmann constant. In one embodiment, the semiconductor structure is a hole-doped semiconductor structure, such as a p-type GaAs semiconductor layer.

Abstract: A wafer-scale fabrication approach for manufacturing single-walled carbon nanotube (SWNT) tips is implemented. Catalyst material is selectively placed (e.g., patterned) onto a plurality of prefabricated elevated structures (e.g., silicon tips) on a wafer. SWNTs are grown protruding from the catalyst on the elevated structures. The resulting SWNT protruding from a tip can be implemented in a variety of applications, such as in atomic force microscopy (AFM). With this approach, nanotube tips can be implemented for a variety of applications, including advanced nanoscale imaging, imaging of solid-state and soft biological systems and for scanning probe lithography.

Abstract: A phase-changeable memory device comprises a substrate and an access transistor formed in and/or on the substrate. Laterally spaced apart first and second conductive patterns are disposed on the substrate and have opposing sidewalls. A conductor electrically connects the first conductive region to a source/drain region of the access transistor. A phase-changeable material region is disposed between the first and second conductive patterns and contacts the opposing sidewalls of the first and second conductive patterns. Contact areas between the conductive patterns and the phase-changeable material region are preferably substantially smaller than contact areas at which the conductive patterns contact conductors (e.g., vias) connected thereto, such that high current densities may be developed in the phase-changeable material. Methods of fabricating such devices are also discussed.

Abstract: Metal-insulator-metal capacitor structures are formed in semiconductor substrates using an anodization procedure on deposited underlying metalization followed by deposition of the second metal and planarization by chemical-mechanical polishing or other procedures. The process is additive in character, as opposed to traditional subtractive etch processes for forming capacitor structures. In addition, the process can be used in damascene applications, and can be used to form a wide variety of capacitive structures while reducing the number of mask layers required for formation.

Abstract: A nonvolatile memory cell occupying a minimum chip area is provided with a cell structure that includes two or more base materials being programmable by a heat induced chemical reaction to form a layer or layers of alloy. The formation of alloy results in a change in resistance of the cell structure so that one or more programmed states are determined. A semiconductor memory constructed by a large number of the nonvolatile memory cells can be obtained in a compact manner with simple and as few as possible steps. This process vertically stacked layers, and this semiconductor memory is thus easily to be combined with other integrated circuits on a single chip.

Abstract: Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

Abstract: The present invention provides a novel method for increasing the amount of deuterium incorporated into trap sites of a transistor device during a deuterium passivation anneal by electrically pre-stressing the fabricated device prior to a deuterium anneal. The method of the present invention equally applies to SOI and CMOS technology. As a result, the incorporation of more deuterium during a deuterium anneal in the process flow reduces the number of undesirable trap sites.

Abstract: The present invention relates to a method of bonding a first member (110, 210, 130, 230, 410, 430, 510, 530, 610) to a second silicon member (120, 220, 420a, 420b, 600) through anodic bonding. The method comprises the steps of selectively depositing on said first member bondable sections (170a, 170b, 270, 470a, 470b, 470c, 570, 620) before bringing said first and second members together for anodic bonding.

Abstract: Defective contact plug fills can be detected by applying an etching solution, which in some embodiments preferentially etches in the <111> direction. The etching solution is some embodiments may also produce a characteristic type of undercutting underneath the contact plug fill. Contact plug fills with defects in them have undercutting underneath as a result of the etchant exposure, while defective contact plug fills have no such undercutting. The contact plug fills that are now undercut by etching exposure are unable to dissipate surface charge or surface applied potential and can be detected using voltage contrast methods or conventional electrical testing techniques, for example.

Abstract: A method of field-assisted fusion bonding produces multiple-layer devices. Contacts (301, 303, 305, 307, 309) are placed at various points along different surfaces of a combination of two or more wafers (201, 203, 205, 501, 503, 505, 801, 803). An electric field is applied to the contacts (301, 303, 305, 307, 309), thereby creating an electrostatic attractive force between the wafers (201, 203, 205, 501, 503, 505, 801, 803). The temperature of the wafer combination is elevated to a fusion bonding temperature while the electric field is applied.

Abstract: The present invention provides a process and apparatus for selectively depositing materials on a semiconductor device, such as depositing phosphors or other optical materials on a light emitting diode (LED), using an electrophoretic deposition process. The semiconductor device comprises a p-side and an n-side. A first biasing voltage is applied between an anode and the p-side of the semiconductor device. A second biasing voltage is applied between the p-side and the n-side of the semiconductor device. The relative biasing of the p-side and the n-side determines where coating is deposited on the semiconductor device. An optional pre-coating process is used to deposit a high resistivity dielectric material, such as silica, on the semiconductor device. The pre-coating can even the electric field on the surface of the semiconductor device, where local features such as metal connections or passivation layers disturb the electric field during phosphor deposition without pre-coating.

Abstract: A unique electrochemical process fills oxygen vacancies in dielectrics while reducing oxidation of nearby electrodes and conductors. Preferably, an electromagnetic field or bias is applied to a dielectric. The bias causes oxygen vacancies in the dielectric to migrate to the surface of the dielectric. As the oxygen vacancies migrate toward the surface, oxygen ions fill the oxygen vacancies. In one embodiment, a unique plasma treatment provides the oxygen ions that react with the oxygen vacancies. In another embodiment, a unique electrolysis treatment provides the oxygen ions that react with the oxygen vacancies.

Abstract: A capacitor formed by a person using only two deposition steps and a dielectric formed by oxidizing a metal layer in an electrolytic solution. The capacitor has first and second conductive plates and a dielectric is formed from the first conductive plate.

Abstract: Disclosed is a method of manufacturing flash memory devices.

Abstract: Disclosed is a method for the electrochemical oxidation of a semiconductor layer. In an electrochemical oxidation treatment for the production process of an electron source 10 (field-emission type electron source) as one of electronic devices, a control section 37 determines a voltage increment due to the resistance of an electrolytic solution B in advance, based on a detected voltage from a resistance detect section 35. Then, the control section 37 controls a current source to supply a constant current so as to initiate an oxidation treatment for a semiconductor layer formed on an object 30. The control section 37 corrects a detected voltage from a voltage detect section 36 by subtracting the voltage increment therefrom. When the corrected voltage reaches a given upper voltage value, the control section 37 is operable to discontinue the output of the current source 32 and terminate the oxidation treatment.

Abstract: The present invention relates to an apparatus and method for electropolishing a metal wire layer on a semiconductor device. To electropolish the metal wiring layer, a wafer is dipped into an electrolyte solution, and positive and negative voltages are applied to the wafer and electrodes, respectively. The electrodes include a main electrode and a plurality of auxiliary electrodes disposed above the main electrode. In a preferred embodiment, the plurality of auxiliary electrodes are mesh-type electrodes and are annular in shape and concentrically disposed, and thus the electrolyte solution can readily flow between them. Further, the metal wiring layer is preferably sequentially electropolished outwardly from the center of the wafer by sequentially applying negative voltages to the plurality of annular auxiliary electrodes. In this manner, a uniform electropolishing process is performed.

Abstract: The present invention includes a method for creating a reconfigurable nanometer-scale electronic network. One embodiment of the invention is made up of the following steps. The first step entails depositing nanometer-scale electrically conducting islands on an insulating substrate. The next step entails engineering electrically conducting molecules to preferentially attach to the nanometer-scale electrically conducting islands, forming a semi-regular array of current-conducting elements. The next step entails selecting individual nodes for bond breaking by applying electrical currents through two orthogonal molecular filaments, this current heating both the molecules and islands raising the temperature of the current-conducting elements at individual nodes and breaking bonds in accordance with a pre-selected network design. The next step entails repeating the step of selecting individual nodes for bond breaking to produce thereby the nanometer-scale electronic network.

Abstract: A method for crystallizing an amorphous film for enhancing a crystallinity and minimizing an amount of remaining metal in a polycrystalline silicon thin film, and a method for fabricating a liquid crystal display device (LCD) by using the same. The method for crystallizing an amorphous film including forming an amorphous film on a substrate; forming a thin first metal layer; forming a second metal layer on the amorphous film at predetermined parts; and heat treating the amorphous film, for crystallizing the amorphous film.

Abstract: In a process for producing a thin-film device, a conducting layer composed of an anodically oxidizable metal is formed on a substrate and is etched to form gate bus lines and gate electrode having upper surfaces parallel to the substrate and inclined side surfaces. The gate bus lines and the gate electrodes are anodically oxidized, so that they include inner conducting portions and outer insulating oxide films covering the inner conducting portions. The outer insulating films prevent the bus lines from short circuiting, and the inclined side surfaces of the bus lines makes it possible to fabricate a dense wiring arrangement.

Abstract: A technique for forming a film of crystalline material, preferably silicon. The technique creates a sandwich structure with a weakened region at a selected depth underneath the surface. The weakened region is a layer of porous silicon with high porosity. The high porosity enclosed layer is formed by (1) forming a porous silicon layer with low porosity on surface of the substrate, (2) epitaxial growth of a non-porous layer over the low-porous layer (3) increasing of porosity of the low-porous layer making the said layer hi-porous, (4) cleaving the semiconductor substrate at said high porous layer. The porosity of the buried low-porous layer is increased by hydrogenation techniques, for example, by processing in hydrogen plasma. The process is preferentially used to produce silicon-on-insulator wafers.

Abstract: Disclosed is a method for the electrochemical oxidation of a semiconductor layer. In an electrochemical oxidation treatment for the production process of an electron source 10 (field-emission type electron source) as one of electronic devices, a control section 37 determines a voltage increment due to the resistance of an electrolytic solution B in advance, based on a detected voltage from a resistance detect section 35. Then, the control section 37 controls a current source to supply a constant current so as to initiate an oxidation treatment for a semiconductor layer formed on an object 30. The control section 37 corrects a detected voltage from a voltage detect section 36 by subtracting the voltage increment therefrom. When the corrected voltage reaches a given upper voltage value, the control section 37 is operable to discontinue the output of the current source 32 and terminate the oxidation treatment.

Abstract: A method for manufacturing a semiconductor device is capable of controlling amounts of protrusion of penetration electrodes (5) from a rear surface of a semiconductor substrate (4) in a easy and accurate manner. Recesses (7) are formed in a substrate proper (6) that has a semiconductor circuit (2) formed on one surface thereof, and an insulation film (8) is formed on an inner wall surface of each of the recesses (7). A conductive material is filled into the recesses (7) through the insulation films (8) to form embedded electrodes (15) that constitute the penetration electrodes (5). A rear side of the substrate proper (6) is re moved until one end face of each of the embedded electrodes (15) is exposed, thereby to form the penetration electrodes (5). The rear surface of the substrate proper (6) is anodized to form an anodic oxide film (9), which is then removed by etching to form the semiconductor substrate (4).

Abstract: A method includes (a) putting a multielectrodic chip lithographed in a wafer that contains between 2 and 2000 individually polarisable electrodes, in contact with a solution or suspension that includes modified colloidal particles with a (bio)chemical recognition element; (b) applying to an electrode of the multielectrodic chip, a potential between −1 and +2V vs. Ag/AgCl saturated, for a period of time between 1 and 300 seconds; (c) washing the chip after this stage (b); and (d) repeat the steps (b) and (c) as many times as needed to deposit a (bio)chemical recognition element, same or different to the one or ones previously deposited, on each one of the electrodes of that chip. The method is applicable for the fabrication of multisensors, particularly in chips and arrays for analytical and diagnostic applications.

Abstract: A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the invention includes contacting a surface of a microelectronic substrate with an electrolytic liquid, the microelectronic substrate having first and second different conductive materials. The method can further include controlling a difference between a first open circuit potential of the first conducive material and a second open circuit potential of the second conductive material by selecting a pH of the electrolytic liquid. The method can further include simultaneously removing at least portions of the first and second conductive materials by passing a varying electrical signal through the electrolytic liquid and the conductive materials. Accordingly, the effects of galvanic interactions between the two conductive materials can be reduced and/or eliminated.