Abstract: Disclosed is a resin composition for encapsulating a semiconductor containing a curing agent, an epoxy resin (B) and an inorganic filler (C), wherein the curing agent is a phenol resin (A) having a predetermined structure. Also disclosed is a semiconductor device obtained by encapsulating a semiconductor element with a cured product of the resin composition for encapsulating a semiconductor.

Abstract: Programmable field effect transistors (FETs) are provided using high-k dielectric metal gate Vt shift effect and methods of manufacturing the same. The method of controlling Vt shift in a high-k dielectric metal gate structure includes applying a current to a gate contact of the high-k dielectric metal gate structure to raise a temperature of a metal forming a gate stack. The temperature is raised beyond a Vt shift temperature threshold for providing an on-state.

Abstract: A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and nanoelectronics device systems, is disclosed. A linear or nonlinear nanoparticle (nanowire) junction design that allows precise controllability over an electronic device (e.g., a varistor) performance, which is typically difficult for the traditional sintered bulk varistor, is also disclosed. A localized doping and chemical modulation, across junctions allows flexible and tunable design over the nanoscale grain boundary band engineering is further disclosed. Furthermore, a method of operating memory, using electrostatic potential modulated coding and decoding across periodic nanoparticle grain boundary linearly, is also disclosed.

Abstract: The disclosure provides an interposer with conductive paths, a three-dimensional integrated circuit (3D IC), a method of reducing capacitance associated with conductive paths in an interposer and a method of manufacturing an interposer. In one embodiment the interposer includes: (1) a semiconductor substrate that is doped with a dopant, (2) conductive paths located within said semiconductor substrate and configured to provide electrical routes therethrough and (3) an ohmic contact region located within said semiconductor substrate and configured to receive a back bias voltage.

Abstract: Improved highly reliable power RFP structures and fabrication and operation processes. The structure includes plurality of localized dopant concentrated zones beneath the trenches of RFPs, either floating or extending and merging with the body layer of the MOSFET or connecting with the source layer through a region of vertical doped region. This local dopant zone decreases the minority carrier injection efficiency of the body diode of the device and alters the electric field distribution during the body diode reverse recovery.

Abstract: Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material.

Abstract: A pixel includes an organic light emitting diode, a first transistor having a source coupled to a first power source, a control gate coupled to a first node, and a drain coupled to a second node, wherein the first transistor includes a floating gate and an insulating layer between the floating gate and the control gate, a second transistor having a source coupled to a data line, a drain coupled to the first node, and a gate coupled to a scan line, a third transistor having a source coupled to the second node, a drain coupled to the organic light emitting diode, and a gate coupled to one of a light emitting control line and the scan line, and a capacitor coupled between the first power source and the first node.

Abstract: A method for removing a metallic nanotube which is formed on a substrate in a first direction is disclosed. The method may comprise: forming a plurality of conductors in a second direction crossing the first direction, the conductors electrically contacting the metallic nanotube, respectively; forming at least two voltage-applying electrodes on the conductors, each of the voltage-applying electrodes electrically contacting at least one of the conductors; and applying voltages to at least some of the conductors through the voltage-applying electrodes, respectively, wherein among conductors to which the voltages are respectively applied, every two adjacent conductors have an electrical potential difference created therebetween, so as to burn out the metallic nanotube.

Abstract: System and methods offset mechanism elements during fabrication of Micro-Electro-Mechanical Systems (MEMS) devices. An exemplary embodiment applies a voltage across an offset mechanism element and a bonding layer of a MEMS device to generate an electrostatic charge between the offset mechanism element and the bonding layer, wherein the electrostatic charge draws the offset mechanism element to the bonding layer. The offset mechanism element and the bonding layer are then bonded.

Abstract: Devices that include one or more functional semiconductor elements that are immersed in static electric fields (E-fields). In one embodiment, one or more electrets are placed proximate the one or more organic, inorganic, or hybrid semiconductor elements so that the static charge(s) of the electret(s) participate in creating the static E-field(s) that influences the semiconductor element(s). An externally applied electric field can be used, for example, to enhance charge-carrier mobility in the semiconductor element and/or to vary the width of the depletion region in the semiconductor material.

Abstract: Actuating a semiconductor device includes providing a transistor that includes a substrate and a first electrically conductive material layer, including a reentrant profile, positioned on the substrate. An electrically insulating material layer is conformally positioned over the first electrically conductive material layer and at least a portion of the substrate. A semiconductor material layer conforms to and is in contact with the electrically insulating material layer. A second electrically conductive material layer and third electrically conductive material layer are nonconformally positioned over and in contact with a first portion of the semiconductor material layer and a second portion of the semiconductor material layer, respectively.

Abstract: A semiconductor device and a method for programming the same are provided. The semiconductor device comprises: a semiconductor substrate with an interconnect formed therein; a Through-Silicon Via (TSV) penetrating through the semiconductor substrate; and a programmable device which can be switched between on and off states, the TSV being connected to the interconnect by the programmable device. The present invention is beneficial in improving flexibility of TSV application.

Abstract: The production method for the oxidized carbon thin film of the present disclosure includes: a first step of preparing a carbon thin film and iron oxide that is in contact with the carbon thin film and contains Fe2O3; and a second step of forming an oxidized carbon thin film having an oxidized portion composed of oxidized carbon by applying a voltage or current between the carbon thin film and the iron oxide with the carbon thin film side being positive and thereby oxidizing a contact portion of the carbon thin film with the iron oxide to change it into the oxidized portion. This production method allows a pattern of nanometer order to be formed on a carbon thin film represented by graphene. The method causes less damage to the formed pattern and has high affinity with a semiconductor process, thereby enabling a wide range of applications as a process technique for producing an electronic device.

Abstract: A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and devices formed using such a method.

Abstract: A wafer is mounted on the top surface of the stage having an electrostatic chuck function, and the wafer at 50° C. or more is cooled to a temperature lower than 50° C. In this step, the voltage to be applied to the internal electrode provided in the stage is raised stepwise to gradually increase the contact area between the back surface of the wafer and the top surface of the stage. Finally, a chuck voltage is applied to the internal electrode, so that the entire back surface of the wafer is uniformly attracted to the top surface of the stage. This reduces damage occurring in the top surface of the stage due to rubbing between the back surface of the wafer and the top surface of the stage.

Abstract: An electrochemical process comprising: providing a 125 mm or larger semiconductor wafer in electrical contact with a conducting surface, wherein at least a portion of the semiconductor wafer is in contact with an electrolytic solution, said semiconductor wafer functioning as a first electrode; providing a second electrode in the electrolytic solution, the first and second electrode connected to opposite ends of an electric power source; and irradiating a surface of the semiconductor wafer with a light source as an electric current is applied across the first and the second electrodes. The invention is also directed to an apparatus including a light source and electrochemical components to conduct the electrochemical process.

Abstract: A semiconductor structure and a method for operating the same are provided. The semiconductor structure includes a substrate, a first doped region, a second doped region, a third doped region, a first trench structure and a second gate structure. The first doped region is in the substrate. The first doped region has a first conductivity type. The second doped region is in the first doped region. The second doped region has a second conductivity type opposite to the first conductivity type. The third doped region having the first conductivity type is in the second doped region. The first trench structure has a first gate structure. The first gate structure and the second gate structure are respectively on different sides of the second doped region.

Abstract: A method for manufacturing an array-type nanotube layer for a thin-film solar cell comprises the steps of: preparing an isotropic Si-substrate; sputtering a metal Ti layer onto the isotropic Si-substrate; heat-treating the Ti-coated Si-substrate in a vacuum heat-treatment environment; annealing the Ti-coated Si-substrate in an annealing heat-treatment environment to produce an intermediate-phase metal Ti layer; anodizing the intermediate-phase metal Ti layer so as to transform the intermediate-phase metal Ti layer into an array-type nanotube layer for the solar cell; and finally applying a reverse voltage to separate the array-type nanotube layer from the isotropic Si-substrate.

Abstract: A semiconducting device includes a piezoelectric structure that has a first end and an opposite second end. A first conductor is in electrical communication with the first end and a second conductor is in electrical communication with the second end so as to form an interface therebetween. A force applying structure is configured to maintain an amount of strain in the piezoelectric member sufficient to generate a desired electrical characteristic in the semiconducting device.

Abstract: Various methods and apparatuses involving salt-based compounds and related doping are provided. In accordance with one or more embodiments, a salt-based material is introduced to a semiconductor material, is heated to generate a neutral compound that dopes the semiconductor material. Other embodiments are directed to semiconductor materials with such a neutral compound as an impurity that affects electrical characteristics therein.

Abstract: A method for controlling the electrical conduction between two electrically conductive portions may include placing of an at least partially ionic crystal between the two electrically conductive portions. The crystal may include at least one surface region coupled to the two electrically conductive portions. The surface region is insulating under the application of an electrical field to the surface region, and electrically conductive in the absence of the electrical field. An application or not of an electrical field to the at least one surface region reduces or establishes the electrical conduction.

Abstract: A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.

Abstract: A method for making a nanowire element includes: providing an imprint mold including a first substrate and a conductive pattern-transferring layer, the pattern-transferring layer includes first conductive strips; electrifying the pattern-transferring layer with an alternating current; applying a nanowire-containing suspension on the pattern-transferring layer; reorienting the nanowires in the nanowire-containing suspension using a dielectrophoresis method, thereby the nanowires connected between two adjacent first conductive strips; providing a pattern-receiving body, the pattern-receiving body including a second substrate and a pattern-receiving layer; pressing the imprint mold onto the pattern-receiving body with the conductive pattern-transferring layer facing the pattern-receiving layer, thereby defining a patterned recess in the pattern-receiving layer and transferring the nanowires to the second substrate; forming a first conductive layer on the second substrate to obtain a conductive pattern layer, the

Abstract: The present invention is to provide a method for manufacturing a silicon nanowire array comprising (a) preparing a porous metal film; (b) placing the porous metal film in contact with a silicon substrate; and (c) etching the silicon substrate with a silicon etching solution. The present invention allows manufacturing vertically aligned large-area silicon nanowires by using the porous metal film as a catalyst and manufacturing nanowires having a porous structure, a porous nodular structure, an inclined structure and a zig-zag structure, which are distinguishable from nanowires of the prior art in their shape and crystallographic orientation, by adjusting etching conditions such as the composition of the silicon etching solution and the etching temperature in the step in which the silicon substrate is subjected to wet etching.

Abstract: Methods and systems for electrochemically depositing doped metal oxide and metal chalcogenide films are disclosed. An example method includes dissolving a metal precursor into a solution, adding a halogen precursor to the solution, and applying a potential between a working electrode and a counter electrode of an electrochemical cell to deposit halogen doped metal oxide or metal chalcogenide onto a substrate. Another example method includes dissolving a zinc precursor into a solution, adding an yttrium precursor to the solution, and applying a potential between a working electrode and a counter electrode of an electrochemical cell to deposit yttrium doped zinc oxide onto a substrate. Other embodiments are described and claimed.

Abstract: A non-volatile bistable nano-electromechanical switch is provided for use in memory devices and microprocessors. The switch employs carbon nanotubes as the actuation element. A method has been developed for fabricating nanoswitches having one single-walled carbon nanotube as the actuator. The actuation of two different states can be achieved using the same low voltage for each state.

Abstract: A method of forming a microball grid array includes adhering a microball precursor material to a transfer medium under conditions to reflect a selective charge pattern. The method includes transferring the microball precursor material from the transfer medium across a gap and to an integrated circuit substrate under conditions to reflect the selective charge pattern. The method includes achieving the microball grid array without the aid of a mask.

Abstract: An electrical circuit component includes a first electrode, a plurality of second electrodes and a negative differential resistance (NDR) material. The first electrode and the plurality of second electrodes are connected to the NDR material and the NDR material is to electrically connect the first electrode to one of the plurality of second electrodes when a sufficient voltage is applied between the first electrode and the one of the plurality of second electrodes through the NDR material.

Abstract: In a manufacturing method of a semiconductor structure, a substrate having a front surface and a back surface is provided. The front surface has a device layer thereon and conductive plugs electrically connected to the device layer. A thinning process is performed on the back surface of the substrate, such that the back surface of the substrate and surfaces of the conductive plugs have a distance therebetween. Holes are formed in the substrate from the back surface to the conductive plugs, so as to form a porous film. An oxidization process is performed, such that the porous film correspondingly is reacted to form an oxide material layer. A polishing process is performed on the oxide material layer to expose the surfaces of the conductive plugs.

Abstract: This patent disclosure presents circuits, system, and method to produce an ideal memory cell and a method to produce a perfect PN junction without undesirable junction voltage and leakage current. These new inventions finally perfect the art to produce PN junction diode sixty years after PN junction diode was invented and the technology to produce an indestructible nonvolatile memory cell that is fast and small.

Abstract: An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.

Abstract: A non-volatile bistable nano-electromechanical switch is provided for use in memory devices and microprocessors. The switch employs carbon nanotubes as the actuation element. A method has been developed for fabricating nanoswitches having one single-walled carbon nanotube as the actuator. The actuation of two different states can be achieved using the same low voltage for each state.

Abstract: Programmable field effect transistors (FETs) are provided using high-k dielectric metal gate Vt shift effect and methods of manufacturing the same. The method of controlling Vt shift in a high-k dielectric metal gate structure includes applying a current to a gate contact of the high-k dielectric metal gate structure to raise a temperature of a metal forming a gate stack. The temperature is raised beyond a Vt shift temperature threshold for providing an on-state.

Abstract: Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material.

Abstract: An optical device includes a substrate and a semiconductor layer located over the substrate. The optical path includes a semiconductor layer that further includes a waveguide core region. The core region includes a first semiconductor region with a morphology of a first type and a first refractive index. The first semiconductor region is located adjacent a second semiconductor region that has a morphology of a second type and a second refractive index that is different from the first refractive index.

Abstract: Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.

Abstract: The invention relates to a method for functionalizing a conductive or semiconductor material (M) by covalent grafting of receptor molecules (R) to its surface, said method comprising the following steps: (i) applying, across the terminals of a source electrode and a drain electrode located on either side of the material (M), sufficient potential difference to thermally activate the material (M) with respect to the grafting reaction of the molecules (R); and (ii) placing the material (M) thus activated in contact with a liquid or gaseous medium containing receptor molecules (R), thereby obtaining a material (M) functionalized by covalently grafted receptor molecules (R).

Abstract: An electronic device includes: multiple electronic elements each including a semiconductor film; and an element isolation region provided between adjacent ones of the multiple electronic elements, the element isolation region including a semiconductor film having a bandgap of 1.95 eV or more, an insulating film, and an element isolation electrode, the element isolation electrode being an electrode which is separated from the semiconductor film of the element isolation region by the insulating film and is applied with a voltage so as to increase a resistance of the semiconductor film of the element isolation region, to thereby electrically isolate the multiple electronic elements from one another.

Abstract: A nanostructure includes a nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there between. A nanostructure in another embodiment includes a substrate having an area with a nanofeature; and a nanowire extending from the nanofeature, the nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there between. A method for forming a nanostructure is also presented. A method for reading and writing data is also presented. A method for preparing nanoparticles is also presented.

Abstract: The present invention relates to a method of generating a hole or recess or well in an electrically insulating or semiconducting substrate, and to a hole or recess or well in a substrate generated by this method. The invention also relates to an array of holes or recesses or wells in a substrate generated by the method. The invention also relates to a device for performing the method according to the present invention.

Abstract: An apparatus for manufacturing a polycrystalline silicon thin film, including a crystallization container filled with silicon oil, crystallization electrodes spaced apart from the crystallization container, and a conductive plate positioned between the crystallization electrodes and connected with the crystallization electrodes. Because an insulating layer between the amorphous silicon thin film and the conductive plate is formed by using silicon oil filled within the crystallization container, Joule-heating induced crystallization (JIC) can be performed through a simpler manufacturing process.

Abstract: Improved highly reliable power RFP structures and fabrication and operation processes. The structure includes plurality of localized dopant concentrated zones beneath the trenches of RFPs, either floating or extending and merging with the body layer of the MOSFET or connecting with the source layer through a region of vertical doped region. This local dopant zone decreases the minority carrier injection efficiency of the body diode of the device and alters the electric field distribution during the body diode reverse recovery.

Abstract: This invention relates to methods for the production of micro-structured substrates and their application in natural sciences and technology, in particular in semiconductor, microfluidic and analysis devices. It concerns a method of introducing a structure, such as a hole or cavity or channel or well or recess or a structural change by providing a controlled electrical discharge.

Abstract: An apparatus, system, and method for a capacitance change non-volatile memory device. The apparatus may include a substrate, a source region in the substrate, a drain region in the substrate, a tunnel oxide layer on the substrate substantially between the source region and the drain region, a floating gate layer on the tunnel oxide layer, a resistance changing material layer on the floating gate layer, and a control gate on the resistance changing material layer.

Abstract: Embodiments of the present invention generally provide a process and apparatus for increasing the absorption coefficient of a chamber component disposed in a thermal process chamber. In one embodiment, a method generally includes providing a substrate carrier having a first surface and a second surface, the first surface is configured to support a substrate and being parallel and opposite to the second surface, subjecting the second surface of the substrate carrier to a surface treatment process to roughen the second surface of the substrate carrier, wherein the substrate carrier contains a material comprising silicon carbide, and forming an oxide-containing layer on the roughened second surface of the substrate carrier. The formed oxide-containing layer has optical absorption properties at wavelengths close to the radiation delivered from one or more energy sources used to heat the chamber component.

Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Insulative material is deposited over the first electrode. An opening is formed into the insulative material over the first electrode. The opening includes sidewalls and a base. The opening sidewalls and base are lined with a multi-resistive state layer comprising multi-resistive state metal oxide-comprising material which less than fills the opening. A second conductive electrode of the memory cell is formed within the opening laterally inward of the multi-resistive state layer lining the sidewalls and elevationally over the multi-resistive state layer lining the base. Other aspects and implementations are contemplated.

Abstract: A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.

Abstract: The invention relates to a test method comprising an electrical connection contact on the support of a substrate of the semiconductor-on-insulator type. This method is remarkable in that it comprises the steps of: a) taking a substrate of the semiconductor-on-insulator type comprising a support substrate entirely covered with an insulator layer and an active layer, a portion of the insulator layer being buried between the active layer and the front face of the support substrate, b) removing a portion of the insulator layer that extends at the periphery of the front face of the support substrate and/or that extends on its rear face, so as to delimit at least one insulator-free accessible area of the support substrate, while retaining at least one portion of the insulator layer on the rear face, c) applying an electrical voltage to the accessible area in order to make the electrical connection contact.

Abstract: Fabricating single-walled carbon nanotube transistor devices includes removing undesirable types of nanotubes. These undesirable types of nanotubes may include nonsemiconducting nanotubes, multiwalled nanotubes, and others. The undesirable nanotubes may be removed electrically using voltage or current, or a combination of these. This approach to removing undesirable nanotubes is sometimes referred to as “burn-off.” The undesirable nanotubes may be removed chemically or using radiation. The undesirable nanotubes of an integrated circuit may be removed in sections or one transistor (or a group of transistors) at a time in order to reduce the electrical current used or prevent damage to the integrated circuit during burn-off.

Abstract: A reconfigurable device and a method of creating, erasing, or reconfiguring the device are provided. At an interface between a first insulating layer and a second insulating layer, an electrically conductive, quasi one- or zero-dimensional electron gas is present such that the interface presents an electrically conductive region that is non-volatile. The second insulating layer is of a thickness to allow metal-insulator transitions upon the application of a first external electric field. The electrically conductive region is subject to erasing upon application of a second external electric field.