Abstract: A semiconductor laser device includes a semiconductor multilayer structure selectively grown on a substrate other than on a predetermined region of the substrate. The semiconductor multilayer structure includes an active layer, and has a stripe-shaped optical waveguide extending in a direction intersecting a front facet through which light is emitted. The active layer has an abnormal growth portion formed at a peripheral edge of the predetermined region, and a larger forbidden band width portion formed around the abnormal growth portion and having a larger width of a forbidden band than that of a portion other than the abnormal growth portion of the active layer. The optical waveguide is spaced apart from the abnormal growth portion and includes the larger forbidden band width portion at the front facet.

Abstract: A method for growing a SiC-containing film on a Si substrate is disclosed. The SiC-containing film can be formed on a Si substrate by, for example, plasma sputtering, chemical vapor deposition, or atomic layer deposition. The thus-grown SiC-containing film provides an alternative to expensive SiC wafers for growing semiconductor crystals.

Abstract: A semiconductor device includes: a monocrystalline substrate; an inter-layer film formed on the monocrystalline substrate; a contact hole penetrating the inter-layer film and partially exposing an upper surface of the monocrystalline substrate; a sidewall formed on an inner surface of the contact hole; a plurality of first monocrystalline layers which include few defects, fill the contact hole, and cover the inter-layer film; and a plurality of second monocrystalline layers which include many defects and cover the sidewall and an upper surface of the inter-layer film so as to be sandwiched between the first monocrystalline layers and the inter-layer film.

Abstract: In one embodiment, an ESD device is configured to include a zener diode and a P-N diode and to have a conductor that provides a current path between the zener diode and the P-N diode.

Abstract: Various methods and devices are implemented using efficient silicon compatible integrated light communicators. According to one embodiment of the present invention, a semiconductor device is implemented for communicating light, such as by detecting, modulating or emitting light. The device has a silicon-seeding location, an insulator layer and a second layer on the insulator layer. The second layer includes a silicon-on-insulator region and an active region surrounded by the silicon-on-insulator region and connected to the silicon-seeding location. The active region includes a single-crystalline germanium-based material that extends from the silicon-seeding location through a passageway with a cross-sectional area that is sufficiently small to mitigate crystalline growth defects.

Abstract: The present invention relates to a method for position-controlled fabrication of a semiconductor quantum dot, the method comprising: providing a substrate (102) of a substrate material; depositing a sacrificial layer (108) of a sacrificial material; depositing an active layer (110) of a semiconductive active material on the sacrificial layer, wherein the substrate, sacrificial and active materials are chosen such that the sacrificial layer is selectively removable with respect to the substrate and the active layer, depositing and patterning a mask layer on the active layer so as to define desired quantum-dot positions in lateral directions, fabricating a lateral access to the sacrificial layer in regions underneath the patterned mask layer; selectively removing, with respect to the substrate and the active layer, the sacrificial layer from underneath the active layer at least under the patterned mask layer; and etching the active layer under the patterned mask layer from underneath the active layer so as to a

Abstract: In one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a resist on a subject layer containing silicon. The method can etch the subject layer using the resist as a mask and with a gas containing a halogen element, which is introduced into a processing chamber. After the etching of the subject layer, the method can slim a planner size of the resist with oxygen gas and a gas containing a halogen element, which are introduced into the same processing chamber.

Abstract: A method for producing a film of compound semiconductor includes providing a substrate and a compound bulk material having a first chemical composition that includes at least one first chemical element and a second chemical element. A film is deposited on the substrate using the compound bulk material as a single source of material. The deposited film has a composition substantially the same as the first chemical composition. A residual chemical reaction is induced in the deposited film using a source containing the second chemical element to thereby increase the content of the second chemical element in the deposited film so that the deposited film has a second chemical composition. The film may be employed in a photovoltaic device.

Abstract: A chemical vapor deposition (CVD) method for selectively depositing GeSb materials onto a surface of a substrate is provided in which a metal that is capable of forming an eutectic alloy with germanium is used to catalyze the growth of the GeSb materials. A structure is also provided that includes a GeSb material located on preselected regions of a substrate. In accordance with the present invention, the GeSb material is sandwiched between a lower metal layer used to catalyze the growth of the GeSb and an upper surface metal layer that forms during the growth of the GeSb material.

Abstract: The present invention relates to a semiconductor device and a method of manufacture thereof, being capable of improving the high integration by increasing a cell region while securing the reliability of device and the process margin through forming a cell region and a core region with the stacking structure.

Abstract: A method for preparing a cadmium sulfide film comprises: providing a slurry; coating a first substrate with the slurry; heating the first substrate to produce a vapor; and depositing the vapor on a second substrate to form a cadmium sulfide film. The slurry comprises a dispersant, cadmium particles and sulfur particles.

Abstract: A Ge epitaxial layer is grown on a silicon substrate with a patterned structure. Through a cyclic annealing, dislocation defects are confined. The present invention provides a method for manufacturing a high-quality Ge epitaxial layer with a low cost and a simple procedure. The Ge epitaxial layer obtained can be applied to high mobility Ge devices or any lattice-mismatched epitaxy on a photonics device.

Abstract: A nonvolatile semiconductor memory device includes: forming a stacked body by alternately stacking a plurality of interlayer insulating films and a plurality of control gate electrodes; forming a through-hole extending in a stacking direction in the stacked body; etching a portion of the interlayer insulating film facing the through-hole via the through-hole to remove the portion; forming a removed portion; forming a first insulating film on inner faces of the through-hole and the portion in which the interlayer insulating films are removed; forming a floating gate electrode in the portion in which the interlayer insulating films are removed; forming a second insulating film so as to cover a portion of the floating gate electrode facing the through-hole; and burying a semiconductor pillar in the through-hole.

Abstract: A photodiode is formed in a recessed germanium (Ge) region in a silicon (Si) substrate. The Ge region may be fabricated by etching a hole through a passivation layer on the Si substrate and into the Si substrate and then growing Ge in the hole by a selective epitaxial process. The Ge appears to grow better selectively in the hole than on a Si or oxide surface. The Ge may grow up some or all of the passivation sidewall of the hole to conformally fill the hole and produce a recessed Ge region that is approximately flush with the surface of the substrate, without characteristic slanted sides of a mesa. The hole may be etched deep enough so the photodiode is thick enough to obtain good coupling efficiencies to vertical, free-space light entering the photodiode.

Abstract: A compound semiconductor workpiece with reduced defects and greater strength that uses Group II-VI semiconductor nanoislands on a substrate. Additional layers of Group II-VI semiconductor are grown on the nanoislands using MBE until the newly formed layers coalesce to form a uniform layer of a desired thickness. In an alternate embodiment, nanoholes are patterned into a silicon nitride layer to expose an elemental silicon surface of a substrate. Group II-VI semiconductor material is grown in the holes until the layers fill the holes and coalesce to form a uniform layer of a desired thickness. Suitable materials for the substrate include silicon and silicon on insulator materials and cadmium telluride may be used as the Group II-VI semiconductor.

Abstract: An embedded MEMS semiconductor substrate is set forth and can be a starting material for subsequent semiconductor device processing. A MEMS device is formed in a semiconductor substrate, including at least one MEMS electrode and a buried silicon dioxide sacrificial layer has been applied for releasing the MEMS. A planarizing layer is applied over the substrate, MEMS device and MEMS electrode. A polysilicon protection layer is applied over the planarizing layer. A polysilicon nitride capping layer is applied over the polysilicon protection layer. A polysilicon seed layer is applied over the polysilicon nitride capping layer. The MEMS device is released by removing at least a portion of the buried silicon dioxide sacrificial layer and an epitaxial layer is grown over the polysilicon seed layer to be used for subsequent semiconductor wafer processing.

Abstract: The present invention provides a single-electron device composed of a necklace of about 5000 nanoparticles. The linear necklace is self-assembled by interfacial phenomena along a triple-phase line of fiber, a substrate and electrolyte containing nanoparticles. A variety of combinations of nanoparticles, such as Au and CdS nanoparticles, may be used to form a necklace. The I-V measurements on the system show both coulomb blockade and staircase, with high currents and high threshold voltage of 1-3 V. The present invention also provides methods for constructing such a device.

Abstract: A method for preparing an AlGaN crystal layer with good surface flatness is provided. A surface layer of AlN is epitaxially formed on a c-plane sapphire single crystal base material by MOCVD method, and the resulting laminated body is then heated at a temperature of 1300° C. or higher so that a template substrate applying in-plane compressive stress and having a surface layer flat at a substantially atomic level is obtained. An AlGaN layer is formed on the template substrate at a deposition temperature higher than 1000° C. by an MOCVD method that includes depositing alternating layers of a first unit layer including a Group III nitride represented by the composition formula AlxGa1-xN (0?x?1) and a second unit layer including a Group III nitride represented by the composition formula AlyGa1-yN (0?y?1 and y?x) such that the AlGaN layer has a superlattice structure.

Abstract: A device 100 comprising a substrate 115 having crystal-support-structures 110 thereon, and a III-V crystal 210. The III-V crystal is on a single contact region 140 of one of the crystal-support-structures. An area of the contact region is no more than about 50 percent of a surface area 320 of the III-V crystal.

Abstract: A method for fabricating a semiconductor device includes forming a sacrificial layer over a substrate, forming a contact hole in the sacrificial layer, forming a pillar to fill the contact hole. The pillar laterally extends up to a surface of the sacrificial layer and then the sacrificial layer is removed. The method further includes forming a gate dielectric layer over an exposed sidewall of the pillar, and forming a gate electrode over the gate dielectric layer. The gate electrode surrounds the sidewall of the pillar.

Abstract: Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during formation of a semiconductor construction. In some embodiments, the microwave radiation has a frequency of about 5.8 gigahertz, and a temperature of the semiconductor construction does not exceed about 500° C. during the exposure to the microwave radiation.

Abstract: A method of forming a circuit structure includes providing a substrate; etching the substrate to form nano-structures; and growing a compound semiconductor material onto the nano-structures using epitaxial growth. Portions of the compound semiconductor material grown from neighboring ones of the nano-structures join each other to form a continuous compound semiconductor film. The method further includes separating the continuous compound semiconductor film from the substrate.

Abstract: Provided are a semiconductor layer manufacturing method and a semiconductor manufacturing apparatus capable of forming a high quality semiconductor layer even by a single chamber system, with a shortened process time required for reducing a concentration of impurities that exist in a reaction chamber before forming the semiconductor layer. A semiconductor device manufactured using such a method and apparatus is also provided.

Abstract: A method of removing a substrate structure is described. A plurality of pillars is formed on a substrate by using a photolithography etching process. A group III nitride semiconductor layer is grown on the plurality of pillars. The plurality of pillars is etched to separate the group III nitride semiconductor layer from the substrate by using a chemical etching process.

Abstract: A method for manufacturing an epitaxial wafer is provided, which can alleviate distortions on a back surface of the epitaxial wafer. The method for manufacturing an epitaxial wafer using a susceptor for a vapor phase growth system having a concave shaped wafer placement portion on an upper face thereof, on which a semiconductor wafer is placed, includes: an oxide film forming step in which an oxide film Ox is formed on a back surface of the semiconductor wafer; a wafer placing step in which, after the oxide film forming step, the semiconductor wafer is placed on a wafer placement portion so that the back surface of the semiconductor wafer faces downward; and an epitaxial growth step in which, after the wafer placing step, an epitaxial layer is grown on a main surface of the semiconductor wafer.

Abstract: A method of manufacturing a semiconductor substrate includes a growing step of growing a second single crystalline semiconductor on a first single crystalline semiconductor, a blocking layer forming step of forming a blocking layer on the second single crystalline semiconductor, and a relaxing step of generating crystal defects at a portion deeper than the blocking layer to relax a stress acting on the second single crystalline semiconductor. The blocking layer includes, e.g., a porous layer, and prevents the crystal defects at the portion deeper than the blocking layer from propagating to the surface of the second single crystalline semiconductor.

Abstract: A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y?1E-5exp(21541/T).

Abstract: There is provided a method for preparing an AlGaN crystal layer having an excellent surface flatness. A buffer layer effective in stress relaxation is formed on a template substrate having a surface layer that is flat at a substantially atomic level and to which in-plane compressive stress is applied, and an AlGaN layer is formed on the buffer layer, so that an AlGaN layer can be formed that is flat at a substantially atomic level. Particularly when the surface layer of the template substrate includes a first AlN layer, a second AlN layer may be formed thereon at a temperature of 600° C. or lower, while a mixed gas of TMA and TMG is supplied in a TMG/TMA mixing ratio of 3/17 or more to 6/17 or less, so that a buffer layer effective in stress relaxation the can be formed in a preferred manner.

Abstract: In a method of making a c-Si-based cell or a ?c-Si-based cell, the improvement of increasing the minority charge carrier's lifetime, comprising: a) placing a c-Si or polysilicon wafer into CVD reaction chamber under a low vacuum condition and subjecting the substrate of the wafer to heating; and b) passing mixing gases comprising NH3/H2 through the reaction chamber at a low vacuum pressure for a sufficient time and at a sufficient flow rate to enable growth of an a-Si:H layer sufficient to increase the lifetime of the c-Si or polysilicon cell beyond that of the growth of an a-Si:H layer without treatment of the wafer with NH3/H2.

Abstract: A semiconductor light emitting device has an n-type layer, a p-type layer, and a light-emitting active layer arranged between the p-type layer and the n-type layer, the active layer having alternating regions of doped and undoped materials. A double heterojunction light emitting device has a bulk active layer having doped portions alternating with undoped portions. A method of manufacturing a light emitting device includes forming a first layer arranged on a substrate, growing an active layer, selectively adding impurities at predetermined times during the growing of the active layer, and forming a second layer arranged on the active layer.

Abstract: A doped semiconductor junction for use in an electronic device and a method for making such junction is disclosed. The junction includes a first polycrystalline semiconductor layer doped with donors or acceptors over a substrate such that the first doped semiconductor layer has a first polarity, the first layer including fused semiconductor nanoparticles; and a second layer in contact with the first semiconductor layer over a substrate to form the semiconductor junction.

Abstract: A method of making a solar grade silicon wafer is disclosed. In at least some embodiments of this invention, the method includes the follow steps: providing a slurry including a liquid that essentially prevents the oxidation of silicon powder and a silicon powder that is essentially free of oxides; providing a solar grade wafer mold defining an interior for receiving the slurry; introducing the slurry into the solar grade wafer mold; precipitating the silicon powder from the slurry to form a preform of the solar grade silicon wafer; and crystallizing the preform to make the solar grade silicon wafer.

Abstract: This invention generally relates to a process for suppressing silicon self-interstitial diffusion near the substrate/epitaxial layer interface of an epitaxial silicon wafer having a heavily doped silicon substrate and a lightly doped silicon epitaxial layer. Interstitial diffusion into the epitaxial layer is suppressed by a silicon self-interstitial sink layer comprising dislocation loops.

Abstract: The present III-nitride crystal manufacturing method, a method of manufacturing a III-nitride crystal (20) having a major surface (20m) of plane orientation other than {0001}, designated by choice, includes: a step of slicing III-nitride bulk crystal (1) into a plurality of III-nitride crystal substrates (10p), (10q) having major surfaces (10pm), (10qm) of the designated plane orientation; a step of disposing the substrates (10p), (10q) adjoining each other sideways in such a way that the major surfaces (10pm), (10qm) of the substrates (10p), (10q) parallel each other and so that the [0001] directions in the substrates (10p), (10q) are oriented in the same way; and a step of growing III-nitride crystal (20) onto the major surfaces (10pm), (10qm) of the substrates (10p), (10q).

Abstract: A semiconductor device includes: a monocrystalline substrate; an inter-layer film formed on the monocrystalline substrate; a contact hole penetrating the inter-layer film and partially exposing an upper surface of the monocrystalline substrate; a sidewall formed on an inner surface of the contact hole; a plurality of first monocrystalline layers which include few defects, fill the contact hole, and cover the inter-layer film; and a plurality of second monocrystalline layers which include many defects and cover the sidewall and an upper surface of the inter-layer film so as to be sandwiched between the first monocrystalline layers and the inter-layer film.

Abstract: A multiplicity of silicon wafers polished at least on their front sides are provided and successively coated individually in an epitaxy reactor by a procedure whereby one of the wafers is placed on a susceptor in the epitaxy reactor, is pretreated under a hydrogen atmosphere at a first hydrogen flow rate, and with addition of an etching medium to the hydrogen atmosphere at a reduced hydrogen flow rate in a second step, is subsequently coated epitaxially on its polished front side, and removed from the reactor. An etching treatment of the susceptor follows a specific number of epitaxial coatings. Silicon wafers produced thereby have a global flatness value GBIR of 0.07-0.3 ?m relative to an edge exclusion of 2 mm.

Abstract: There is provided a method for fabricating a gallium nitride crystal with low dislocation density, high crystallinity, and resistance to cracking during polishing of sliced pieces by growing the gallium nitride crystal using a gallium nitride substrate including dislocation-concentrated regions or inverted-polarity regions as a seed crystal substrate. Growing a gallium nitride crystal 79 at a growth temperature higher than 1,100° C. and equal to or lower than 1,300° C. so as to bury dislocation-concentrated regions or inverted-polarity regions 17a reduces dislocations inherited from the dislocation-concentrated regions or inverted regions 17a, thus preventing new dislocations from occurring over the dislocation-concentrated regions or inverted-polarity regions 17a. This also increases the crystallinity of the gallium nitride crystal 79 and its resistance to cracking during the polishing.

Abstract: An optical semiconductor device with a multiple quantum well structure, in which well layers and barrier layers comprising various types of semiconductor layers are alternately layered, in which device well layers (6a) of a first composition based on a nitride semiconductor material with a first electron energy and barrier layers (6b) of a second composition of a nitride semiconductor material with electron energy which is higher in comparison with the first electron energy are provided, followed, seen in the direction of growth, by a radiation-active quantum well layer (6c), for which the essentially non-radiating well layers (6a) and the barrier layers (6b) arranged in front form a superlattice.

Abstract: A method for fabricating a semiconductor device includes forming a sacrificial layer over a substrate, forming a contact hole in the sacrificial layer, forming a pillar to fill the contact hole. The pillar laterally extends up to a surface of the sacrificial layer and then the sacrificial layer is removed. The method further includes forming a gate dielectric layer over an exposed sidewall of the pillar, and forming a gate electrode over the gate dielectric layer. The gate electrode surrounds the sidewall of the pillar.

Abstract: The present invention relates to a semiconductor device and a method of manufacture thereof, being capable of improving the high integration by increasing a cell region while securing the reliability of device and the process margin through forming a cell region and a core region with the stacking structure.

Abstract: A deposition method which deposits a CdS buffer layer on a surface of a solar cell from a process solution including all chemical components of the CdS buffer layer material. CdS is deposited in a deposition chamber by heating the surface of the solar cell absorber to cause the transfer of heat from the solar cell absorber layer to at least a portion of the process solution that is in contact with the surface. Used solution is cooled, and replenished in a solution container and redirected into the deposition chamber.

Abstract: A method of forming composite nanostructures using one or more nanomaterials. The method provides a nanostructure material having a surface region and one or more nano void regions within a first thickness in the surface region. The method subjects the surface region of the nanostructure material with a fluid. An external energy is applied to the fluid and/or the nanostructure material to drive in a portion of the fluid into one or more of the void regions and cause the one or more nano void regions to be substantially filled with the fluid and free from air gaps.

Abstract: A catalyst particle on a substrate is exposed to reactants containing a semiconductor material in a reactor. An intrinsic semiconductor nanowire having constant lateral dimensions is grown at a low enough temperature so that pyrolysis of the reactant is suppressed on the sidewalls of the intrinsic semiconductor nanowire. Once the intrinsic semiconductor nanowire grows to a desired length, the temperature of the reactor is raised to enable pyrolysis on the sidewalls of the semiconductor nanowire, and thereafter dopants are supplied into the reactor with the reactant. A composite semiconductor nanowire having an intrinsic inner semiconductor nanowire and a doped semiconductor shell is formed. The catalyst particle is removed, followed by an anneal that distributes the dopants uniformly within the volume of the composite semiconductor nanowire, forming a semiconductor nanowire having constant lateral dimensions and a substantially uniform doping.

Abstract: Methods and apparatus for producing a gallium nitride semiconductor on insulator structure include: bonding a single crystal silicon layer to a transparent substrate; and growing a single crystal gallium nitride layer on the single crystal silicon layer.

Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.

Abstract: Formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed on the semiconductor substrate for at least three times to form all semiconductor layers, of the epitaxial layers. Thereby, impurity concentration profiles of the semiconductor layers can be uniform, and pn junctions can be formed vertically to a wafer surface. Furthermore, the semiconductor layers can each be formed with a narrow width, so that impurity concentrations thereof are increased. With this configuration, high breakdown voltage and low resistance can be achieved.

Abstract: A growth plane of substrate 1 is processed to have a concavo-convex surface. The bottom of the concave part may be masked. When a crystal is grown by vapor phase growth using this substrate, an ingredient gas does not sufficiently reach the inside of a concave part 12, and therefore, a crystal growth occurs only from an upper part of a convex part 11. As shown in FIG. 1(b), therefore, a crystal unit 20 occurs when the crystal growth is started, and as the crystal growth proceeds, films grown in the lateral direction from the upper part of the convex part 11 as a starting point are connected to cover the concavo-convex surface of the substrate 1, leaving a cavity 13 in the concave part, as shown in FIG. 1(c), thereby giving a crystal layer 2, whereby the semiconductor base of the present invention is obtained. In this case, the part grown in the lateral direction, or the upper part of the concave part 12 has a low dislocation region and the crystal layer prepared has high quality.

Abstract: A method to fabricate adjacent silicon fins of differing heights comprises providing a silicon substrate having an isolation layer deposited thereon, patterning the isolation layer to form first and second isolation structures, patterning the silicon substrate to form a first silicon fin beneath the first isolation structure and a second silicon fin beneath the second isolation structure, depositing an insulating layer on the substrate, planarizing the insulating layer to expose top surfaces of the first and second isolation structures, depositing and patterning a masking layer to mask the first isolation structure but not the second isolation structure, applying a wet etch to remove the second isolation structure and expose the second silicon fin, epitaxially depositing a silicon layer on the second silicon fin, and recessing the insulating layer to expose at least a portion of the first silicon fin and at least a portion of the second silicon fin.

Abstract: A method is disclosed for making a doped semiconductor transport layer for use in an electronic device comprising: growing in-situ doped semiconductor nanoparticles in a colloidal solution; depositing the in-situ doped semiconductor nanoparticles on a surface; and annealing the deposited in-situ doped semiconductor nanoparticles so that the organic ligands boil off the surface of the in-situ doped semiconductor nanoparticles.

Abstract: A method for manufacturing a semiconductor wafer with a strained Si layer having sufficient tensile strain and few crystal defects, while achieving a relatively simple layered structure, is provided.