Abstract: A programmable resistance, chalcogenide, switching or phase-change material device includes a substrate with a plurality of stacked layers including a conducting bottom composite electrode layer, an insulative layer having an opening formed therein, an active material layer deposited over both the insulative layer and the bottom composite electrode, and a top electrode layer deposited over the active material layer. The device uses a chemical or electrochemical liquid phase deposition process to selectively and conformally fill the insulative layer opening with the conductive bottom composite electrode layer. Conformally filling the conductive material within the opening reduces structural irregularities within the opening thereby increasing material density and resistivity within the device and thereby improving device performance and reducing programming current.

Abstract: A method for growing a SiC-containing film on a Si substrate is disclosed. The SiC-containing film can be formed on a Si substrate by, for example, plasma sputtering, chemical vapor deposition, or atomic layer deposition. The thus-grown SiC-containing film provides an alternative to expensive SiC wafers for growing semiconductor crystals.

Abstract: This invention generally relates to a process for suppressing silicon self-interstitial diffusion near the substrate/epitaxial layer interface of an epitaxial silicon wafer having a heavily doped silicon substrate and a lightly doped silicon epitaxial layer. Interstitial diffusion into the epitaxial layer is suppressed by a silicon self-interstitial sink layer comprising dislocation loops.

Abstract: Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.

Abstract: A method forming a Group IV semiconductor junction on a substrate is disclosed. The method includes depositing a first set Group IV semiconductor nanoparticles on the substrate. The method also includes applying a first laser at a first laser wavelength, a first fluence, a first pulse duration, a first number of repetitions, and a first repetition rate to the first set Group IV semiconductor nanoparticles to form a first densified film with a first thickness, wherein the first laser wavelength and the first fluence are selected to limit a first depth profile of the first laser to the first thickness. The method further includes depositing a second set Group IV semiconductor nanoparticles on the first densified film.

Abstract: The invention relates to a method of forming a layer of elastically unstrained crystalline material intended for electronics, optics, or optronics applications, wherein the method is carried out using a structure that includes a first crystalline layer which is elastically strained under tension (or respectively in compression) and a second crystalline layer which is elastically strained in compression (or respectively under tension), with the second layer being adjacent to the first layer.

Abstract: A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate and forms a first aluminum (Al)-containing film in compression overlying the Si substrate. Nano-column holes are formed in the first Al-containing film, which exposes regions of the underlying Si substrate. A layer of GaN layer is selectively grown from the exposed regions, covering the first Al-containing film. The GaN is grown using a lateral nanoheteroepitaxy overgrowth (LNEO) process. The above-mentioned processes are reiterated, forming a second Al-containing film in compression, forming nano-column holes in the second Al-containing film, and selectively growing a second GaN layer. Film materials such as Al2O3, Si1-xGex, InP, GaP, GaAs, AlN, AlGaN, or GaN, may be initially grown at a low temperature. By increasing the growth temperatures, a compressed layer of epitaxial GaN can be formed on a Si substrate.

Abstract: Methods and systems for improving heteroepitaxial crystal quality of semiconductor materials include forming a pattern on the semiconductor substrate over which the hetero-epitaxial layer is grown. The pattern provides predetermined sites for dislocation initiation and termination of dislocation propagation. The layer may be treated with a focused laser beam during or subsequent to the layer growth process. Laser light may be focused at a selected depth, where the light intensity is sufficient to cause structural and/or electronic changes localized at that depth. The laser beam may be selectively scanned to provide the desired change only at preferred spatial locations on the substrate. The laser wavelength and power may be selected to be appropriate for the materials being treated.

Abstract: A method of making efficient Integrated Diamond Carrier heat sink and mounting structures usable typically to mount the solid-state laser bars often employed for pumping high power lasers, for example. The disclosed method forms the Integrated Diamond Carrier on a shaped sacrificial substrate member by chemical vapor deposition growing of diamond on a patterned substrate, made from for example silicon semiconductor. The substrate serves as a mold and is etched away after Integrated Diamond Carrier base plate formation leaving the freestanding diamond carrier. Optically usable surfaces are achieved on the Integrated Diamond Carrier through use of substrate crystal plane characteristics and an improved deposition arrangement.

Abstract: A method of making a solar grade silicon wafer is disclosed. In at least some embodiments of this invention, the method includes the follow steps: providing a slurry including a liquid that essentially prevents the oxidation of silicon powder and a silicon powder that is essentially free of oxides; providing a solar grade wafer mold defining an interior for receiving the slurry; introducing the slurry into the solar grade wafer mold; precipitating the silicon powder from the slurry to form a preform of the solar grade silicon wafer; and crystallizing the preform to make the solar grade silicon wafer.

Abstract: The fabrication method of a mixed substrate comprising a tensile strained silicon-on-insulator portion and a compressive strained germanium-on-insulator portion comprises a first step of producing a strained silicon-on-insulator base substrate comprising first and second tensile strained silicon zones. After the base substrate has been produced, the method comprises the successive steps of masking the first tensile strained silicon zone forming the tensile strained silicon-on-insulator portion of the substrate, of performing germanium enrichment treatment of the second tensile strained silicon zone of the base substrate until a compressive strained germanium layer is obtained forming said compressive strained germanium-on-insulator portion of the substrate, and of removing the masking.

Abstract: The present invention relates to a novel process for producing (Al, Ga)InN and AlGaInN single crystals by means of a modified HVPE process, and also to (Al, Ga)InN and AlGaInN bulk crystals of high quality, in particular homogeneity. The III-V compound semiconductors produced by the process according to the invention are used in optoelectronics, in particular for blue, white and green LEDs and also for high-power, high-temperature and high-frequency field effect transistors.

Abstract: The invention relates to a method for producing a layer structure comprising a strained layer on a substrate. The inventive method comprises the steps of producing a defect area in a layer adjoining the layer to be strained, and relaxing at least one layer adjoining the layer to be strained. The defect area is especially produced in the substrate. Additional layers can be epitactically grown. Layer structures so produced are especially suitable for producing various types of components.

Abstract: A method for selectively forming an epitaxial Si containing film on a semiconductor structure at low temperature. The method includes providing the structure in a process chamber, the structure containing a Si substrate having an epitaxial Si surface area and a patterned film area thereon. A Si film is non-selectively deposited onto the structure, the Si film comprising an epitaxial Si film deposited onto the epitaxial Si surface and a non-epitaxial Si film deposited onto an exposed surface of the patterned film. The non-epitaxial Si film is selectively dry etched away to form a patterned epitaxial Si film. The Si film may be a SiGe film.

Abstract: A charge compensation component having a drift path between two electrodes, an electrode and a counterelectrode, and methods for producing the same. The drift path has drift zones of a first conduction type and charge compensation zones of a complementary conduction type with respect to the first conduction type. A drift path layer doping comprising the volume integral of the doping locations of a horizontal drift path layer of the vertically extending drift path including the drift zone regions and charge compensation zone regions arranged in the drift path layer is greater in the vicinity of the electrodes than in the direction of the centre of the drift path.

Abstract: Methods are provided for fabricating memory devices. A method comprises fabricating charge-trapping stacks overlying a silicon substrate and forming bit line regions in the substrate between the charge trapping stacks. Insulating elements are formed overlying the bit line regions between the stacks. The charge-trapping stacks are etched to form two complementary charge storage nodes and to expose portions of the silicon substrate. Silicon is grown on the exposed silicon substrate by selective epitaxial growth and is oxidized. A control gate layer is formed overlying the complementary charge storage nodes and the oxidized epitaxially-grown silicon.

Abstract: The present invention relates to a nitride semiconductor substrate such as gallium nitride substrate and a method for manufacturing the same. The present invention forms a plurality of trenches on a lower surface of a base substrate that are configured to absorb or reduce stresses applied larger when growing a nitride semiconductor film on the base substrate from a central portion of the base substrate towards a peripheral portion. That is, the present invention forms the trenches on the lower surface of the base substrate such that pitches get smaller or widths or depths get larger from the central portion of the base substrate towards the peripheral portion.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming an oxide film on a surface layer section of an entire surface of a semiconductor substrate, forming a window section by selectively removing the oxide film from an active surface side of the semiconductor substrate, the window section exposing a substrate semiconductor layer forming the semiconductor substrate, forming a first semiconductor layer having an etching selection ratio higher than an etching selection ratio of the substrate semiconductor layer so as to cover the substrate semiconductor layer exposed in the window section, forming a second semiconductor layer having an etching selection ratio higher than the etching selection ratio of the first semiconductor layer so as to cover the first semiconductor layer, forming a pair of support member holes for exposing the substrate semiconductor layer opened by removing the second semiconductor layer and the first semiconductor layer inside a pair of areas positioned on both side

Abstract: A method of making an ex-situ doped semiconductor transport layer for use in an electronic device includes: growing a first set of semiconductor nanoparticles having surface organic ligands in a colloidal solution; growing a second set of dopant material nanoparticles having surface organic ligands in a colloidal solution; depositing a mixture of the first set of semiconductor nanoparticles and the second set of dopant material nanoparticles on a surface, wherein there are more semiconductor nanoparticles than dopant material nanoparticles; performing a first anneal of the deposited mixture of nanoparticles so that the organic ligands boil off the surfaces of the first and second set of nanoparticles; performing a second anneal of the deposited mixture so that the semiconductor nanoparticles fuse to form a continuous semiconductor layer and the dopant material atoms diffuse out from the dopant material nanoparticles and into the continuous semiconductor layer.

Abstract: Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are injected into the reaction chamber to selectively grow an epitaxial semiconductor layer on a sidewall and on a bottom surface of the recess. A selective etching gas is injected into the reaction chamber to selectively etch a fence of the epitaxial semiconductor layer which is adjacent to the sidewall of the recess and grown to a level that is higher than an upper surface of the semiconductor substrate.

Abstract: A method for growing an improved quality device by depositing a low temperature (LT) magnesium (Mg) doped nitride semiconductor thin film. The low temperature Mg doped nitride semiconductor thin film may have a thickness greater than 50 nm. A multi quantum well (MQW) active layer may be grown at a growth temperature and the LT Mg doped nitride semiconductor thin film may deposited on the MQW active layer at a substrate temperature no greater than 150° C. above the growth temperature.

Abstract: A method comprises, in a reaction chamber, depositing a seed layer of germanium over a silicon-containing surface at a first temperature. The seed layer has a thickness between about one monolayer and about 1000 ?. The method further comprises, after depositing the seed layer, increasing the temperature of the reaction chamber while continuing to deposit germanium. The method further comprises holding the reaction chamber in a second temperature range while continuing to deposit germanium. The second temperature range is greater than the first temperature.

Abstract: An n-type field effect transistor (NFET) and methods of forming a halo for an NFET to control the short channel effect are disclosed. One method includes forming a gate over a silicon substrate; recessing the silicon adjacent to the gate; forming a halo by epitaxially growing boron in-situ doped silicon germanium (SiGe) in the recess; and epitaxially growing silicon over the silicon germanium. Alternatively, the halo can be formed by ion implanting boron into an embedded SiGe region within the silicon substrate. The resulting NFET includes a boron doped SiGe halo embedded within the silicon substrate. The embedded SiGe layer may be a relaxed layer without inserting strain in the channel. The high solid solubility of boron in SiGe and low diffusion rate allows formation of a halo that will maintain the sharp profile, which provides better control of the short channel effect and increasing control over NFET threshold voltage roll-off.

Abstract: A method for fabricating a plurality of semiconductor bodies, in particular based on nitride compound semiconductor material. The method includes forming a mask layer (3) over a substrate (1) or over an initial layer (2), which mask layer has a plurality of windows (4) leading to the substrate (1) or to the initial layer (2), etching back the substrate (1) or the initial layer (2) in the windows (4), in such a manner that pits (41) are formed in the substrate (1) or in the initial layer (2) starting from these windows.

Abstract: A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the SiGe source/drain extensions 90 and the semiconductor wafer 10 is annealed. Also, a transistor source/drain region 80, 90 having a SiGe source/drain extension 90 that contains evenly distributed dopants, is highly doped, and has highly abrupt edges.

Abstract: This invention pertains to electronic/optoelectronic devices with reduced extended defects and to a method for making it. The method includes the steps of depositing a dielectric thin film mask material on a semiconductor substrate surface; patterning the mask material to form openings therein extending to the substrate surface; growing active material in the openings; removing the mask material to form the device with reduced extended defect density; and depositing electrical contacts on the device.

Abstract: The invention provides an optical component whose siting, shape and size are well controlled and a method of manufacturing such an optical component. The optical component of the present invention includes a base member disposed on a substrate, and an optical member disposed on the top surface of the base member.

Abstract: A method of forming a lattice-tuning semiconductor substrate comprises the steps of defining parallel strips of a Si surface by the provision of spaced parallel oxide walls (2) on the surface, selectively growing a first SiGe layer on the strips such that first dislocations (3) extend preferentially across the first SiGe layer between the walls (2) to relieve the strain in the first SiGe layer in directions transverse to the walls (2), and growing a second SiGe layer on top of the first SiGe layer to overgrow the walls (2) such that second dislocations form preferentially within the second SiGe layer above the walls (2) to relieve the strain in the second SiGe layer in directions transverse to the first dislocations (3). The dislocations so produced serve to relax the material in two mutually transverse directions whilst being spatially separated so that the two sets of dislocations cannot interact with one another.

Abstract: A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode.

Abstract: An article comprises a semiconductor substrate and a coating mixture on the semiconductor substrate. The coating mixture Is comprised of adhesion promoter and photopolymer. The adhesion promoter contains ?-amino propyltriethoxysilane in organic solution.

Abstract: There are now provided thin-film solar cells and method of making. The devices comprise a low-cost, low thermal stability substrate with a semiconductor body deposited thereon by a deposition gas. The deposited body is treated with a conversion gas to provide a microcrystalline silicon body. The deposition gas and the conversion gas are subjected to a pulsed electromagnetic radiation to effectuate deposition and conversion.

Abstract: Methods for manufacturing semiconductor devices are disclosed. In a disclosed method, a first nitride layer and a device isolation oxide layer are etched to thereby expose a portion of a silicon substrate where an active region is to be formed. An epitaxial growth is performed on the active region and a first oxide layer is deposited thereon. Portions of the first oxide layer where a source and a drain are to be formed are etched. The first oxide layer deposited on the portions where the source and the drain are to be formed is then etched. An epitaxial growth is performed on the portions where the source and the drain are to be formed to thereby form the source and the drain. A second nitride layer is deposited thereon. A portion of the first oxide layer located where a gate is to be formed is etched using a gate mask. A third nitride layer is deposited on the source, the drain, and the exposed active region and then etched back to thereby form a nitride layer to control a length of the gate.

Abstract: A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium layer of a semiconductor substrate containing a single crystal silicon-germanium layer on the surface; forming a first single crystal silicon layer in the trench region and an active region; oxidizing the first single crystal silicon layer; forming a first thermal oxide layer on the surface of the first single crystal silicon layer; forming a device isolation region; embedding an insulator in the trench region; and forming a device in an active region over the single crystal silicon-germanium layer separated by the device isolation region, wherein the step of forming the device in the active region further includes forming a doped region of a depth to reach within the single crystal silicon-germanium layer below the first single crystal silicon layer.

Abstract: A surface-transformation method of forming regions of a second material in a first solid material to control the properties of the first solid material is disclosed. The regions of the second material are formed in the first solid material by drilling holes to a predefined depth and at a predefined lattice position. The holes in the first solid material are then filled with a second material and then the first and second materials are heated to a temperature close to the melting point of the first solid material to spontaneously form the regions filled with the second material and embedded in the first solid material at the desired location. A liquid-phase immersion method or a deposition method may be employed to fill the holes in the first solid material.

Abstract: A method for improving thermal dissipation in large gallium nitride light emitting diodes includes replacing sapphire with a better thermal conductor resulting in more efficient removal of thermal energy. A method for achieving a reliable and strong temporary bond between a GaN epitaxial layer and a support wafer. A method for transferring an epitaxial film from a growth substrate to a secondary substrate. An excimer laser initiates film delamination from the growth substrate. The laser beam is shaped by a shadow mask and aligned to an existing pattern in the growth substrate. A method for fabricating a LED that radiates white spectrum light. A phosphor that radiates a white spectrum after excitation in the blue or UV spectrum onto the GaN epitaxial wafer prior to die separation and packaging. A method for depositing a metal substrate onto a GaN epitaxy layer.

Abstract: The present invention provides a bump forming apparatus (101, 501) which can prevent charge appearance semiconductor substrates (201, 202) from pyroelectric breakdown and physical failures, a method carried out by the bump forming apparatus for removing charge of charge appearance semiconductor substrates, a charge removing unit for charge appearance semiconductor substrates, and a charge appearance semiconductor substrate. At least when the wafer is cooled after the bump bonding is connected on the wafer, electric charge accumulated on the wafer (202) because of the cooling is removed through direct contact with a post-forming bumps heating device (170), or the charge is removed by a decrease in temperature control so that charge can be removed in a noncontact state. Therefore, an amount of charge of the wafer can be reduced in comparison with the conventional art, so that the wafer is prevented from pyroelectric breakdown and damage such as a break or the like to the wafer itself.

Abstract: A semiconductor wafer with a front surface and a back surface and an epitaxial layer of semiconducting material deposited on the front surface, wherein the surface of the epitaxial layer has a maximum density of 0.14 localized light scatterers per cm2 with a cross section of greater than or equal to 0.12 ?m, and the front surface of the semiconductor wafer, prior to the deposition of the epitaxial layer, has a surface roughness of 0.05 to 0.29 nm RMS, measured by AFM on a 1 ?m×1 ?m reference area. There is also a process for producing a semiconductor wafer with a front surface and a back surface and an epitaxial layer of semiconducting material deposited on the front surface.

Abstract: In a separation layer removing process ?, temperature in a reaction chamber (heat treatment temperature TX) is raised to about 1000° C. and a separation layer A is evaporated through thermal decomposition, to thereby separate about 10 ?m in thickness of protection layer B from a base substrate side (a sapphire substrate 101 comprising a buffer layer 102). Because decomposition temperature of the separation layer A is higher than growth temperature of the protection layer B (about 650° C.) and lower than growth temperature of the semiconductor crystal C (about 1000° C.), the separation layer A vanishes (evaporates) by thermal decomposition, which generates this separation process. Accordingly, a semiconductor crystal having a cross sectional structure shown in FIG. 2B is obtained.

Abstract: Hemi-spherical grain silicon enhancement with epitaxial silicon for semiconductor assemblies is described. Epitaxial silicon is used to enhance hemi-spherical grain silicon on semiconductor structures, such as storage node capacitor plates for a semiconductor assembly. Methods described include forming an optional amorphous silicon layer as a base to firm hemi-shperical grain silicon thereon. The rough texture of the hemi-spherical grain silicon enhances the overall textured surface of the capacitor plate by the addition of epitaxial silicon.

Abstract: A transparent layer of a LED device and the method for growing the same are disclosed in this present invention. This present invention provides an improved liquid phase epitaxy (LPE) process for growing a transparent layer of a LED device. In the above-mentioned LPE process, an improved supersaturated solution is utilized to overcome the shortcomings in the prior art, wherein the supersaturated solution comprises antimony and/or indium as a solvent. Furthermore, a metallic zinc and/or magnesium dopant is added into the supersaturated solution to optimize the characters of the transparent layer. Therefore, this invention can provide a more efficient method for growing a transparent layer of a LED device, and the quality of the above-mentioned transparent layer can thereby be improved.

Abstract: A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium layer of a semiconductor substrate containing a single crystal silicon-germanium layer on the surface; forming a first single crystal silicon layer in the trench region and an active region; oxidizing the first single crystal silicon layer; forming a first thermal oxide layer on the surface of the first single crystal silicon layer; forming a device isolation region; embedding an insulator in the trench region; and forming a device in an active region over the single crystal silicon-germanium layer separated by the device isolation region, wherein the step of forming the device in the active region further includes forming a doped region of a depth to reach within the single crystal silicon-germanium layer below the first single crystal silicon layer.

Abstract: A technique for forming a film of crystalline material, preferably silicon. The technique creates a sandwich structure with a weakened region at a selected depth underneath the surface. The weakened region is a layer of porous silicon with high porosity. The high porosity enclosed layer is formed by (1) forming a porous silicon layer with low porosity on surface of the substrate, (2) epitaxial growth of a non-porous layer over the low-porous layer (3) increasing of porosity of the low-porous layer making the said layer hi-porous, (4) cleaving the semiconductor substrate at said high porous layer. The porosity of the buried low-porous layer is increased by hydrogenation techniques, for example, by processing in hydrogen plasma. The process is preferentially used to produce silicon-on-insulator wafers.

Abstract: A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique.

Abstract: A method of coating a semiconductor substrate material with a coating material consisting of the steps of mixing an adhesion promoter with a coating material and applying the mixture to a semiconductor substrate material. The invention also includes means for coating a semiconductor substrate material with a coating material comprising means for mixing adhesion promoters with coating materials and means for applying the mixture of adhesion promoters and coating materials to a semiconductor substrate.

Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Abstract: More specifically, gallium nitride semiconductor layers may be fabricated by etching an underlying gallium nitride layer on a sapphire substrate, to define at least one post in the underlying gallium nitride layer and at least one trench in the underlying gallium nitride layer. The at least one post includes a gallium nitride top and a gallium nitride sidewall. The at least one trench includes a trench floor. The gallium nitride sidewalls are laterally grown into the at least one trench, to thereby form a gallium nitride semiconductor layer. However, prior to performing the laterally growing step, the sapphire substrate and/or the underlying gallium nitride layer is treated to prevent growth of gallium nitride from the trench floor from interfering with the lateral growth of the gallium nitride sidewalls of the at least one post into the at least one trench.

Abstract: A method and an apparatus for growing a layer on one surface of a wafer by liquid phase deposition are provided. At first, a first wafer is putted on a first wafer-holder by its first surface. Then, a growth-liquid vessel having a first opening at the bottom is mounted on the first wafer-holder. Thereafter, a growth liquid is poured into the growth-liquid vessel to expose a second surface of the first wafer to the growth liquid for growing the layer on the second surface of the first wafer. Then, the, first wafer is taken out from the first wafer-holder to obtain a wafer with a layer grown only on one surface.

Abstract: A process for epitaxially coating the front surface of a semiconductor wafer in a CVD reactor, the front surface of the semiconductor wafer being exposed to a process gas which contains a source gas and a carrier gas, and the back surface of the semiconductor wafer being exposed to a displacement gas, wherein the displacement gas contains no more than 5% by volume of hydrogen, with the result that diffusion of dopants out of the back surface of the semiconductor wafer, which is intensified by hydrogen, is substantially avoided. With this process, it is possible to produce a semiconductor wafer with a substrate resistivity of ≦100 m&OHgr;cm and a resistivity of the epitaxial layer of >1 &OHgr;cm without back-surface coating, the epitaxial layer of which semiconductor wafer has a resistance inhomogeneity of <10%.

Abstract: In the case in which a ZnO based oxide semiconductor layer is to be hetero-epitaxially grown on a substrate formed of a material which is different from that of a ZnO based oxide semiconductor, the ZnO based oxide semiconductor layer is grown at a high temperature of 500° C. or more, and supply of oxygen is stopped and gradual cooling is carried out until a substrate temperature is lowered to 350° C. or less after the growth of the ZnO based oxide semiconductor layer is completed. As a result, it is possible to suppress the generation of dislocations or crystal defects over an epitaxial grown layer based on the atmosphere while the substrate temperature is lowered after the growth of the semiconductor layer and a difference in a coefficient of thermal expansion, thereby obtaining a semiconductor device having a high quality ZnO based oxide semiconductor layer which has an excellent crystalline property and a semiconductor light emitting device having the high characteristics.

Abstract: A method of forming a single crystal semiconductor film on a non-crystalline surface is described. In accordance with this method, a template layer incorporating an ordered array of nucleation sites is deposited on the non-crystalline surface, and the single crystal semiconductor film is formed on the non-crystalline surface from the ordered array of nucleation sites. An integrated circuit incorporating one or more single crystal semiconductor layers formed by this method also is described.